Download QUEUED SERIAL MODULE Reference Manual

Freescale Semiconductor, Inc.
DSCKL — Delay before SCK
This bit determines the length of time the QSPI delays from peripheral chip-select
(PCS) valid to SCK transition for serial transfers in which the command control bit,
DSCK of the QSPI RAM, equals one.
PCS to SCK Delay = [DSCKL/System Clock Frequency]
where DSCKL equals {1,2,3,... 127}.
DTL — Length of Delay after Transfer
These bits determine the length of time that the QSPI delays after each serial transfer
in which the command control bit, DT of the QSPI RAM, equals one.
Delay after Transfer = [(32 * DTL)/System Clock Frequency]
Freescale Semiconductor, Inc...
where DTL equals {1,2,3,... 255}.
SPCR2 — QSPI Control Register 2
15
14
13
12
SPIFIE
WREN
WRTO
0
0
0
0
11
$YFFC1C
10
9
8
ENDQP
7
6
5
4
0
0
0
0
0
0
0
0
3
2
1
0
NEWQP
RESET:
0
0
0
0
0
0
0
0
0
SPIFIE — SPI Finished Interrupt Enable
1 = QSPI interrupts enabled
0 = QSPI interrupts disabled
WREN — Wrap Enable
1 = Wraparound mode enabled
0 = Wraparound mode disabled
WRTO — Wrap To
1 = Wrap to address found in NEWQP
0 = Wrap to address $0
Bit 12 — Not Implemented
ENDQP — Ending Queue Pointer
This field determines the last absolute address in the queue to be completed by the
QSPI.
Bits [7:4] — Not Implemented
NEWQP — New Queue Pointer Value
NEWQP determines which queue entry the QSPI transfers first.
SPCR3 — QSPI Control Register 3
15
14
13
12
11
0
0
0
0
0
0
0
0
0
10
$YFFC1E
9
LOOP HMIE
Q
8
HALT
7
0
SPSR*
RESET:
0
0
0
0
* SPSR — QSPI Status Register
QSM
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