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UM10755 PTN3355 (e)DP to VGA bridge IC application board Rev. 1 — 19 January 2015 User manual Document information Info Content Keywords PTN3355, PTN3393, DisplayPort, eDP, VGA, bridge, application board Abstract This user manual presents demonstration / application board capability of interfacing an (embedded) DisplayPort source to VGA output. The application board (nicknamed "ULT DPVGA") is intended for use as an evaluation and customer demonstration tool, as well as a reference design. UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board Revision history Rev Date Description 1 20150119 Initial version. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] UM10755 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 2 of 19 UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board 1. Introduction PTN3355 is a low-power DisplayPort to VGA bridge IC with an integrated 1-2 VGA switch. PTN3355 consumes approximately 200 mW of power for video streaming in WUXGA resolution and 890 uW of power in low-power mode. The VGA output is powered down when there is no valid DisplayPort source data being transmitted. PTN3355 is suitable for Ultra Low Power Notebook and other low-power devices. PTN3355 also offers a second VGA port for docking design. PTN3355 is powered from a 3.3 V power source, and generates 1.5 V through an internal step-down switch regulator and buck converter for internal core usage and DAC usage. For cost saving, the external inductor for the buck converter can be removed; the internal LDO can supply 1.5 V for core usage and DAC usage without any re-work. However, using LDO consumes twice as much as the buck converter, about 400 mW. This document describes the user manual of PTN3355 ULT DP-VGA application board, including: • Overall PCB connectors, jumpers, and power supplies • Equipment/Tools that this board will be interfacing with for board testing • System level connections such as cables and connectors that this board will be plugged into This application board is intended to demonstrate the bridging capabilities of PTN3355 on low power DP to VGA conversion. 1.1 Purposes This document is for internal engineers to evaluate the performance of PTN3355 and to develop firmware, including collecting and verifying system level features/performances/functionalities such as: • • • • • • Verify power management schemes Power sequence Power consumption measurement during various operating modes. Allow access to test points and jumpers for measurement and configuration purposes Flash over AUX and MS_I2C Programming and debug test via MS_I2C For marketing to demonstrate ULT DP-VGA to customers in the field: • • • • • UM10755 User manual Functional and interoperability test. This board should be connected to a DP or an eDP source. This board can be powered by an external 3V3 power adapter, or External power supplies with +3.3V (1A), or DP 1.0 cable that carries 3V3 power. All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 3 of 19 UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board For customers to evaluate PTN3355: • Use I2C to change configuration. 2. General description 2.1 Co-layout of PTN3355 with PTN3393 This application board is designed to evaluate PTN3393 first then PTN3355 later with component stuffing variation. An HVQFN40 socket footprint is reserved in preparation for socket installation to test and program ICs. Due to the bulky socket footprint, the bulk converter design has to be placed on the back side to be close to PTN3355. Also due to co-layout for two ICs, extra components are necessary for stuffing option. Hence the layout is not optimal as if only PTN3355 is placed without the socket. The placement can be dramatically improved in a real application. 2.2 Block diagram 4.5" VGA CONNECTOR2 1.5V 4.7uF 3.3V 39,38 1,5,21 2-DP (e)DP INTF 36,35 VGA2 B G R VGA1 8 AUX PTN3355 (6x6 mm) in Socket H/V Sync DDC_I2C VGA CONNECTOR1 4.7uH GND 3.5" HPD I2C_BUS JTAG DDC_I2C SM_BUS sEEPROM CFG um10755_bd Fig 1. ULT DP-VGA application board block diagram UM10755 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 4 of 19 UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board um10755_appboard Fig 2. PTN3393 application board UM10755 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 5 of 19 UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board um10755_3355appboard Fig 3. PTN3355 application board 2.3 PTN3355 ULT DP-VGA application board features UM10755 User manual • • • • • • • Stuff options for PT3393 or PTN3355. • • • • • • • One I2C header for DDC control. Groups of jumpers for pin configuration. Other jumpers for test options. One reset button. Power LED. HPD LED. One I2C header bringing out I2C pins (SCL, SDA, GND) to interface with a I2C-Bird dongle to program (Flash over I2C) and debug. One JTAG for FW download. One 3V3 power adapter jack. Test point for external power supplies 3.3 V (1A). Option to power from DP connector. Jumper to select between 3 power sources Two VGA connectors selectable by jumper setting. All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 6 of 19 UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board 3. Hardware requirements • • • • • • Item 1 - (e)DP sources of Intel, AMD, Apple Item 2 - VTG5225-DP or DPT-200, DP sources with DP 1.1 or DP1.0 cable Item 3 - DPA-400, AUX analyzer Item 4 - Different native resolution monitors Item 5 - FS2 with 2x5 JTAG connection for FW download Item 6 - I2C Bird with 1x4 header connection for s-EEPROM R/W 4. Board specifications 4.1 General description • • • • • Layers: 4 layers expected - trace, ground, VCC, trace Size: 3.5" x 4.5" Material: FR4 Thickness: 62 mil Impedance: 50 ohm single-end, 75 ohm single-end RGB, 100 ohm differential on DP and AUX signal pairs. 4.2 PCB stack ups um10755_pcbstackup Fig 4. ULT DP-VGA Application Board PCB Stack Up example UM10755 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 7 of 19 UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board 4.3 Top assembly drawings of the PTN3355 Application Board um10755_topass Fig 5. PTN3355 application board top assembly drawings UM10755 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 8 of 19 UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board 4.4 Bottom assembly drawings of the PTN3355 Application Board um10755_botass Fig 6. PTN3355 application board bottom assembly drawings 5. Connector specifications 5.1 Connectors and jumpers Table 1. Connectors and jumpers Jumper number Jumper name Connector name Manufacturer Part number J1 DP CONN SINK DP RCPT 20 POS Molex 47272-0001 J2 POWER JACK CONN JACK POWER 2.1MM PC CUI PJ-102A J3,J4 VGA_CONN CONN D-SUB RCPT 15POS HD R/A EDAC 634-015-274-992 J5,J7 HEADER 4 CONN HEADER .100 SINGL STR 4POS Sullins PBC04SAAN UM10755 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 9 of 19 UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board Table 1. Connectors and jumpers …continued Jumper number Jumper name Connector name Manufacturer Part number J6 HEADER, 2x5 CONN HEADER .100 DUAL STR 10POS Sullins PBC05DAAN J8,J10,J11 CON1 CONN HEADER .100 SINGL STR 1POS Sullins PBC01SAAN JP1,JP3,JP4,JP5,JP6, HEADER 3 JP7,JP8,JP9,JP10 CONN HEADER .100 SINGL STR 3POS Sullins PBC03SAAN JP2 CONN HEADER .100 SINGL STR 2POS Sullins PBC02SAAN HEADER 2 5.2 Cables • DP 1.0 cable to power the application board • DP 1.1 cable for DP communication only • VGA cable 5.3 Jumper settings Table 2. Jumper settings Jumper number Signal Names Jumper Settings Default Setting JP1 +3V3_IC 1-2, select external power to measure 2-3 JP2 HPD_ON 1-2 Enable HPD LED JP3 + J8 +3V3_FB 2-3, select 3-1 power source 1-2 OPEN: Disable HPD LED 1-2, Select 3V3 power adapter 1-2 2-3, Select external power supply JP3-2 to J8-1, Select DP power JP4 TESTMODE 1-2 HIGH, CFG[5:1] = JTAG PINS 2-3 2-3 LOW, CFG[5:1] = CONFIG PINS. I2C = 40H OPEN, CFG[5:1] = CONFIG PINS. I2C = C0H JP5 CFG5_TCK 1-2 HIGH, 33 MHZ XTAL is used OPEN OPEN, 27 MHZ XTAL is used 2-3 LOW, 25 MHZ XTAL is used JP6 DOCK_IN 1-2 HIGH, Select VGA2 JP7 CFG1-MS_SCL/TDI CFG1, CFG2: OPEN 2-3 LOW or OPEN, Select VGA1 2-3 11: Compliant HPD behavior, MS Bus is used 10: Non-compliant HPD behavior UM10755 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 10 of 19 UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board Table 2. Jumper settings …continued Jumper number Signal Names Jumper Settings Default Setting JP9 CFG2-MS_SDA/TMS 01: Non-compliant HPD behavior 2-3 00: Compliant HPD behavior, MS bus is not used JP8 WP 1-2 HIGH, WP for S-EEPROM JP10 CFG3-FLT/TDO 1-2 HIGH, Support FLT 2-3 2-3 LOW, No WP S-EEPROM 2-3 2-3 LOW or OPEN, No FLT support 6. Power options PTN3355_3393 application board can be powered by three different methods. 6.1 DP 1.0 cable Set JP3-2 to J8-1 to select DP power um10755_powerbydp Fig 7. Power by DP 1.0 cable 6.2 3.3 V power adapter Set JP3 pin 2 to pin 1 to select 3V3 power adapter UM10755 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 11 of 19 UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board um10755_powerby3v3 Fig 8. Power by 3.3 V power adapter 6.3 External power source Set JP3 pin 2 to pin 3 to select external 3.3V power supply. Clip 3.3V power lead to TP5, and clip ground lead to GND test point. UM10755 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 12 of 19 UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board um10755_extpwrsrc Fig 9. Power by external 3.3 V power supply (1 of 2) UM10755 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 13 of 19 UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board um10755_pwrext3v3 Fig 10. Power by external 3.3 V power supply (2 of 2) UM10755 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 14 of 19 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors UM10755 7.1 PTN3393 stuffing VCORE C2 0.1uF C3 4.7uF 2 4 + 2 1 1 2 2 OSC_IN LDOCAP_DIG OSC_OUT VCORE 1 0 RED1 RED 32 RED2 34 OSC_IN OSC_IN 35 36 33 OSC_OUT OSC_OUT NC4 VDDA33_DAC BLU2 BLU BLU1 HSYNC HSYNC1 VSYNC VSYNC1 29 GRN2 28 GRN 27 VDDA_DAC 26 BLU 25 HSYNC DNL 24 VSYNC 23 DDC_SCL2 22 DDC_SDA BLU2 BLU SCH[2] SCH[2] HSYNC SCH[2] VSYNC SCH[2] DDC_SCL2 SCH[2] DDC_SDA SCH[2,4] 21 1 VDD_3V3 DDC_SDA2 DDC_SDA2 SCH[2] C20 0.1uF 2 DDC_SDA2 1 C11 0.1uF HPD DNL CLK_O PLACE NEAR PIN 14 DDC_SCL MS_SDA/TMS TP_WHITE DDC_SCL DDC_SCL SCH[2,4] Title PTN3393 DPVGA Demo Board Stuff Option MS_SCL/TDI MS_SDA/TMS TP1 CLK_O_33 DNL DNL VDD_3V3 2 2 SCH[2] 1 VDDA_DP DNL C18 2.2uF_10V RST SW SCH[2] GRN TRST_N VDD_3V3 0 INTERNAL PULL UP 1 2 PB-SPST-MOM GRN2 PLACE NEAR PIN 21 2 0 R21 TDI_33 2 R12 2 1 C22 1uF 1 4 2 1.20K 1% HSYNC2 VSYNC2 HSYNC2 VSYNC2 SCH[2] SCH[2] Size Date: Document Number Wednesday, July 25, 2012 Rev 1.0 Sheet 2 of 5 um10755_3393stuffing Fig 11. PTN3393 stuffing option design UM10755 15 of 19 © NXP Semiconductors N.V. 2015. All rights reserved. J10 CON1 1 RST_N PLACE NEAR PIN 8 RST_N 1 R8 GND TRSTn RSET 41 DNL PTN3393 1 0 31 GRN1 30 TRST_N SW1 3 2 1 R19 VDDA_DAC 2 TESTMODE PVDD33 1 10K R6 2 37 S0 TESTMODE LDOCAP_DIG VDDA15_DAC GRN2 20 DNL NC3 DDC_SCL1 DDC_SCL TDI_33 19 MS_SDA/TMS TRST_N 2 0 RSET VDDD33_IO VDDE33_IO 18 SCH[4] SCH[4] 1 R20 MS_SDA/TMS 17 MS_SCL/TDI SCH[2] SCH[2] PLACE NEAR PIN 27 RSET DDC_SDA DDC_SDA1 HSYNC2 TDI CFG5_TCK CFG5_TCK 38 DNL VBUCK_1V5 SCH[4] PVDD33 ML1_N ML1_N HPD SCH[4] S1 40 ML1_P CFG3_TDO CFG3_TDO PGND NC1 ML1_P RED2 RED C15 0.1uF NC2 DDC_SCL2 VDDA15_DP 16 SCH[4] 10 CFG3_TDO ML1_N HPD 9 ML1_N ML0_N 15 SCH[3] SCH[3] ML1_P ML0_N PLACE NEAR PIN 36 (PTN3393) 14 REMOVE L2, PLACE CURRENT METER ACCROSS +3V3_IC AND VDD_3V3 ML1_P ML0_P L3 FB 1 TP_RED SCH[3] ML0_P RST_N 1 1 TP_RED TP21 PRX C9 2.2uF_10V RED VSYNC2 8 AUX_N VDDE33_IO VDD_3V3 RED2 CFG2_SDA/TMS TMS 7 ML0_N AUX_N C8 0.1uF GRN CFG1_SCL/TDIVDDA33_DP 6 VBUCK_1V5 TP6 5 AUX_P CFG5_TCK ML0_N ML0_P 2 12.0K 1% AUX_P VDDA_DP SCH[3] VDDE33 1 R11 CFG0/DOCK_IN LDOCAP_AUX HPD VDD_3V3 4 DNL VDD_3V3 LDOCAP_AUX ML0_P 2 3 AUX_N VDD_3V3 SCH[3] 2 0 HPD AUX_N 1 R9 RST_N SCH[3] DOCK_IN LDOCAP_AUX AUX_P 11 DOCK_IN AUX_P CLK_O_33 +3V3_IC SCH[4] SCH[3] VDDA33_DNW VDDA33_AUX HPD 1 SWOUT DOCK_IN=0, SELECT VGA1 DOCK_IN=1, SELECT VGA2 VDDA_3V3 S2 PTN3393 DDC_SDA2CLK_O PLACE NEAR PIN 5 TO MEASURE IC POWER APPLY EXTERNAL PWR TO PIN1 NORMAL OP: PIN2-PIN3 S3 U1 PLACE NEAR PIN 2 JP1 HEADER 3 39 1 DOCK_IN 0.01uF 13 1 2 3 DNL DNL 2 C17 +3V3_IC DNL 2.2uF_10V 1 LDOCAP_AUX VBUCK_1V5 PTN3355 (e)DP to VGA bridge IC application board Rev. 1 — 19 January 2015 All information provided in this document is subject to legal disclaimers. C16 2 R6=10K FOR 3393, DNL R6=0 FOR 3355. LOAD VDDE33 2 R3 VDD_3V3 DOCK_IN LDOCAP_AUX CFG3/TDO TDO +3V3 VDDD15 TESTMODE S3 +3V3_PWR SCH[4] CON1 2 12pF DNL LDOCAP_DIG VDD_3V3 VDDD33_CORE SWOUT +3V3_IC 1 C4 1 PLACE NEAR PIN 36 PLACE NEAR PIN 1 DOUBLE FOOTPRINT FOR Y1 2016 AND 3225 PARTS TO TEST: 2016 XTAL 3225 XTAL: ECS-270-20-33 3225 OSC: TXC AU-27.000MBE J11 1 DNL PLACE NEAR PIN 38 2 12pF 1 1 C14 0.01uF 2 1 C13 0.1uF 2 1 1 C12 2.2uF_10V DNL 2 DNL 2 2 C58 0.1uF 1 FB FB C5 2.2uF_10V Y1 27MHz-6pF 2 3 2 2 1 1 2 1 1 L4 L2 1 C1 VBUCK_1V5 DAC_33 1 VDDA_3V3 1 VDD_3V3 CFG5/TCK TCK VDD_3V3 1 REMOVE R62, PLACE CURRENT METER ACCROSS VBUCK_1V5 AND J9 PVDD33 +3V3_IC 12 User manual 7. Stuffing options xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx REMOVE R62, PLACE CURRENT METER ACCROSS VBUCK_1V5 AND J9 3 1 R4 R6 RED2 RED1 RED HSYNC1 VSYNC VSYNC1 GRN2 28 GRN 27 VDDA_DAC 26 BLU 25 HSYNC 24 GRN2 1 R18 23 DDC_SCL2 22 DDC_SDA SCH[2] GRN SCH[2] BLU2 BLU SCH[2] SCH[2] HSYNC SCH[2] VSYNC SCH[2] DDC_SCL2 SCH[2] DDC_SDA SCH[2,4] 21 GND 1 VDD_3V3 DDC_SDA2 DDC_SDA2 SCH[2] C20 0.1uF 2 DDC_SDA2 1 R17 TP_WHITE DDC_SCL DDC_SCL SCH[2,4] TP1 CLK_O_33 TRST_N 2 R15 2 R16 1 CLK_O 2 0 HPD Title 0 MS_SDA/TMS PTN3355 DPVGA Demo Board Stuff Option 0 0 MS_SCL/TDI PLACE NEAR PIN 14 2 0 VSYNC VDD_3V3 2 C18 2.2uF_10V RST SW VDDA_DP 2 R13 VDD_3V3 PB-SPST-MOM 1 INTERNAL PULL UP TRST_N 1 2 HSYNC TDI_33 1 4 BLU1 29 2 1.20K 1% HSYNC2 VSYNC2 HSYNC2 VSYNC2 SCH[2] SCH[2] Size Date: Document Number Monday, January 13, 2014 Rev 1.4 Sheet 2 of 5 um10755_3355stuffing Fig 12. PTN3355 stuffing option design UM10755 16 of 19 © NXP Semiconductors N.V. 2015. All rights reserved. RST_N BLU2 BLU 1 R8 RSET PLACE NEAR PIN 21 J10 CON1 1 NC4 32 33 OSC_IN 34 OSC_OUT OSC_IN VCORE 35 LDOCAP_DIG VDDA15_DAC TESTMODE 37 36 VDDD15 VDDD33_CORE S0 TESTMODE PVDD33 1 38 PVDD33 S1 RST_N 1 39 PGND 40 PTN3355 PLACE NEAR PIN 8 SW1 3 GRN1 30 1 0.01uF VDDA_DAC 41 0.1uF SCH[2] SCH[2] DDC_SCL TRST_N HSYNC2 TDI 1 C10 19 TRST_N C21 MS_SDA/TMS 1 SCH[4] TDI_33 TRSTn MS_SDA/TMS CFG5_TCK GRN2 VDDD33_IO VDDE33_IO VSYNC2 SCH[4] CFG3_TDO CFG2_SDA/TMS TMS MS_SCL/TDI ML1_N 18 CFG5_TCK SCH[4] ML1_N VBUCK_1V5 NC3 DDC_SDA DDC_SDA1 17 SCH[4] ML1_P MS_SDA/TMS CFG3_TDO NC1 HPD RSET NC2 DDC_SCL2 VDDA15_DP ML1_P 16 SCH[4] ML0_N RED PLACE NEAR PIN 27 RSET VDDA33_DAC (PTN3393) CFG3_TDO ML1_N HPD 2 REMOVE L2, PLACE CURRENT METER ACCROSS +3V3_IC AND VDD_3V3 10 ML1_N SCH[3] SCH[3] 1 TP_RED 9 ML1_P 2 1 1 TP_RED TP21 ML0_N RED2 RED CFG3/TDO TDO 8 VBUCK_1V5 TP6 ML0_P PLACE NEAR PIN 36 RED2 CFG5/TCK TCK 7 ML0_P CFG1_SCL/TDIVDDA33_DP ML1_P ML0_N PRX 15 SCH[3] 6 AUX_N VDDE33_IO 14 ML0_N ML0_P AUX_N CFG5_TCK SCH[3] 5 0 C8 0.1uF GRN VDDA_DP ML0_P VDDE33 AUX_P 13 SCH[3] 2 0 1 R10 VDD_3V3 LDOCAP_AUX AUX_P HPD 4 AUX_N CFG0/DOCK_IN LDOCAP_AUX HPD VDD_3V3 3 RST_N AUX_N VDD_3V3 2 RST_N SCH[3] DOCK_IN LDOCAP_AUX AUX_P 11 +3V3_IC AUX_P CLK_O_33 +3V3_IC DOCK_IN SCH[3] VDDA33_DNW VDDA33_AUX HPD 1 SWOUT DOCK_IN=0, SELECT VGA1 DOCK_IN=1, SELECT VGA2 VDDA_3V3 S2 PTN3355 VDD_3V3 2 PTN3355 (e)DP to VGA bridge IC application board Rev. 1 — 19 January 2015 All information provided in this document is subject to legal disclaimers. PLACE NEAR PIN 5 TO MEASURE IC POWER APPLY EXTERNAL PWR TO PIN1 NORMAL OP: PIN2-PIN3 SCH[4] 0 U1 PLACE NEAR PIN 2 JP1 HEADER 3 2 S3 2 1 R7 DDC_SDA2CLK_O C19 0.1uF 12 1 1 2 3 DOCK_IN S3 0 LDOCAP_AUX OSC_OUT R6=10K FOR 3393, DNL R6=0 FOR 3355. LOAD VDDE33 OSC_IN OSC_OUT 2 DOCK_IN 1 TESTMODE VBUCK_1V5 12pF LDOCAP_DIG VDD_3V3 VDD_3V3 LDOCAP_AUX CON1 2 2 SWOUT SCH[4] 1 31 PLACE NEAR PIN 36 +3V3 1 C4 L1 PLACE NEAR PIN 1 +3V3_PWR DOUBLE FOOTPRINT FOR Y1 2016 AND 3225 PARTS TO TEST: 2016 XTAL 3225 XTAL: ECS-270-20-33 3225 OSC: TXC AU-27.000MBE J11 1 4.7uH PLACE NEAR PIN 38 +3V3_IC 1 4 + 2 12pF DAC_33 C3 4.7uF 2 1 2 1 C14 0.01uF 2 1 1 2 C13 0.1uF 1 Y1 27MHz-6pF 2 DDC_SCL1 DDC_SCL C2 0.1uF FB C12 2.2uF_10V 2 C7 1uF 2 1 C6 0.1uF C58 0.1uF 2 2 1 FB C5 2.2uF_10V 2 C1 VBUCK_1V5 1 1 2 2 1 1 1 L4 1 L2 VCORE 20 VDDA_3V3 LDOCAP_DIG VDD_3V3 VDD_3V3 2 PVDD33 +3V3_IC NXP Semiconductors UM10755 User manual 7.2 PTN3355 stuffing UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board 7.3 PTN3355_PTN3393 stuffing options table Table 3. PTN3355_PTN3393 stuffing options table Location Function/Value PTN3355 PTN3393 C6 0.1uF Load No Load C7 1uF Load No Load C16 2.2uF_10V No Load Load C17 0.01uF No Load Load C19 0.1uF Load No Load R7 0 Ohm Load No Load R9 0 Ohm No Load Load R10 0 Ohm Load No Load R11 12.0K 1% No Load Load R1 10K No Load No Load R5 10K No Load No Load R6 0 Ohm for PTN3355 Load No Load 10K for PTN3393 R3 0 Ohm No Load Load L1 4.7uH Load No Load C3 4.7uF Load No Load R4 0 Ohm Load No Load R17 0 Ohm Load No Load C22 1uF No Load Load R12 0 Ohm No Load Load R13 0 Ohm Load No Load R15 0 Ohm Load No Load R16 0 Ohm Load No Load R21 0 Ohm No Load Load R18 0 Ohm Load No Load 8. References UM10755 User manual [1] Data Specification, PTN3355.pdf, 14 July 2014 [2] Schematic, PTN3355_1.14_CONFIDENTIAL.pdf [3] BOM, PTN3355_ONLY_REV14_BOM.xls [4] AN11413-PTN3393-PTN3355 rev4.pdf [5] AN11415-PTN3355 rev1.pdf [6] Allegro layout, PTN3393 DEMO BOARD_REV1_305-PD12-0592_PCB_07-27-2012.brd All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 17 of 19 UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board 9. Legal information 9.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 9.2 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product UM10755 User manual design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Evaluation products — This product is provided on an “as is” and “with all faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 9.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 18 of 19 UM10755 NXP Semiconductors PTN3355 (e)DP to VGA bridge IC application board 10. Contents 1 1.1 2 2.1 2.2 2.3 3 4 4.1 4.2 4.3 4.4 5 5.1 5.2 5.3 6 6.1 6.2 6.3 7 7.1 7.2 7.3 8 9 9.1 9.2 9.3 10 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Purposes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 General description . . . . . . . . . . . . . . . . . . . . . . 4 Co-layout of PTN3355 with PTN3393. . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PTN3355 ULT DP-VGA application board features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Hardware requirements. . . . . . . . . . . . . . . . . . . 7 Board specifications . . . . . . . . . . . . . . . . . . . . . 7 General description . . . . . . . . . . . . . . . . . . . . . 7 PCB stack ups . . . . . . . . . . . . . . . . . . . . . . . . . 7 Top assembly drawings of the PTN3355 Application Board . . . . . . . . . . . . . . . . . . . . . . . 8 Bottom assembly drawings of the PTN3355 Application Board . . . . . . . . . . . . . . . . . . . . . . . 9 Connector specifications . . . . . . . . . . . . . . . . . 9 Connectors and jumpers . . . . . . . . . . . . . . . . . 9 Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Jumper settings . . . . . . . . . . . . . . . . . . . . . . . 10 Power options . . . . . . . . . . . . . . . . . . . . . . . . . 11 DP 1.0 cable . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 V power adapter . . . . . . . . . . . . . . . . . . . . 11 External power source . . . . . . . . . . . . . . . . . . 12 Stuffing options . . . . . . . . . . . . . . . . . . . . . . . . 15 PTN3393 stuffing . . . . . . . . . . . . . . . . . . . . . . 15 PTN3355 stuffing . . . . . . . . . . . . . . . . . . . . . . 16 PTN3355_PTN3393 stuffing options table . . . 17 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 19 January 2015 Document identifier: UM10755