Download VR Series 64-/32-Bit Microprocessor Programming Guide AN

CHAPTER 5 EXCEPTIONS
5.5.3 Multiple interrupts
In the exception processing described above, interrupts during the processing of exceptions (including interrupts)
are not supported. To enable multiple interrupts, save CP0 registers (EPC register, Status register, etc.) used during
the processing of exceptions, and set the KSU, ERL, EXL, and IE bits of the Status register to interrupt enabled.
To disable multiple interrupts after once enabling them, change the Status register in the exception processing,
and then restore the contents of the register saved.
The exception processing to enable multiple interrupts is performed in the following procedure.
(1) Saving CPU registers
Save the contents of the CPU registers used in the processing in (2), (3), (4), (5), (6), and (7) below to the
memory.
(2) Saving CP0 registers
Save the contents of the CP0 registers and EPC register used in the processing in (3), (4), and (5) below to
the memory.
(3) Setting Status register
Set the Status register to enable multiple interrupts. The following contents are set to the Status register:
KSU are: 00
ERL bit:
0
EXL bit:
0
IE bit:
1
(4) Exception processing
Perform processing to exclude the cause of the exception. If the exception cause is the register to which the
contents have been saved in (1) and (2), change the memory to which the contents have been saved,
otherwise it is reverted to the state before the exception in the restoration processing in (6) and (7).
(5) Setting Status register
Restore the contents of the Status register in (2), and disable multiple interrupts.
(6) Restoring CP0 registers
Restore the contents of the CP0 registers saved in (2).
(7) Restoring CPU registers
Restore the contents of the CPU registers saved in (1).
Application Note U10710EJ5V0AN
81