Download VR Series 64-/32-Bit Microprocessor Programming Guide AN

CHAPTER 2 CACHE
This chapter describes the method of manipulating the cache of VR Series processors.
2.1 Cache Initialization
The following describes the cache initialization procedure.
2.1.1 Cache initialization procedure
What occurs in cache initialization differs somewhat between CPUs that have parity in their cache and CPUs that
have no parity. The cache with no parity can be initialized only by clearing the V bit of the cache line (invalidating the
cache line). This is because a cache with no parity does not cause parity errors next time it is used even if the data
portion is not initialized.
The cache can be initialized in the following procedure.
(1) Cache with no parity
(a) Instruction cache
1. Invalidate the cache line using the Index_Invalidate operation of the CACHE instruction.
(b) Data cache
1. Initialize the TagLo register using the MTC0 instruction.
2. Write to the cache tag using the Index_Store_Tag operation of the CACHE instruction.
(2) Cache with parity
(a) Instruction cache
1. Set the CE bit of the Status register to 0.
2. Set the cache tag and determine the physical address managed by the cache.
3. Initialize the TagLo register using the MTC0 instruction.
4. Write to the cache tag using the Index_Store_Tag operation of the CACHE instruction.
5. Initialize data block of the cache using the Fill operation of the CACHE instruction.
6. Invalidate the cache line using the Index(Hit)_Invalidate operation of the CACHE instruction.
(b) Data cache
1. Set the CE bit of the Status register to 0.
2. Initialize the TagLo register using the MTC0 instruction.
3. Write to the cache tag using the Index_Store_Tag operation of the CACHE instruction.
4. Make the cache block Dirty Exclusive using the Create_Dirty_Exclusive operation of the CACHE
instruction.
5. Initialize data block of the cache using the SW instruction.
6. Invalidate the cache line using the Index(Hit)_Invalidate operation of the CACHE instruction.
Note that the initial value of the CP0 register used in the cache instruction is not guaranteed after reset. Set the
values of these registers before use.
92
Application Note U10710EJ5V0AN