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Download VR Series 64-/32-Bit Microprocessor Programming Guide AN
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CHAPTER 1 OUTLINE (2) 2-way superscalar pipeline Reads two instructions simultaneously, and processes them in parallel. The pipeline of the VR5000 Series, VR5432, and VR5500 uses this method. In the VR5000 Series, one of two pipelines is assigned to CPU instructions, and the other is assigned to FPU instructions, and one each of the CPU and FPU instructions are processed simultaneously. In the VR5432 and VR5500, this assignment does not occur and two instructions are processed simultaneously regardless of whether the instruction is from the CPU or FPU. Figure 1-2. Outline of 2-Way Superscalar Pipeline (5 Stages) and Instruction Execution PClock Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction IC RF EX DC WB Pipeline (3) 4-way superscalar pipeline Reads four instructions simultaneously and processes them in parallel. The pipeline of the VR10000 Series uses this method. Figure 1-3. Outline of 4-Way Superscalar Pipeline (5 Stages) and Instruction Execution Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction IF ID IS EX WB Pipeline Application Note U10710EJ5V0AN 21
