Download Xilinx ISE In-Depth Tutorial

Chapter 3: HDL-Based Design
The following third-party simulation tool is optional for this tutorial and may be used in
place of ISim:
•
ModelSim SE/PE/DE 10.1a (or above)
VHDL or Verilog
This tutorial supports both VHDL and Verilog designs and applies to both designs
simultaneously, noting differences where applicable. You will need to decide which HDL
language you would like to work through for the tutorial and download the appropriate
files for that language. XST can synthesize a mixed-language design. However, this tutorial
does not cover the mixed language feature.
Installing the Tutorial Project Files
The tutorial project files are provided with the ISE Design Suite Tutorials available from
the Xilinx website. Download either the VHDL or the Verilog design flow project files.
After you have downloaded the tutorial project files from the web, unzip the tutorial
projects into the c:\xilinx_tutorial directory, replacing any existing files in that
directory.
When you unzip the tutorial project files into c:\xilinx_tutorial, the directory
wtut_vhd (for a VHDL design flow) or wtut_ver (for a Verilog design flow) is created
within c:\xilinx_tutorial, and the tutorial files are copied into the newly-created
directory.
The following table lists the locations of tutorial source files.
Table 3-1:
Tutorial Directories
Directory
Description
wtut_vhd
Incomplete VHDL Source Files
wtut_ver
Incomplete Verilog Source Files
wtut_vhd\wtut_vhd_completed
Completed VHDL Source Files
wtut_ver\wtut_ver_completed
Completed Verilog Source Files
Note: The completed directories contain the finished HDL source files. Do not overwrite any files in
the completed directories.
This tutorial assumes that the files are unzipped under c:\xilinx_tutorial, but you
can unzip the source files into any directory with read/write permissions. If you unzip the
files into a different location, substitute your project path in the procedures that follow.
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ISE In-Depth Tutorial
UG695 (v14.1) April 24, 2012