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11.4 9-pin JTAG/SWD connector
Some target boards only provide a 9-pin JTAG/
SWD connector for Cortex-M. For these devices
SEGGER provides a 20-pin -> 9-pin Cortex-M
adapter.
VTref
1
2
SWDIO / TMS
GND
GND
3
5
4
6
SWCLK / TCK
SWO / TDO
--NC
7
9
8 TDI
10 nRESET
The following table lists the output of the 9-pin Cortex-M connector.
PIN
1
2
4
6
---
8
9
SIGNAL
TYPE
Description
This is the target reference voltage. It is used to check if
the target has power, to create the logic-level reference
VTref
Input for the input comparators and to control the output logic
levels to the target. It is normally fed from Vdd of the
target board and must not have a series resistor.
SWDIO: (Single) bi-directional data pin.
SWDIO/
I/O /
JTAG mode set input of target CPU. This pin should be
TMS
output pulled up on the target. Typically connected to TMS of the
target CPU.
SWCLK: Clock signal to target CPU. It is recommended
that this pin is pulled to a defined state of the target
SWCLK/TCK Output
board. Typically connected to TCK of target CPU.
JTAG clock signal to target CPU.
When using SWD, this pin is used as Serial Wire Output
trace port (optional, not required for SWD communicaSWO/TDO
Input tion).
JTAG data output from target CPU. Typically connected to
TDO of the target CPU.
This pin (normally pin 7) is not existent on the 19-pin
----JTAG/SWD and Trace connector.
JTAG data input of target CPU.- It is recommended that
this pin is pulled to a defined state on the target board.
Typically connected to TDI of the target CPU. For CPUs
TDI
Output
which do not provide TDI (SWD-only devices), this pin is
not used. J-Link will ignore the signal on this pin when
using SWD.
Not connected inside J-Link. Leave open on target hardNC
NC
ware.
Table 11.11: 9-pin JTAG/SWD pinout
Pins 3 and 5 are GND pins connected to GND on the Cortex-M adapter. They should
also be connected to GND in the target system.
J-Link / J-Trace (UM08001)
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