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Compiling Simulation Libraries
Use Case III: Compiling HDL Sources in Your Own Repository
If you have your own repository of EDK style pcores, you may to compile them into
<compedklib-output-dir-name> as follows:
compedklib -o <compedklib-output-dir-name>
-X <compxlib-output-dir-name>
-E <compedklib-output-dir-name>
-lp <Your-Repository-Dir>
In this form, the -E value accounts for the possibility that some of the pcores in your
repository may need to access the compiled models generated by Use Case I. This is very
likely because the pcores in your repository are likely to refer to HDL sources in the EDK
built-in repositories.
You can limit the compilation to named cores in the repository:
compedklib -o <compedklib-output-dir-name>
-X <compxlib-output-dir-name>
-E <compedklib-output-dir-name>
-lp <Your-Repository-Dir>
-lib core1
-lib core2
In this case, the entire repository is read but only the pcores indicated by the -c options are
compiled.
You can add -compile_sublibs to the above to compile the pcores that the indicated
pcore depends on.
Other Details
x
If the simulator is not indicated, then MTI is assumed.
x
You can supply multiple -X and -E arguments. The order is important. If you have
the same pcore in two places, the first one is used.
x
Some pcores are secure in that their source code is not available. In such cases, the
repository contains the compiled models. These are copied out into <compedkliboutput-dir-name>.
x
If your pcores are in your XPS project, you do not need to do Use Case II.
XPS/SIMGEN will create the scripts to compile them.
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Only VHDL is supported.
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The execution log is available in compedklib.log.
x
Starting in EDK 7.1, the file indicated by your MODELSIM environment variable is
not modified by CompEDKLib. However, the simulation scripts generated by
SIMGEN will modify the file pointed to by the MODELSIM variable.
Setting Up SmartModels
SmartModels represent integrated circuits and system buses as black boxes that accept
input stimulus and respond with appropriate output behavior. Such behavioral models
provide improved performance over gate-level models, while at the same time protecting
the proprietary designs created by semiconductor vendors. SmartModels connect to
hardware simulators through the SWIFT interface, which is integrated with over 30
commercial simulators, including Synopsys VCS, Cadence Verilog-XL, Cadence NcSim,
and Model Technology ModelSim SE/PE (1).
Platform Studio User Guide
UG113 (v4.0) February 15, 2005
www.xilinx.com
1-800-255-7778
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