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Datasheet
Core clock frequency for APIX1 Mode = 125MHz and for APIX2 Mode = 187.5MHz. All values specified for
TA=25°C. tSCK = 1/fSCK.
APIX1 Mode
Parameter
Description
fSCK
SCK Clock Frequency
tSCKH
APIX2 Mode
Min.
Max.
Min
Max
Units
-
11
-
15
MHz
SCK High Time
45
-
33
-
ns
tSCKL
SCK Low Time
45
-
33
-
ns
tCSH
CS# High Time
20
-
15
-
ns
tCSS
CS# Setup Time
1/2 tSCK
-
1/2 tSCK
-
ns
tCSHO
CS# Hold Time
50
-
34
-
ns
tDISU
Data In Setup Time
16
-
12
-
ns
tDIHO
Data in Hold Time
16
-
12
-
ns
tDOV
Data Output Valid
-
40
-
29
ns
tDOHO
Data Output Hold Time
8
-
5
-
ns
tDODIS
Data Output Disable Time
-
50
-
45
ns
tA
Data Access Time
20
-
15
-
ns
Table 1-10: SPI Slave Interface characteristics (Read Access)
APIX1 Mode
Parameter
Description
fSCK
SCK Clock Frequency
tSCKH
APIX2 Mode
Min.
Max.
Min
Max
Units
-
31
-
41
MHz
SCK High Time
1/2 tSCK
-
1/2 tSCK
-
ns
tSCKL
SCK Low Time
1/2 tSCK
-
1/2 tSCK
-
ns
tCSH
CS# High Time
20
-
15
-
ns
tCSS
CS# Setup Time
1/2 tSCK
-
1/2 tSCK
-
ns
tCSHO
CS# Hold Time
50
-
34
-
ns
tDISU
Data In Setup Time
16
-
12
-
ns
tDIHO
Data In Hold Time
16
-
12
-
ns
Table 1-11: SPI Slave Interface characteristics (Write Only Access)
DS_INAP375T Revision 1.2
Inova Semiconductors Confidential
Page 9 of 37