1
Download Hardware Components, Registers and peripheral Devices
Transcript
4 CPU OVERVIEW Mnemonic vadd.s rd,rs,rt vadd.p rd,rs,rt vadd.t rd,rs,rt vadd.q rd,rs,rt vsub.s rd,rs,rt vsub.p rd,rs,rt vsub.t rd,rs,rt vsub.q rd,rs,rt vdiv.s rd,rs,rt vdiv.p rd,rs,rt vdiv.t rd,rs,rt vdiv.q rd,rs,rt vmul.s rd,rs,rt vmul.p rd,rs,rt vmul.t rd,rs,rt vmul.q rd,rs,rt vdot.p rd,rs,rt vdot.t rd,rs,rt vdot.q rd,rs,rt vhdp.p rd,rs,rt vhdp.t rd,rs,rt vhdp.q rd,rs,rt vmin.s rd,rs,rt vmin.p rd,rs,rt vmin.t rd,rs,rt vmin.q rd,rs,rt vmax.s rd,rs,rt vmax.p rd,rs,rt vmax.t rd,rs,rt vmax.q rd,rs,rt vabs.s rd,rs vabs.p rd,rs vabs.t rd,rs vabs.q rd,rs vneg.s rd,rs vneg.p rd,rs vneg.t rd,rs vneg.q rd,rs vidt.p rd vidt.t rd vidt.q rd vzero.s rd vzero.p rd vzero.t rd vzero.q rd vone.s rd vone.p rd vone.t rd vone.q rd vrcp.s rs,rd vrcp.p rs,rd vrcp.t rs,rd vrcp.q rs,rd vrsq.s rs,rd vrsq.p rs,rd vrsq.t rs,rd vrsq.q rs,rd 46 Opcode 0x60000000 0x60000080 0x60008000 0x60008080 0x60800000 0x60800080 0x60808000 0x60808080 0x63800000 0x63800080 0x63808000 0x63808080 0x64000000 0x64000080 0x64008000 0x64008080 0x64800080 0x64808000 0x64808080 0x66000080 0x66008000 0x66008080 0x6D000000 0x6D000080 0x6D008000 0x6D008080 0x6D800000 0x6D800080 0x6D808000 0x6D808080 0xd0010000 0xd0010080 0xd0018000 0xd0018080 0xd0020000 0xd0020080 0xd0028000 0xd0028080 0xd0030080 0xd0038000 0xd0038080 0xd0060000 0xd0060080 0xd0068000 0xd0068080 0xd0070000 0xd0070080 0xd0078000 0xd0078080 0xd0100000 0xd0100080 0xd0108000 0xd0108080 0xd0110000 0xd0110080 0xd0118000 0xd0118080 op 011000 011000 011000 011000 011010 011010 011010 011010 011000 011000 011000 011000 011001 011001 011001 011001 011001 011001 011001 011001 011001 011001 011011 011011 011011 011011 011011 011011 011011 011011 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 110100 000 000 000 000 000 000 000 000 111 111 111 111 000 000 000 000 001 001 001 100 100 100 010 010 010 010 011 011 011 011 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 rt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt ttttttt 0000001 0000001 0000001 0000001 0000010 0000010 0000010 0000010 0000011 0000011 0000011 0000110 0000110 0000110 0000110 0000111 0000111 0000111 0000111 0010000 0010000 0010000 0010000 0010001 0010001 0010001 0010001 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 rs sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 sssssss sssssss sssssss sssssss sssssss sssssss sssssss sssssss 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 rd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd ddddddd Description SetVectorZero.Single SetVectorZero.Pair SetVectorZero.Triple SetVectorZero.Quad SetVectorOne.Single SetVectorOne.Pair SetVectorOne.Triple SetVectorOne.Quad
