Download MPC7450 RISC Microprocessor Family Product Brief

MPC7450 Microprocessor Features
The L2 cache controller contains the L2 cache control register (L2CR), which does the following:
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Includes bits for enabling parity checking on the L2
Provides for instruction-only and data-only modes
Provides hardware flushing for the L2
Selects between two available replacement algorithms for the L2 cache
The L2 implements the MESI cache coherency protocol using three status bits per sector.
Requests from the L1 cache generally result from instruction misses, data load or store misses, write-through
operations, or cache management instructions. Requests from the L1 cache are compared against the L2 tags and
serviced by the L2 cache if they hit; if they miss in the L2 cache, they are forwarded to the L3 cache.
The L2 cache tags are fully pipelined and non-blocking for efficient operation. Thus the L2 cache can be accessed
internally while a load for a miss is pending (allowing hits under misses). A reload for a cache miss is treated as a
normal access and blocks other accesses for only 1 cycle.
For more information, see Chapter 3, “L1, L2, and L3 Cache Operation,”of the MPC7450 RISC Microprocessor
Family User’s Manual.
2.6 L3 Cache Implementation
The unified L3 cache receives memory requests from L1 and L2 instruction and data caches independently. The L3
cache interface is implemented with an on-chip, two-way set associative tag memory with 2,048 (2K) tags per way
and a dedicated interface with support for up to 2 Mbytes of external synchronous SRAMs. Note that the L3 cache
is not supported on the MPC7441, MPC7445, MPC7447, MPC7447A, and the MPC7448
Tags are sectored to support either two or four cache blocks per tag entry, depending on the L2 cache size. Each
sector (32-byte cache block) in the L3 cache has three status bits that are used to implement the MESI cache
coherency protocol. Accesses to the L3 cache can be designated as write-back or write-through, and the L3
maintains cache coherency through snooping.
The L3 interface can be configured to use 1 or 2 Mbytes of the SRAM area as a private memory space. The
MPC7457 in particular can support 1,2, or 4 Mbytes of private memory. Accesses to private memory do not
propagate to the system bus. The MPC7450 can also be configured to use 1 Mbyte of SRAM as L3 cache and a
second Mbyte as private memory. Also, in this case, private memory accesses do not propagate to the L3 cache or
the external system bus.
The private memory space provides a low-latency, high-bandwidth area for critical data or instructions. Accesses to
the private memory space do not propagate to the L3 cache nor are they visible to the external system bus. The
private memory space is also not snooped, so the coherency of its contents must be maintained by software or not
at all. For more information, see Chapter 3, “L1, L2, and L3 Cache Operation,”of the MPC7450 RISC
Microprocessor Family User’s Manual.
The L3 cache control register (L3CR) provides control of L3 cache configuration and interface timing. The L3
private memory control register (L3PM) configures the private memory feature.
The L3 cache interface provides two clock outputs that allow the clock inputs of the SRAMs to be driven at select
frequency divisions of the processor core frequency. For the MPC7457, the L3 cache interface provides two sets of
two differential clock outputs.
Requests from the L3 cache generally result from instruction misses, data load or store misses, write-through
operations, or cache management instructions. Requests from the L1 and L2 cache are compared against the L3 tags
and serviced by the L3 cache if they hit; if they miss in the L3 cache, they are forwarded to the bus interface. Note
MPC7450 RISC Microprocessor Family Product Brief, Rev. 5
Freescale Semiconductor
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