Download MPC7450 RISC Microprocessor Family User`s Manual

TABLES
Table
Number
Title
Page
Number
5-5
MPC7451 Microprocessor Instruction Summary—Control MMUs .......................... 5-22
5-6
MPC7451 Microprocessor MMU Registers ............................................................... 5-24
5-7
BAT Registers—Field and Bit Descriptions for Extended Addressing...................... 5-28
5-8
Upper BAT Register Block Size Mask Encoding....................................................... 5-29
5-9
Upper BAT Register Block Size Mask Encoding when the Extended Block Size is Enabled (HID0[XBBSEN] = 1)5-32
5-10
PTE Bit Definitions..................................................................................................... 5-38
5-11
Table Search Operations to Update History Bits—TLB Hit Case ............................. 5-39
5-12
Model for Guaranteed R and C Bit Settings ............................................................... 5-42
5-13
SDR1 Register Bit Settings—Extended Addressing .................................................. 5-52
5-14
Minimum Recommended Page Table Sizes—Extended Addressing......................... 5-53
5-15
Implementation-Specific Resources for Software Table Search Operations.............. 5-68
5-16
Implementation-Specific SRR1 Bits........................................................................... 5-69
5-17
TLBMISS Register—Field and Bit Descriptions ....................................................... 5-70
5-18
PTEHI and PTELO Bit Definitions ............................................................................ 5-71
6-1
Performance Effects of Memory Operand Placement ................................................ 6-38
6-2
Branch Operation Execution Latencies ...................................................................... 6-45
6-3
System Operation Instruction Execution Latencies.................................................... 6-45
6-4
Condition Register Logical Execution Latencies ....................................................... 6-46
6-5
Integer Unit Execution Latencies................................................................................ 6-46
6-6
Floating-Point Unit (FPU) Execution Latencies......................................................... 6-48
6-7
Load/Store Unit (LSU) Instruction Latencies............................................................. 6-50
6-8
AltiVec Instruction Latencies ..................................................................................... 6-52
6-9
Fetch Alignment Example .......................................................................................... 6-59
6-10
Loop Example—Three Iterations ............................................................................... 6-60
6-11
Branch-Taken Bubble Example.................................................................................. 6-60
6-12
Eliminating the Branch-Taken Bubble ....................................................................... 6-61
6-13
Misprediction Example............................................................................................... 6-61
6-14
Three Iterations of Code Loop.................................................................................... 6-62
6-15
Code Loop Example Using CTR ................................................................................ 6-63
6-16
Link Stack Example.................................................................................................... 6-65
6-17
Position-Independent Code Example.......................................................................... 6-66
6-18
Dispatch Stall Due to Rename Availability ................................................................ 6-68
6-19
Load/Store Multiple Micro Operation Generation Example ...................................... 6-69
6-20
GIQ Timing Example ................................................................................................. 6-70
6-21
VIQ Timing Example ................................................................................................. 6-71
6-22
Serialization Example ................................................................................................. 6-72
6-23
IU1 Timing Example .................................................................................................. 6-73
6-24
FPU Timing Example ................................................................................................. 6-74
6-25
FPSCR Rename Timing Example .............................................................................. 6-75
6-26
Vector Execution Latencies ........................................................................................ 6-76
6-27
Vector Unit Example .................................................................................................. 6-76
6-28
Load Hit Pipeline Example......................................................................................... 6-78
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MPC7450 RISC Microprocessor Family User’s Manual
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