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Download C8051F58x/F59x
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C8051F58x/F59x 6. 12-Bit ADC (ADC0) ADC0TK ADC0CN AD0PWR3 AD0PWR2 AD0PWR1 AD0PWR0 AD0TM1 AD0TM0 AD0TK1 AD0TK0 AD0EN BURSTEN AD0INT AD0BUSY AD0WINT AD0LJST AD0CM1 AD0CM0 The ADC0 on the C8051F58x/F59x consists of an analog multiplexer (AMUX0) with 35/28 total input selections and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, programmable window detector, programmable attenuation (1:2), and hardware accumulator. The ADC0 subsystem has a special Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. The AMUX0, data conversion modes, and window detector are all configurable under software control via the Special Function Registers shows in Figure 6.1. ADC0 inputs are single-ended and may be configured to measure P0.0P3.7, the Temperature Sensor output, VDD, or GND with respect to GND. The voltage reference for ADC0 is selected as described in Section “7. Temperature Sensor” on page 74. ADC0 is enabled when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing conversions in Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode conversions are taking place. Start Conversion P0.7 P1.0 Burst Mode Oscillator 25 MHz Max P1.7 P2.0 Burst Mode Logic 12-Bit SAR Selectable Gain ADC 35-to-1 AMUX0 P2.7 P3.0 P3.1* Start Conversion ADC0GNH ADC0GNL ADC0GNA 00 AD0BUSY (W) 01 Timer 1 Overflow 10 CNVSTR Input 11 Timer 2 Overflow ADC0L SYSCLK VDD FCLK P0.0 Accumulator AD0TM1:0 AD0PRE AD0POST FCLK REF *Available on 48-pin and 40-pin packages ADC0H ADC0MX4 ADC0MX3 ADC0MX2 ADC0MX1 ADC0MX0 ADC0MX AD0WINT VDD Temp Sensor GND AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0RPT1 AD0RPT0 GAINEN P3.7* ADC0LTH ADC0LTL ADC0CF ADC0GTH ADC0GTL 32 Window Compare Logic Figure 6.1. ADC0 Functional Block Diagram Rev. 1.3 54
