Download EFM32-G8XX-DK User Manual - Digi-Key

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USER MANUAL
Development Kit EFM32-G8XX-DK
Feature rich development platform for evaluation, prototyping and application
development for the EFM32 Gecko MCU family with the ARMCortex-M3 CPU core.
Main features;
• Advanced Energy Monitoring provides real-time visibility into the energy
consumption of an application or prototype design.
• Exchangeable prototyping board for custom application development
• On-board emulator with debug out functionality
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1 Introduction
1.1 Features
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Advanced Energy Monitoring system for precise current tracking.
Special hardware configuration for isolation of the MCU power domain.
Replaceable prototyping board for quick custom application development.
Full feature USB debugger / emulator with debug out functionality.
3.5-inch TFT-LCD 320x200 pixel RGB color display.
Board Controller for board configuration / signal routing.
Single ended and differential ADC inputs.
Line-in stereo audio input amplifier.
Line-out stereo audio output amplifier.
2 RS232 connectors.
3-axis accelerometer.
SPI Flash and microSD card reader (SPI mode).
EEPROM.
Temperature sensor.
IrDA tranceiver.
256Kx16bit / 512KB parallel bus SRAM.
2Mx16 / 4MB parallel bus NOR Flash.
Ambient light sensor and potmeter.
5 way joystick.
4 User buttons, 8-bit DIP switch and 16 user LEDs.
1.2 Board Configuration
The EFM32-G8XX-DK is a highly flexible development kit. It offers many features and peripherals to the
EFM32 through jumperless configuration. The different features on the kit are available as configured
in the motherboard's Board Controller. Configuration is easily done by a simple API in the kit Board
Support Package.
If none of the motherboard features are needed, configuration of the Board Controller is not necessary.
All EFM32 GPIO pins are available on the prototyping board.
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2 Kit Block Diagram
An overview of the Kit is shown in the block diagram below.
Figure 2.1. EFM32-G8XX-DK Block Diagram
IrDA
RS232 A
RS232 B
TXD
RXD
CTS
RTS
EFM32 Prototyping Board
90
90
TXD
RXD
RS232 Level
Shifter
Serial
USART
8
Analog out
DAC
Line out
2
2
160 seg LCD
Display
(optional)
Analog in
ADC
8
SPI
SPI Bus
Line in
2
SPI Flash
4
EFM32
Microcontroller
I2C
I2C Bus
Analog Inputs
2
4
EEPROM
EFM3 2
MCU Reset
BC Bus
28
EFM32 Microcontroller Board
Accelerom eter
Tem perature
Sensor
BC Bus Connect
3
2
Am bient light
System
Reset
NOR Flash
Potentiom eter
SRAM
4
Board Control
40
SPI
Debug In/ Out
4
14
MicroSD
SPI Flash
DISPLAY
8
5
4
16
USB
320x 240 TFT- LCD
DIP- switches
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Pushbuttons
3
joystick
AEM
User LEDs
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3 Mainboard hardware layout
The layout of the EFM32-G8XX-DK mainboard is shown below.
Figure 3.1. EFM32-G8XX-DK hardware layout
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4 Power supply
4.1 USB
The EFM32-G8XX-DK can get it's power from the standard USB 2.0 Type B port located on the
motherboard. The USB hub the kit is connected to needs to be able to deliver 500 mA (5 unit loads).
4.2 External power supply
By using the DC jack plug located on the motherboard, the EFM32-G8XX-DK can be powered by an
external power supply. The voltage must be 5V and the supply must be able to deliver 500mA.
The power jack dimensions should be a standard 5.5 mm outer diameter and 2.1 mm inner diameter.
The tip is 5V and the sleeve is GND.
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5 Reset infrastructure
5.1 MCU
The primary user reset for the MCU is the reset button on the MCU board. This will only reset the MCU.
It can also be reset using the board controller, by writing to the RESET_MCU bit in the RESET register.
Finally, it can be reset by debuggers.
5.2 Board controller
The board controller can be reset by pushing the reset button on the main board.
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6 Peripherals
The development kit has a rich set of user programmable peripherals that allows most of the EFM32G
on-chip peripherals to be evaluated and tested.
The registers referred to in this chapter are accessible using the kit Board Support Package. Refer to
the BSP chapter in this manual to learn how to enable the motherboard peripherals. A reference to all
the registers and their function is in the Board Controller chapter.
6.1 Pushbuttons
The state of the pushbuttons marked SW1 to SW4 can be read from the board controller, using the
PUSHBUTTON register. The buttons are debounced by RC filters with a time constant of 1ms.
6.2 DIP switches
The dipswitch positions can be read from the board controller, using the DIPSWITCH register. The
switches are not debounced.
6.3 Joystick
The joystick position can be read from the board controller, using the JOYSTICK register. The positions
are debounced by RC filters with a time constant of 1ms.
6.4 LEDs
The user LEDs can be set by the board controller by writing to the LED register. The state of the LEDs
can also be read back.
6.5 Differential analog input
This BNC input signal is converted to a differential signal by a differential operational amplifier using
ground as reference.The op amp output common mode voltage is 1.65V, and also implements a lowpass active filter with a 3dB cutoff frequency of 4MHz.
The common mode voltage can be changed by adjusting the R5 and R12 resistors. It can also be
controlled by the VCM pin on the EFM if a shunt resistor is soldered in place of R252 and R5 and R12
are removed.
The peripheral is connected directly to the EFM when the ANALOG_DIFF bit in the PERCTRL register
in the board controller has been set.
6.6 Single ended analog inputs
This peripheral connects the two BNCs to the ADC on the EFM, and can be used as a single ended
analog interface. It can also be used for digital I/O.
The peripheral is connected directly to the EFM when the ANALOG_SE bit in the PERCTRL register in
the board controller has been set.
6.7 Line in / Audio in
This is an audio input amplifier with filter, and the output connects to the ADC of the EFM. The gain
of the amplifier is 0 dB and the bias point is 1.65 V. The filter is a 3-pole linear phase MFB filter with
a cutoff frequency of 20 kHz. In addition to the input amplifier and filter, the line in is equipped with a
voltage divider resulting in 6dB attenuation.
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The peripheral is connected directly to the EFM when the AUDIO_IN bit in the PERCTRL register in the
board controller has been set.
6.8 Line Out / Audio out
This is an audio output amplifier with filter, and the input connects to the DAC of the EFM. The gain of
the amplifier is 6 dB and is referenced to ground. The filter is a 3-pole linear phase MFB filter with a
cutoff frequency (at -3 dB) is at 27 kHz.
The peripheral is connected directly to the EFM when the AUDIO_OUT bit in the PERCTRL register in
the board controller has been set.
6.9 RS232
There are two RS232 connectors on the board which connects to the USART and LEUART of the EFM.
The RS232 driver runs at 3.3 V and it is recommended that the MCU voltage is 3.3 V as well. Unpredicted
behavior can occur if the MCU voltage is much lower than 3.3V and the RS232 driver is enabled.
The two RS232 drivers can be connected to the EFM individually by setting the RS232_A and RS232_B
bits in the PERCTRL register in the board controller. The RS232_SHUTDOWN bit must also be cleared.
Note
When none of the RS232 drivers are in use, it is highly recommended that the driver is shut
down by setting the RS232_SHUTDOWN bit in the PERCTRL register.
6.10 Accelerometer
This is a 3-axis accelerometer that connects to the ADC of the EFM. It outputs voltages proportional
to the g-forces for each axis. There are two settings for the range. If ACCEL_GSEL in the PERCTRL
register is cleared, the range is from 0 to 1.5 g, and when the bit is set the range is from 0 to 6 g.
The peripheral is connected directly to the EFM when the ACCEL bit in the PERCTRL register in the
board controller has been set.
6.11 IrDA
This is a 115.2 kBit/s (SIR) IrDA transceiver with a range of up to 70 cm, and connects to the USART
of the EFM.
The peripheral is connected directly to the EFM when the IRDA bit in the PERCTRL register in the board
controller has been set.
6.12 Potmeter
This is a potmeter pulled to 3.3 V by a 10k resistor, and it is connected to the ADC of the EFM. Using
the potmeter the output of this peripheral can be adjusted from 0 V to 3 V.
The peripheral is connected directly to the EFM when the POTMETER bit in the PERCTRL register in
the board controller has been set.
6.13 Ambient light sensor
This is an LDR in series with a 10k resistor, and it is connected to the ADC of the EFM. The output
voltage of the sensor ranges from 0.1 V to 2 V, increasing with the amount of light.
The peripheral is connected directly to the EFM when the AMBIENT bit in the PERCTRL register in the
board controller has been set.
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6.14 I C EEPROM
2
2
The 2 KB I C EEPROM is connected to the I C module of the EFM. The maximum bus speed is 400
kHz and the address is 0xA0.
The peripheral is connected directly to the EFM when the I2C bit in the PERCTRL register in the board
controller has been set.
2
6.15 I C Temperature sensor
2
2
The I C temperature sensor is connected to the I C module of the EFM. Temperature range of the sensor
is -55 °C to +125 °C. The maximum bus speed is 400 kHz and the address is 0x90.
The peripheral is connected directly to the EFM when the I2C bit in the PERCTRL register in the board
controller has been set.
6.16 SPI Flash
A 16 MBit SPI flash is connected to the SPI module of the EFM.
The peripheral is connected directly to the EFM when the SPI bit in the PERCTRL register in the board
controller has been set. To route the chip select correctly, the FLASH bit in the BC_SPI_CFG register
in the board controller must also be set.
6.17 microSD
A microSD slot is connected to the SPI module of the EFM.
The peripheral is connected directly to the EFM when the SPI bit in the PERCTRL register in the board
controller has been set. To route the chip select correctly, the MICROSD bit in the BC_SPI_CFG register
in the board controller must also be set.
6.18 TFT LCD
The TFT LCD can be accessed from the EFM through the board controller. The interface can be
configured to be either 9 bit or 16 bit. This selection is done by setting the 16BIT bit in the DISPLAY_CTRL
register in the board controller. It is also possible to use the SPI interface, but then the R112 resistor
must be moved over to the position of R112.
Note
16 bit or SPI interface options are currently not supported by the board controller.
6.19 SRAM
The 512 KB SRAM can be accessed from the EFM through the board controller. The data width is either
8 or 16 bit, depending on the access method.
6.20 NOR Flash
The 4 MB NOR Flash can be accessed from the EFM through the board controller. The data width is
either 8 or 16 bit, depending on the access method.
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7 Board Support Package
The Board Support Package (BSP) is a set of C source and header files that enables easy access to,
and control over board specific features and peripherals.
The package defines an API for direct access to the board controller registers, as well as regular function
calls for the most frequently used features.
7.1 Installation location
When installing the complete software package for the kit, the BSP will be installed under the main
installation directory, typically in a location such as
C:\Program Files\Energy Micro\boards\EFM32_Gxxx_DK\bsp\
or something similar. All files in the board support package is prefixed by dvk.
7.2 Resource usage
The BSP can be configured to use 1 of 2 access methods
• SPI - USART2 Serial Peripheral Interface
• EBI - External Bus Interface
SPI and EBI have different requirements regarding pin usage, see table below:
Table 7.1. GPIO Usage
GPIO Port
SPI Pins
EBI Pins
A
0-6, 15
B
C
2-5,13
12
D
E
8-15
F
2-5
The advantage of EBI over SPI, is that EBI access is a fast, directly memory mapped register access,
while SPI will add a synchronous two way transfer over a slower SPI interface. The disadvantage of EBI
is that it will consume a lot more I/O pins than SPI. The DVK will by default be configured to use SPI,
to enable EBI a small SPI initialization routine needs to be called once (per restart of the entire kit, not
per restart of the EFM32).
For DK part number EFM32_G8xx_DK with LCD controller, SPI is the only option as EBI and LCD cannot
be combined.
You must take care in not using these pins for other purposes after initialization of the BSP, as conflicts
and unpredictable behavior will result. You can disable the DVK interfaces after you have set your
configuration.
7.3 Application Programming Interface
To use the BSP, include the Development Kit header file, like this:
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#include "dvk.h"
Depending on the part number defined in your project as a build option, the DVK will default to the most
common access method for your MCU module according to part number. If you need to override the
default board control access method, you can define the access method by overriding the default with
DVK_SPI_CONTROL or DVK_EBI_CONTROL defines, such as
#define DVK_SPI_CONTROL
#include "dvk.h"
All functions in the BSP are prefixed with DVK_. The main initialization routine is defined as
void DVK_init(void);
and must be called before any access to the DVK-functions. To disable the BSP, call
void DVK_disable(void);
You can access all registers with the generic functions
void DVK_writeRegister(volatile uint16_t *addr, uint16_t data);
uint16_t DVK_readRegister(volatile uint16_t *addr);
Usable addresses for these functions, including bit fields are defined in the header file
dvk_bcregisters.h
The functions
void DVK_enablePeripheral( DVKPeripheral peri );
void DVK_disablePeripheral( DVKPeripheral peri );
can be used to toggle access/peripheral switches to all peripherals on the DVK. See the "peripheral"
example application for usage.
In addition to these main functions, full documentation of the complete API is included in the Doxygen/
HTML documentation of the installed package.
7.4 Example Applications
There are a number of example applications to illustrate the usage of the DVK API. You will find these
with their corresponding IAR Embedded Workbench and Keil MDK-ARM project files under
C:\Program Files\Energy Micro\boards\EFM32_Gxxx_DK\examples\
The examples include, among others
• blink - Simple application using the DVK and it's LED control API
• peripherals - Toggles peripherals on and off, indicated by LEDs on the board
• joystick - Use DVK LED, joystick and interrupt APIs for indicating DVK joystick movement
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The example files above have been configured to be built for both the EFM32_G2xx_DK and
EFM32_G8xx_DK kits, with the EFM32G290F128 and EFM32G890F128 part numbers. Select the
project that matches your setup to ensure correct operation.
7.5 How to include in your own applications
The easiest way to include the BSP in your application is to base your work on one of the example
applications, for instance the easy "blink" demonstration. The following items are recommended for
correct configuration:
1. Make sure you define the correct part number (e.g. EFM32G290F128) as a preprocessor defined
symbol
2. Make sure you define the correct part number (e.g. EFM32G290F128) for your IAR EWARM / Keil
MDK-ARM project
3. Add and include the EFM32_CMSIS-files (startup_efm32.s, system_efm32.c, core_cm3.c) to your
project
4. Add and include _all_ BSP package .c-files, with the dvk-prefix to your project
5. Configure include paths to point at the CMSIS/CM3/CoreSupport and CMSIS/CM3/DeviceSupport/
EnergyMicro/EFM32 directories
6. Configure include paths to point to the dvk/bsp directory
Make sure you call "DVK_init()" early at startup, and you should be all set.
7.6 Chip errata
Early versions of the development kit are shipped with EFM32 Engineering Samples on the MCU
modules. There has been updates to configuration and reset values that needs to be configured correctly
on these early parts. We recommend always starting your application with a call to
#include "chip.h"
void CHIP_init(void);
to ensure correct and stable behavior. See the BSP examples for details. We recommend also to
download and read the latest errata from the Energy Micro website for your part number.
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8 Configuration
Some parameters can be configured using the GUI. The other parameters, such as peripheral control,
can be controlled by software. See the Board Controller chapter for details.
8.1 MCU voltage
The MCU voltage can be set by entering the CFG page from the main page. Use the joystick to navigate
to VMCU and set your desired voltage by moving the joystick sideways. The measured VMCU can be
read at the bottom of this screen. Push Save to store your settings.
8.2 Debug settings
The debug routing can be set by entering the CFG page from the main page. Use the joystick to navigate
to Debug Control and set your desired mode by moving the joystick sideways. Push Save to store your
settings.
See the debug chapter to read more about the different modes.
8.3 Peripheral configuration
The peripheral configuration can be set by entering the CFG page from the main page and then entering
the Peri page. All peripherals connected to the EFM can be en- or disabled individually using the list
displayed in the GUI.
8.4 Program MCU
To program the MCU with files uploaded to the flash, enter the Flash page from the main page. The
list of available binaries are shown, and one of them can be selected by using the joystick. When the
desired binary has been selected, push Flash to program the MCU. While programming, a new page
shows with a progress bar. A status message appears when the programming is finished.
Note
The debug mode has to be set to MCU for this to work.
8.5 Upload files
To upload files, Gecko Commander must be used. This is an executable that can be found in the install
location, typically:
C:\Program Files\Energy Micro\EFM32 Kit Package\GeckoCmd\Gecko.exe
After launching the program, execute this command in Gecko Commander:
put your_binary_file.bin \flash\your_binary_file.bin
To see the commands available, execute this command for help:
h
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9 Advanced Energy Monitor
9.1 AEM Display
To enter AEM from the main page, press the pushbutton under the display labeled AEM. If the EFM
is using the display, press the AEM button at the right side of the display, and the board controller will
take control of the display and show the AEM. To return to EFM control, simply press the AEM button
once more.
When the AEM is entered, you will get a real-time graphical display of the current consumption of the
EFM and other circuits powered by the VMCU power rail. The AEM display mainly features a plot of
current the consumption over time. It also displays the latest sampled current consumption and voltage.
9.2 AEM configuration
There are several parameters that can be configured on the AEM. To configure AEM, first enter the
AEM page. Then push the button labeled CFG. In the CFG page, you can adjust the scale of the time
axis of the current plot.
9.3 AEM theory of operation
In order to be able to measure currents ranging from 0.1uA to 50mA (114dB dynamic range), two current
sense amplifiers are utilized. The amplifiers measure voltage drop over a small series resistor and
translates this into a current. Each amplifier is adjusted for current measurement in a specific range.
The ranges for the amplifiers overlap and a change between the two occurs when the current is 200uA.
To reduce noise, averaging of the samples is performed before the current measurement is presented
in the AEM GUI.
During startup of the kit and when VMCU is changed, a calibration of the AEM is performed. This
calibration compensates for the offset error in the sense amplifiers. In order for the calibration to be
correct, no load should be connected between the pins of ST6 during calibration.
9.4 AEM accuracy and performance
The Advanced Energy Monitor is capable of measuring currents in the range of 0.1uA to 50mA. For
currents above 200uA, the AEM is accurate within 0.1mA. When measuring currents below 200uA, the
accuracy increases to 1uA. Even though the absolute accuracy is 1uA in the sub 200uA range, the AEM
is able to detect changes in the current consumption as small as 100nA. The measurement bandwidth
of the AEM is 60Hz when measuring currents below 200uA and 120Hz when measuring currents above
200uA. The table below summarizes accuracy of the two current sense amplifiers in different ranges.
Table 9.1. AEM accuracy
Current range
Low gain amplifier accuracy
High gain amplifier accuracy
50mA
0.1mA
-
1mA
0.1mA
-
200uA
0.01mA
1uA
10uA
-
0.1uA
1uA
-
0.1uA
Note
In order for the AEM to work correctly, VMCU should be 3.0V or higher.
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10 Board controller
The board controller (BC) consists of the control MCU and an FPGA. The FPGA is essentially a
programmable multiplexer that allows the resources on the board to be shared between the EFM and
the control MCU. It also enables jumperless peripheral configuration. The control MCU implements the
built-in debugger, the AEM and performs housekeeping tasks.
To use the board controller for your application, the Board Support Package (BSP) must be installed.
See the BSP chapter to find out how.
10.1 Register Map
The offset register address is relative to the registers base address.
Offset
Name
Type
Description
0x000
BC_BC_CFG
RW
Board Controller Config register
0x002
BC_EM
RW
Energy Mode register
0x004
BC_MAGIC
R
Magic number
0x006
BC_LED
RW
User LEDs register
0x008
BC_PUSHBUTTON
R
User pushbutton status register
0x00A
BC_DIPSWITCH
R
User dipswitch status register
0x00C
BC_JOYSTICK
R
Joystick state register
0x00E
BC_AEM
R
AEM button status register
0x010
BC_DISPLAY_CTRL
RW
Display control register
0x012
BC_EBI_CFG
RW
EBI configuration register
0x014
BC_BUS_CFG
RW
BUS configuration register
0x018
BC_PERCTRL
RW
Peripheral control register
0x01A
BC_AEMSTATE
R
AEM button status register
0x01C
BC_SPI_CFG
RW
SPI configuration register
0x01E
BC_RESET
RW
Reset register
0x020
BC_ADC_START
RW
ADC start byte register
0x022
BC_ADC_STATUS
R
ADC status register
0x024
BC_ADC_DATA
R
ADC data register
0x028
BC_HW_VERSION
R
Hardware version register
0x02A
BC_FW_BUILDNO
R
Firmware build number
0x02C
BC_FW_VERSION
R
Firmware version register
0x02E
BC_SCRATCH_COMMON
RW
Common scratch register
0x030
BC_SCRATCH_EFM0
RW
EFM scratch register 0
0x032
BC_SCRATCH_EFM1
RW
EFM scratch register 1
0x034
BC_SCRATCH_EFM2
RW
EFM scratch register 2
0x036
BC_SCRATCH_EFM3
RW
EFM scratch register 3
0x038
BC_SCRATCH_BC0
RW
BC scratch register 0
0x03A
BC_SCRATCH_BC1
RW
BC scratch register 1
0x03C
BC_SCRATCH_BC2
RW
BC scratch register 2
0x03E
BC_SCRATCH_BC3
RW
BC scratch register 3
0x040
BC_INTFLAG
RW
Interrupt flags
0x042
BC_INTEN
RW
Interrupt enables
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10.2 Register Description
10.2.1 BC_BC_CFG - Board Controller Config register
RW
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0x000
14
Bit Position
15
Offset
BC_CFG
Access
Name
Bit
Name
Reset
Access
Description
15:1
Reserved
To ensure compatibility with future devices, always write bits to 0.
0
BC_CFG
0
RW
Board controller configuration
Use this bit to change between SPI and EBI interface on the board controller
Value
Mode
Description
0
SPI
The BC is configured to use the SPI interface.
1
EBI
The BC is configured to use the EBI interface.
10.2.2 BC_EM - Energy Mode register
1
1
0
2
2
RW 0x0
3
3
4
5
6
7
9
10
11
12
13
14
15
0x002
8
Bit Position
Offset
Reset
EM
Access
Name
Bit
Name
Reset
Access
Description
15:3
Reserved
To ensure compatibility with future devices, always write bits to 0.
2:0
EM
0x0
RW
Energy Mode register
This register is used to store the Energy Mode the EFM is running in.
10.2.3 BC_MAGIC - Magic number
Reset
0
4
5
6
MAGIC
R
Access
Name
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0xEF32
9
10
11
12
13
14
15
0x004
8
Bit Position
Offset
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Bit
Name
Reset
Access
Description
15:0
MAGIC
0xEF32
R
Magic number
This register can be used to test the interface.
10.2.4 BC_LED - User LEDs register
Offset
0
1
2
3
4
5
6
7
0x0000
8
9
10
11
12
13
0x006
14
15
Bit Position
RW
Reset
LED
Access
Name
Bit
Name
Reset
Access
Description
15:0
LED
0x0000
RW
User LED register
Write to this register to change the DVK user leds
10.2.5 BC_PUSHBUTTON - User pushbutton status register
1
0
1
0
2
2
0x0
3
3
4
5
6
7
8
9
10
11
12
13
0x008
14
Bit Position
15
Offset
Reset
PUSHBUTTON
R
Access
Name
Bit
Name
Reset
Access
Description
15:4
Reserved
To ensure compatibility with future devices, always write bits to 0.
3:0
PUSHBUTTON
0x0
R
User pushbutton status register
Read this register to determine the state of the pushbuttons
10.2.6 BC_DIPSWITCH - User dipswitch status register
Offset
4
5
6
7
0x00
Reset
DIPSWITCH
R
Access
Name
2010-04-09 - t0005_1.10
8
9
10
11
12
13
14
15
0x00A
Bit Position
17
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Bit
Name
Reset
Access
Description
15:8
Reserved
To ensure compatibility with future devices, always write bits to 0.
7:0
DIPSWITCH
0x00
R
User dipswitch status register
Read this register to determine the state of the dipswitch
10.2.7 BC_JOYSTICK - Joystick state register
15:5
Reserved
To ensure compatibility with future devices, always write bits to 0.
4
CENTER
0
0
0
R
DOWN
1
0
R
2
0
R
3
0
RIGHT
Access
1
Reset
UP
Name
2
Bit
LEFT
Name
3
CENTER
R
Access
R
0
Reset
4
5
6
7
8
9
10
11
12
13
0x00C
14
Bit Position
15
Offset
Description
R
Joystick CENTER switch state register
Read this register to get the status of the center switch of the joystick.
3
LEFT
0
R
Joystick LEFT switch state register
Read this register to get the status of the left switch of the joystick.
2
UP
0
R
Joystick UP switch state register
Read this register to get the status of the up switch of the joystick.
1
RIGHT
0
R
Joystick RIGHT switch state register
Read this register to get the status of the right switch of the joystick.
0
DOWN
0
R
Joystick DOWN switch state register
Read this register to get the status of the down switch of the joystick.
10.2.8 BC_AEM - AEM button status register
0
0
Reset
4
5
6
7
9
10
11
12
13
14
15
0x00E
8
Bit Position
Offset
AEM
R
Access
Name
Bit
Name
Reset
Access
Description
15:1
Reserved
To ensure compatibility with future devices, always write bits to 0.
0
AEM
0
R
AEM button status register
Read this register to determine the state of the AEM button
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10.2.9 BC_DISPLAY_CTRL - Display control register
Name
Bit
Name
Reset
Access
15:2
Reserved
To ensure compatibility with future devices, always write bits to 0.
1
POWER_ENABLE
0
0
0
RESET
POWER_ENABLE
Access
RW
RW
0
Reset
1
2
3
4
5
6
7
8
9
10
11
12
13
0x010
14
Bit Position
15
Offset
Description
RW
Display power enable
RW
Display reset
Set this bit to enable power to the TFT display
0
RESET
0
Set this bit to put the TFT display into reset mode
10.2.10 BC_EBI_CFG - EBI configuration register
0
RW 0x0
1
2
3
4
5
6
7
8
9
10
11
12
13
0x012
14
Bit Position
15
Offset
Reset
EBI_CFG
Access
Name
Bit
Name
Reset
Access
Description
15:2
Reserved
To ensure compatibility with future devices, always write bits to 0.
1:0
EBI_CFG
0x0
RW
EBI configuration register
Set this register to configure the BC EBI interface to match the configuration in your application
Value
Mode
Description
0
EBI_16_16
The BC EBI is in a 16 address bits and 16 data bits configuration
1
EBI_8_8
The BC EBI is in a 8 address bits and 8 data bits configuration
2
EBI_24_8
The BC EBI is in a 24 address bits and 8 data bits configuration
10.2.11 BC_BUS_CFG - BUS configuration register
0
1
2
3
4
5
6
7
RW 0x0
Reset
BUS_CFG
Access
Name
2010-04-09 - t0005_1.10
8
9
10
11
12
13
14
0x014
Bit Position
15
Offset
19
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Bit
Name
Reset
Access
Description
15:2
Reserved
To ensure compatibility with future devices, always write bits to 0.
1:0
BUS_CFG
0x0
RW
BUS configuration register
Set this register to configure which bus has access to the SRAM, Nor Flash and TFT display.
Value
Mode
Description
0
FSMC
The FSMC has access
1
EBI
The EBI interface has access
2
SPI
The SPI interface has access
10.2.12 BC_PERCTRL - Peripheral control register
Bit
Name
Reset
Access
Description
15
IRDA_SHUTDOWN
0
RW
Shut down IrDA transceiver
RW
Shut down RS232 driver
0
RW
ACCEL
0
1
RW
AMBIENT
0
2
RW
POTMETER
0
3
RW
RS232A
0
4
RW
RS232B
0
5
RW
SPI
0
6
RW
I2C
0
RW
IRDA
0
8
0
RW
ANALOG_SE
RW
ANALOG_DIFF
0
9
10
RW
AUDIO_OUT
0
11
RW
AUDIO_IN
0
12
RW
ACCEL_GSEL
0
13
RW
ACCEL_SELFTEST
0
14
RW
RS232_SHUTDOWN
Name
RW
Access
IRDA_SHUTDOWN
0
Reset
0
15
0x018
7
Bit Position
Offset
Set this bit to shut down the IrDA transceiver
14
RS232_SHUTDOWN
0
Set this bit to shut down the RS232 driver. It is strongly recommended that this is done when the application does not use RS232.
13
ACCEL_SELFTEST
0
RW
Accelerometer selftest mode
Set this bit to put the accelerometer into selftest mode
12
ACCEL_GSEL
0
RW
Accelerometer g-select
Use this bit to configure the g-range of the accelerometer
11
Value
Mode
Description
0
LOW
The g-range is up to 1.5g
1
HIGH
The g-range is up to 6g
AUDIO_IN
0
RW
Audio in connect
Set this bit to connect the audio in amplifier to the EFM
10
AUDIO_OUT
0
RW
Audio out connect
Set this bit to connect the audio out amplifier to the EFM
9
ANALOG_DIFF
0
RW
Analog differential input connect
Set this bit to connect the analog differential inputs to the EFM
8
ANALOG_SE
0
RW
Analog single ended input connect
Set this bit to connect the analog single ended inputs to the EFM
7
IRDA
0
RW
IrDA connect
Set this bit to connect the IrDA transceiver to the EFM
6
I2C
0
2
RW
I C bus connect
2
Set this bit to connect the I C devices to the EFM
5
SPI
2010-04-09 - t0005_1.10
0
RW
SPI bus connect
20
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Bit
Name
Reset
Access
Description
Set this bit to connect the SPI devices to the EFM
4
RS232B
0
RW
RS232B connect
RW
RS232A connect
RW
Potmeter connect
RW
Ambient light sensor connect
Set this bit to connect the RS232 B to the EFM
3
RS232A
0
Set this bit to connect the RS232 A to the EFM
2
POTMETER
0
Set this bit to connect the potmeter to the EFM
1
AMBIENT
0
Set this bit to connect the ambient light sensor to the EFM
0
ACCEL
0
RW
Accelerometer connect
Set this bit to connect the accelerometer chip to the EFM
10.2.13 BC_AEMSTATE - AEM button status register
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0x01A
14
Bit Position
15
Offset
AEM
R
Access
Name
Bit
Name
Reset
Access
Description
15:1
Reserved
To ensure compatibility with future devices, always write bits to 0.
0
AEM
0
R
AEM state register
When this bit is 0, the BC can take control of the TFT display, and when 1 the EFM can take control. This bit is toggled by the
AEM button push
10.2.14 BC_SPI_CFG - SPI configuration register
0
1
2
3
RW
0
Reset
4
5
6
7
8
9
10
11
12
13
0x01C
14
Bit Position
15
Offset
SPI_CFG
Access
Name
Bit
Name
Reset
Access
Description
15:1
Reserved
To ensure compatibility with future devices, always write bits to 0.
0
SPI_CFG
0
RW
SPI configuration register
This register selects which SPI module will receive the CS signal
Value
Mode
Description
0
FLASH
The SPI CS is routed to the SPI Flash
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Bit
Name
Reset
Access
Description
Value
Mode
Description
1
MICROSD
The SPI CS is routed to the microSD
10.2.15 BC_RESET - Reset register
EFM
Name
Bit
Name
Reset
Access
15:2
Reserved
To ensure compatibility with future devices, always write bits to 0.
1
EFM
0
0
0
RW
Access
FLASH
RW
0
Reset
1
2
3
4
5
6
7
8
9
10
11
12
13
0x01E
14
Bit Position
15
Offset
Description
RW
EFM reset signal
RW
Flash reset signal
Set this bit to put the EFM into a reset state
0
FLASH
0
Set this bit to put the Nor flash into a reset state
10.2.16 BC_ADC_START - ADC start byte register
0
1
2
3
0x00
4
5
6
7
9
10
11
12
13
14
15
0x020
8
Bit Position
Offset
RW
Reset
ADC_START
Access
Name
Bit
Name
Reset
Access
Description
15:8
Reserved
To ensure compatibility with future devices, always write bits to 0.
7:0
ADC_START
0x00
RW
ADC start byte
Write this byte to start a conversion on the voltage monitor ADC. The content of the byte is equal to the start byte for the ADC itself.
10.2.17 BC_ADC_STATUS - ADC status register
0
1
2
3
4
5
6
BUSY
R
Access
Name
2010-04-09 - t0005_1.10
7
0
Reset
8
9
10
11
12
13
14
0x022
Bit Position
15
Offset
22
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Bit
Name
Reset
Access
Description
15:1
Reserved
To ensure compatibility with future devices, always write bits to 0.
0
BUSY
0
R
ADC status byte
Read this bit to determine the state of the ADC conversion
Value
Mode
Description
0
DONE
The ADC is not doing a conversion
1
BUSY
The ADC is busy doing a conversion
10.2.18 BC_ADC_DATA - ADC data register
1
0
0
2
2
1
3
3
4
5
6
7
0x0000
9
10
11
12
13
14
15
0x024
8
Bit Position
Offset
Reset
ADC_START
R
Access
Name
Bit
Name
Reset
Access
Description
15:0
ADC_START
0x0000
R
ADC data register
This register contains the result of the latest conversion
10.2.19 BC_HW_VERSION - Hardware version register
0x0
PCB
BOARD
R
Access
R
Reset
Name
Access
4
5
6
7
9
0x0
10
11
12
13
14
15
0x028
8
Bit Position
Offset
Bit
Name
Reset
Description
15:11
Reserved
To ensure compatibility with future devices, always write bits to 0.
10:8
PCB
0x0
R
PCB revision
Read these bits to determine the PCB revision
7:4
Reserved
To ensure compatibility with future devices, always write bits to 0.
3:0
BOARD
0x0
R
Board revision
Read these bits to determine the board revision
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10.2.20 BC_FW_BUILDNO - Firmware build number
0
1
2
3
4
5
6
7
0x0000
8
9
10
11
12
13
0x02A
14
Bit Position
15
Offset
Reset
BUILDNO
R
Access
Name
Bit
Name
Reset
Access
Description
15:0
BUILDNO
0x0000
R
Board revision
Read this register to determine the firmware build number
10.2.21 BC_FW_VERSION - Firmware version register
2
1
0
2
1
0
3
0x00
4
5
6
7
8
10
9
R
PATCHLEVEL
Name
MINOR
MAJOR
R
Access
R
Reset
0x0
11
12
13
0x0
0x02C
14
Bit Position
15
Offset
Bit
Name
Reset
Access
Description
15:12
MAJOR
0x0
R
Firmware major revision
R
Firmware minor revision
R
Firmware patch level
Read these bits to determine the major revision
11:8
MINOR
0x0
Read these bits to determine the minor revision
7:0
PATCHLEVEL
0x00
Read these bits to determine the patch level
10.2.22 BC_SCRATCH_COMMON - Common scratch register
Offset
3
4
5
6
7
0x0000
RW
Reset
SCRATCH_COMMON
Access
Name
2010-04-09 - t0005_1.10
8
9
10
11
12
13
14
15
0x02E
Bit Position
24
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Bit
Name
Reset
Access
Description
15:0
SCRATCH_COMMON
0x0000
RW
Common scratch register
This register can be used as a scratch register for both the EFM and the board controller.
10.2.23 BC_SCRATCH_EFM0 - EFM scratch register 0
3
2
1
0
3
2
1
0
4
5
6
7
0x0000
8
9
10
11
12
13
0x030
14
Bit Position
15
Offset
RW
Reset
SCRATCH_EFM0
Access
Name
Bit
Name
Reset
Access
Description
15:0
SCRATCH_EFM0
0x0000
RW
EFM scratch register 0
This register can be used as a scratch register for the EFM. The board controller has read only access.
10.2.24 BC_SCRATCH_EFM1 - EFM scratch register 1
Offset
4
5
6
7
0x0000
8
9
10
11
12
13
0x032
14
15
Bit Position
RW
Reset
SCRATCH_EFM1
Access
Name
Bit
Name
Reset
Access
Description
15:0
SCRATCH_EFM1
0x0000
RW
EFM scratch register 1
This register can be used as a scratch register for the EFM. The board controller has read only access.
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10.2.25 BC_SCRATCH_EFM2 - EFM scratch register 2
0
1
2
3
4
5
6
7
0x0000
8
9
10
11
12
13
0x034
14
Bit Position
15
Offset
RW
Reset
SCRATCH_EFM2
Access
Name
Bit
Name
Reset
Access
Description
15:0
SCRATCH_EFM2
0x0000
RW
EFM scratch register 2
This register can be used as a scratch register for the EFM. The board controller has read only access.
10.2.26 BC_SCRATCH_EFM3 - EFM scratch register 3
3
2
1
0
3
2
1
0
4
5
6
7
0x0000
8
9
10
11
12
13
0x036
14
Bit Position
15
Offset
RW
Reset
SCRATCH_EFM3
Access
Name
Bit
Name
Reset
Access
Description
15:0
SCRATCH_EFM3
0x0000
RW
EFM scratch register 3
This register can be used as a scratch register for the EFM. The board controller has read only access.
10.2.27 BC_SCRATCH_BC0 - BC scratch register 0
4
5
6
7
0x0000
RW
Reset
SCRATCH_BC0
Access
Name
2010-04-09 - t0005_1.10
8
9
10
11
12
13
14
0x038
Bit Position
15
Offset
26
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Bit
Name
Reset
Access
Description
15:0
SCRATCH_BC0
0x0000
RW
BC scratch register 0
This register can be used as a scratch register for the BC. The EFM has read only access.
10.2.28 BC_SCRATCH_BC1 - BC scratch register 1
3
2
1
0
3
2
1
0
4
5
6
7
0x0000
8
9
10
11
12
13
0x03A
14
Bit Position
15
Offset
RW
Reset
SCRATCH_BC1
Access
Name
Bit
Name
Reset
Access
Description
15:0
SCRATCH_BC1
0x0000
RW
BC scratch register 1
This register can be used as a scratch register for the BC. The EFM has read only access.
10.2.29 BC_SCRATCH_BC2 - BC scratch register 2
4
5
6
7
0x0000
9
10
11
12
13
14
15
0x03C
8
Bit Position
Offset
RW
Reset
SCRATCH_BC2
Access
Name
Bit
Name
Reset
Access
Description
15:0
SCRATCH_BC2
0x0000
RW
BC scratch register 2
This register can be used as a scratch register for the BC. The EFM has read only access.
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10.2.30 BC_SCRATCH_BC3 - BC scratch register 3
Offset
0
1
2
3
4
5
6
7
0x0000
8
9
10
11
12
13
0x03E
14
15
Bit Position
RW
Reset
SCRATCH_BC3
Access
Name
Bit
Name
Reset
Access
Description
15:0
SCRATCH_BC3
0x0000
RW
BC scratch register 3
This register can be used as a scratch register for the BC. The EFM has read only access.
10.2.31 BC_INTFLAG - Interrupt flags
Bit
Name
Reset
Access
15:4
Reserved
To ensure compatibility with future devices, always write bits to 0.
3
AEM
0
0
RW
PB
0
1
RW
0
2
0
DIP
Name
RW
AEM
Access
JOYSTICK
3
RW
0
Reset
4
5
6
7
8
9
10
11
12
13
0x040
14
Bit Position
15
Offset
Description
RW
AEM interrupt flag
This bit is set when the AEM button is pushed or released. It will assert an interrupt to the EFM if the interrupt has been enabled.
This bit is cleared by writing a 1 to it.
2
JOYSTICK
0
RW
Joystick interrupt flag
This bit is set when the joystick changes position, or is pushed or released. It will assert an interrupt to the EFM if the interrupt has
been enabled. This bit is cleared by writing a 1 to it.
1
DIP
0
RW
Dipswitch interrupt flag
This bit is set when any of the dipswitch positions are changed. It will assert an interrupt to the EFM if the interrupt has been enabled.
This bit is cleared by writing a 1 to it.
0
PB
0
RW
Pushbuttons interrupt flag
This bit is set when any of the 4 pushbutton are pushed or released. It will assert an interrupt to the EFM if the interrupt has been
enabled. This bit is cleared by writing a 1 to it.
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10.2.32 BC_INTEN - Interrupt enables
Offset
Bit
Name
Reset
Access
15:4
Reserved
To ensure compatibility with future devices, always write bits to 0.
3
AEM
0
0
RW
PB
0
1
RW
0
2
0
DIP
Name
RW
AEM
Access
JOYSTICK
3
RW
0
Reset
4
5
6
7
8
9
10
11
12
13
0x042
14
15
Bit Position
Description
RW
AEM interrupt enable
If this bit is set, an interrupt is asserted when the corresponding interrupt flag is set.
2
JOYSTICK
0
RW
Joystick interrupt enable
If this bit is set, an interrupt is asserted when the corresponding interrupt flag is set.
1
DIP
0
RW
Dipswitch interrupt enable
If this bit is set, an interrupt is asserted when the corresponding interrupt flag is set.
0
PB
0
RW
Pushbuttons interrupt enable
If this bit is set, an interrupt is asserted when the corresponding interrupt flag is set.
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11 Connectivity
11.1 Resource connections
In general, all ports are routed from the BRD3300A to the prototyping board. That means that Port A on
the EFM is replicated on Port A on the prototyping board. In addition to that, a lot of EFM pins has been
connected to other resources on the board, some using switches and some permanent.
The following table describes the connections between the EFM on the BRD3300A and the kit resources.
Table 11.1. Connections
MCU
MCU function
EFM32_BConnection
EXP32_BProto
port
Function
A0
LCD_SEG13
A1
LCD_SEG14
A2
LCD_SEG15
A3
LCD_SEG16
A4
LCD_SEG17
A5
LCD_SEG18
A6
LCD_SEG19
A9
LCD_SEG37
A15
LCD_SEG12
B0
LCD_SEG32
B1
LCD_SEG33
B2
LCD_SEG34
B3
LCD_SEG20
B4
LCD_SEG21
B5
LCD_SEG22
B6
LCD_SEG23
B7
US1_CLK #0
B53
RS232_A
B53
J4
RS232_A_#CTS
B8
US1_CS #0
B54
RS232_A
B54
J5
RS232_A_#RTS
B11
DAC0_OUT0
B48
AUDIO_OUT
B48
I7
AUDIO_OUT_RIGHT
B12
DAC0_OUT1
B49
AUDIO_OUT
B49
I8
AUDIO_OUT_LEFT
C0
US1_TX #0
B55
RS232_A
B55
J6
RS232_A_TX
C1
US1_RX #0
B52
RS232_A
B52
J3
RS232_A_RX
C2
US2_TX #0
B42
BC_BUS_CONNECT_SPI
B42
H13
BC_BUS26
C3
US2_RX #0
B43
BC_BUS_CONNECT_SPI
B43
H14
BC_BUS27
C4
US2_CLK #0
B40
BC_BUS_CONNECT_SPI
B40
H11
BC_BUS24
C5
US2_CS #0
B41
BC_BUS_CONNECT_SPI
B41
H12
BC_BUS25
C6
LEU1_TX #0
B62
RS232_B
B62
J9
RS232_B_TX
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MCU
MCU function
EFM32_BConnection
EXP32_BProto
port
Function
C7
LEU1_RX #0
B63
RS232_B
B63
J10
RS232_B_RX
C8
US0_CS #2
B65
SPI
B65
J12
SPI_BUS_#CS
C9
US0_CLK #2
B64
SPI
B64
J11
SPI_BUS_SCLK
C10
US0_RX #2
B67
SPI
B67
J14
SPI_BUS_MISO
C11
US0_TX #2
B66
SPI
B66
J13
SPI_BUS_MOSI
B72
Connected
B72
H15
BC_BUS_CONNECT_EBI
C12
C13
Connected
C15
FPGA_#INT
B79
Connected
B79
J18
MCUDBG_TDO_SWO
D0
ADC_CH0
B50
AUDIO_IN
B50
I9
AUDIO_IN_RIGHT
D1
ADC_CH1
B51
AUDIO_IN
B51
I10
AUDIO_IN_LEFT
D2
ADC_CH2
B56
ACCEL
B56
I11
ACCEL_XOUT
D3
ADC_CH3
B57
ACCEL
B57
I12
ACCEL_YOUT
D4
ADC_CH4
B58
ACCEL
B58
I13
ACCEL_ZOUT
D5
ADC_CH5
B70
POTMETER
B70
I15
SENSOR_POTMETER
D5
ADC_CH5
B71
AMBIENT
B71
I16
SENSOR_LIGHT
D6
ADC_CH6
B46
ANALOG_DIFF
B46
I5
ANALOG_DIFF_N
D7
ADC_CH7
B47
ANALOG_DIFF
B47
I6
ANALOG_DIFF_P
D9
LCD_SEG28
D10
LCD_SEG29
D11
LCD_SEG30
D12
LCD_SEG31
D14
I2C0_SDA #3
B68
I2C
B68
J15
I2C_BUS_SDA
D15
I2C0_SCL #3
B69
I2C
B69
J16
I2C_BUS_SCL
E4
LCD_COM0
E5
LCD_COM1
E6
LCD_COM2
E7
LCD_COM3
E8
LCD_SEG4
E9
LCD_SEG5
E10
LCD_SEG6
E11
LCD_SEG7
E12
LCD_SEG8
E13
LCD_SEG9
E14
LCD_SEG10
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MCU
MCU function
EFM32_BConnection
EXP32_BProto
port
Function
E15
LCD_SEG11
F0
DGB_SWCLK
B77
Connected
B77
I18
MCUDBG_TCK_SWCLK
F1
DGB_SWDIO
B78
Connected
B78
J17
MCUDBG_TCK_SWDIO
F2
LCD_SEG0
F3
LCD_SEG1
F4
LCD_SEG2
F5
LCD_SEG3
F6
LCD_SEG24
F7
LCD_SEG25
F8
LCD_SEG26
F9
LCD_SEG72
Table 11.2. Nomenclature
Name
Description
MCU
The pin name of the MCU
MCU function
The I/O function on that pin that is used for this resource
EFM32_B
The corresponding pin number on the EFM32_B connector. If this is empty, the signal is not routed out
from the BRD3300A
Connection
Which API function is used to make the connection.
EXP32_B
The corresponding pin number on the EXP32_B connector. If this is empty, the signal is not routed out
from the BRD3300A
Proto port
The corresponding pin on the proto board
Function
The name of the kit resource
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12 Connectors
12.1 EFM32 and EXP32 connectors
The EFM32 connector is used to connect the MCU plugin board to the main board, and the EXP32
connector is used to connect the prototype card to the main board. The EFM32_A connector and the first
16 pins of the EFM32_B connector is directly connected to the corresponding pins on the EXP32_A and
EXP32_B connectors. These signals duplicate the MCU ports to the port headers on the prototype board.
Some care must be taken when fitting and removing the plugin cards. Make sure that the plugin boards
sits properly in place to ensure good connections. The connectors are rated for 100 plugin cycles.
For pinout check the schematics.
12.2 Debug connector
This connector is used for Debug In and Debug Out (see Debug chapter). The pinout is described in
the table.
Table 12.1. Debug connector pinout
Pin
number
Function
Note
1
VTARGET
Target voltage on the debugged application.
2
NC
3
/TRST
4
GND
5
TDI
6
GND
7
TMS/SWDIO
8
GND
9
TCK
10
GND
11
RTCK
12
GND
13
TDO/SWO
14
GND
15
/RESET
16
GND
17
PD
This pin has a 100k pulldown.
18
Cable detect
This signal must be pulled to ground by the external debugger or application for cable
insertion detection.
19
PD
This pin has a 100k pulldown.
20
GND
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JTAG tap reset
JTAG data in
JTAG TMS or Serial Wire data I/O
JTAG TCK or Serial Wire clock
JTAG RTCK
JTAG TDO or Serial Wire Output
Target MCU reset
33
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13 Debugging
The EFM32-G8XX-DK has an on-board debugger, and it can be used in different ways to debug the
EFM, both on and off kit. Below are descriptions on the different modes. Check the configuration chapter
to find out how to change the debug setting.
Table 13.1. Debug modes
Mode
Description
Debug MCU
In this mode the built-in debugger is connected to EFM on the BRD3300A.
Debug IN
In this mode the built-in debugger is disconnected, and an external debugger can be connected to
debug the EFM on the BRD3300A.
Debug OUT
In this mode the built-in debugger can be used to debug an EFM mounted in your own application.
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14 IDEs
The following IDEs are supported.
14.1 IAR
An evaluation version of IAR is included in the EFM32-G8XX-DK package. Check the quick start guide
and IAR's own documentation on how to use it.
14.2 KEIL
An evaluation version of KEIL is included in the EFM32-G8XX-DK package. Check the quick start guide
and KEIL's own documentation on how to use it.
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15 Gecko Commander and Upgrades
Gecko Commander is a command line utility that comes with the Gecko DK Installer package. It can
perform various kit and EFM32 specific tasks. Press "h" for help at the prompt for a listing of available
commands. Press "h command" for help for a specific command, listing arguments and options.
15.1 Available commands
Table 15.1. Gecko Commander
Command
Description
ping
"Ping" kit, i.e. verify that target kit is up and running
speed
Sets the link speed for the serial wire debug interface from the kit, towards the EFM32
reset
Reset kit, which also implies a reset of the EFM32 as well
usb
Change J-Link USB port used, default is port 0. Unless you have multiple J-Link debuggers there
should be no reason to change this
version
Get PCB and firmware versions of kit
install
Install an application or boot package. This command, with a filename ending with .emz as an option
upgrades the kit software
ls
List directory, shows which binary files has been uploaded to the kit, which can be flashed with the GUI
put
Copy a binary file from host to target, that can be used to flash directly from the kit GUI (Flash
submenu)
rm
Remove file
flash
Flashes the EFM32 program memory with binary file, starting from flash address 0x0000000. Enter
filename as argument.
verify
Verifies correct installation of a binary into flash
dumpbin
Dumps content of memory of the EFM32 to file
erase
Erases the entire flash
unlock
Unlocks a locked chip and performs a device erase
lock
Locks the chip, prevents reading out the flash over debugger interface
protect
Write-protects pages in flash
uprotect
Clears all write protection lock bits
power
Dump power measurements from the running application to file. Enter filename as argument.
mode
Sets the mode of the on-board debugger. Available modes:
mcu - Debug the EFM32 using the on-board debugger
in - Debug the EFM32 using an external debugger
out - Use the STK as an external debugger
off - Disable the debugger
15.2 Upgrades
Upgrading the kit can be done by using the "Upgrade Kit" script in the start menu. New versions can
be downloaded from http://www.energymicro.com/downloads/. The script will use Gecko commander to
install the latest available Kit SW package. It is important to upgrade the kit when installing a new SW
package, as new Gecko commander functionality might require kit controller software upgrades.
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16 Version information
The current version information can be read from the EFM32-G8XX-DK by entering the About page from
the main page in the GUI, and then pushing Info.
Table 16.1. Current versions
Type
Version
Released
Firmware revision
1v3
2010-04-09
FPGA version
1v1
2009-11-13
Hardware version
2v0
2009-11-13
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17 MCU board
The EFM32-G8XX-DK is equipped with the BRD3300A. The main features are listed here, but for a
complete overview, check the BRD3300A user manual.
Features:
• The worlds most energy friendly microcontroller
• Compatible with the Advanced Energy Monitoring (AEM) system of the EFM32 Gecko Development
Kit
• Leds indicating power and reset
• 32 MHz crystal
• 32.768 kHz crystal
• Reset button and ground-hooks for easy debugging
• Energy Micro LCD
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18 Prototyping Board
The EFM32-G8XX-DK is equipped with a prototyping board. The main features are listed here, but for
a complete overview, check the prototyping board user manual.
18.1 Overview
Features:
• Ready-to-use prototyping area for hole-mount, TSSOP, SO, SOT23-6, SOT23 and 0805 SMD
components.
• VMCU power domain tracked by the Advanced Energy Monitor (AEM).
• 3.3V and 5V power domains available.
• All EFM32 IO lines directly accessible through pin headers.
• User LEDS ready for use.
• LEDS indicating power.
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19 Errata
19.1 DVK hardware errata
19.1.1 Port E0 on EFM32 MCU board disconnected
Kit Revisions
Rev A
Description
Revision A kits are shipped with engineering samples of the EFM32. On MCU boards containing these
engineering samples, port E0 on the EFM32 is disconnected. The MCU boards in question are shipped
with a sticker indicating that port E0 is disconnected.
19.2 DVK firmware errata
19.2.1 VMCU regulator
Firmware Revisions
1.0.1
Description
Firmware version 1.0.1 contains an I2C driver that on some occasions hangs. When this happens, VMCU
freezes and can no longer be changed. The same issue may also result in wrong VMCU setting after
startup. A power cycle of the DVK fixes the problem. This errata is fixed in firmware version 1.1.1 or
newer.
19.2.2 Storing user configuration
Firmware Revisions
1.0.1
Description
Firmware version 1.0.1 contains an I2C driver that on some occasions hangs. When this happens, user
configuration may no longer be stored. A power cycle of the DVK fixes the problem. This errata is fixed
in firmware version 1.1.1 or newer.
19.2.3 Debug mode setting
Firmware Revisions
1.0.1
Description
When changing debug mode using the GUI, the actual configuration of the debug interface is not always
the same as the debug mode set by the GUI. An upgrade to firmware version 1.1.1 or newer fixes this
errata.
19.2.4 Serial Wire Output
Firmware Revisions
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1.0.1
Description
Enabling Serial Wire Output (SWO) would cause onboard firmware to fail. An upgrade to firmware version
1.1.1 or newer fixes this errata.
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20 Schematic
On the next pages you can find the schematic and the assembly drawings of the main board.
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5
4
3
2
1
D
D
EFM32 Development Kit
Board Function
C
B
A
Revision History
Page
Analog Interfaces
2
Sensors, SPI bus and I2C bus
3
User Interface
4
Display Interface
5
Flash and SRAM
6
Board Control - Control MCU
7
Board Control - Buses
8
Board Control - Misc
9
Board Control - JTAG
10
Control MCU
11
Control MCU - BC Interface
12
Debug Interface
13
Board Control - Level shift
14
EXP32 Assignments #1
15
EXP32 Assignments #2
16
EFM32 Board Connectors
17
EXP32 Board Connectors
18
Main Power Regulators
19
EFM Power Regulators and AEM
20
Power monitoring
Rev.
Description
C
Initial Release
C
B
/
TOP
Schematic Title
A
EFM32 Development Kit - Mainboard
21
Page Title
Designed:
Approved:
JNO
JNO
Size
BOM Doc No:
Title Page
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
1 of
21
3
C1 100P
P2
2
U1A
8
1
4
1
C4
100N
NM
R11
24R9
R12
10K
ANALOG_DIFF_P
R9
1
AGND
R5
49R9
(p 16,18)
4
5
AGND
ANALOG_SE_B (p 16,18)
C5
1K
ST3
BNC
D
22P
R8 49R9
AD8132ARM
R10 390R
AGND
(p 16,18)
TP103
2
3
C6
C7
22P
22P
1
R6
10K
(p 16,18) ANALOG_DIFF_VCM
ANALOG_DIFF_N
C3
390P
2
R7
49R9
P3
ST2
22P
5
-
VDIFFAMP
BNC
C2
R4 49R9
+
ST1
ANALOG_SE_A (p 16,18)
1K
1
R3 390R
BNC
4
5
TP101 TP102
R1 390R
GND
R252
0R
1
TP100
R2
1
1
4
5
D
2
2
3
2
4
TP99
P1
2
3
2
5
SE -> Diff Input
AGND
AGND
AGND
R13 390R
R14
49R9
C8 100P
AGND
AGND
AGND
R262 1K
C16 10U
C10 220P
TP105
TP106
R19
15K
3
5
R17 15K
C9 150P
TP104
R20 27K
U2A
2
LINE_IN_RIGHT
U3B
C14
R22 10R
4
2
1
C
R30
1K
C12
680P
VLINE_IN
AGND
AUDIO_IN_RIGHT
+
R23 7K5
R24 7K5
8
(p 16,18) (p 16,18) AUDIO_OUT_RIGHT
C13
10N
R16 47K
AGND
1
1
3
SJ1-3515
AGND
Single-Ended Inputs/Outputs
R15 15K
TP161
J2
AGND AGND
1U
INR
TP107
10
OUTR
J1
R25 10R
3
5
C15
1N
TLV2473IDGQ
MAX9724A
AGND
C
4
2
1
R26 10R
AGND
GND
R27 15K
R21
47K
C11
100N
SJ1-3515
TP108
C18 220P
TP109
R28 15K
C19
C20
10N
10N
U3A
TP162
AGND
C21 150P
TP110
R263
C17 10U
R36 27K
1K
R35
15K
R29
1K
R32 7K5
6
-
1U
AO_SGND
R33 7K5
(p 16,18) AUDIO_OUT_LEFT
U2B
8
LINE_IN_LEFT
C22
TP111
AO_SGND AO_SGND
INL
11
OUTL
C23
1N
R38 10R
C25
680P
2
7
AGND
9
AUDIO_IN_LEFT
MAX9724A
(p 16,18)
C26
10N
+
GND
TLV2473IDGQ
AGND
AGND
Line In Amplifier & Filter
Line Out Driver & Filter
B
B
C27 1U
Power Supply and Decoupling
U3C
1
VDIFFAMP TP25
3V3
U1B
R42
V+
6
V-
NC
7
5
10R
3
1
C32
100P
C33
100N
C34
10U
L3
C1P
C1N
3
TP23
(p 9,16) AUDIO_OUT_CONNECT
2
R39
47K
BLM21B102S
TP98
5V
SVSS
SGND
VDD
PVSS
PGND
9
7
0R R40
1
2
BLM21B102S
AD8132ARM
SHDN
L1
12
GND
C29
C30
C31
10U
10N
100P
4
2
C28
1U
MAX9724A
AGND
3V3
VLINE_IN
TP153
TP24
R41
10R
U2C
A (p 9,16)
5
AUDIO_IN_CONNECT
6
R43
47K
4
11
AGND
1SHDN
VDD
10
L2
GND
GND
GND_HEAT
C35
C36
C37
100P
10N
10U
AO_SGND
AO_SGND
A
EFM32 Development Kit - Mainboard
AO_SGND
Page Title
TLV2473IDGQ
GND
AGND
Designed:
Approved:
JNO
JNO
Size
BOM Doc No:
Analog Interfaces
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
AGND
GND
Schematic Title
1
2
BLM21B102S
2SHDN
GND
<Schematic Path>
TOP
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
2 of
21
5
4
U36A
7
8
9
(p 16,18) IF_RS232_A_TX
(p 16,18) IF_RS232_A_#RTS
(p 11,16,18) IF_RS232_B_TX
(p 16,18) IF_RS232_A_RX
(p 16,18) IF_RS232_A_#CTS
(p 11,16,18) IF_RS232_B_RX
D
T_IN1
T_IN2
T_IN3
10
11
12
5
9
4
8
3
7
2
6
1
RS232_A_TX
RS232_A_#RTS
RS232_B_TX
GND
15
14
13
R_IN1
R_IN2
R_IN3
RS232_A_RX
RS232_A_#CTS
RS232_B_RX
1
(p 16,18) IF_IRDA_TXD
(p 16,18) IF_IRDA_RXD
10
0R
R165
0R
3
4
5
(p 9) IF_IRDA_SHUTDOW N
11
R164
3V3
1
R169
100K
2
R170
TP89
10R
GND
TYCO_5747844_6
SD
5
2
U43
18
17
16
T_OUT1
T_OUT2
T_OUT3
R_OUT1
R_OUT2
R_OUT3
19
(p 9) IF_RS232_SHUTDOW N
3
P9
ADM3315E
R171
47R
GND
7
6
P10
EN
(p 11,16,18) CTRLMCU_RS232_B_TX
(p 11,16,18) CTRLMCU_RS232_B_RX
C161
10U
5
9
4
8
3
7
2
6
1
GND
C162
100N
C163
C164
10U
100N
8
10
TX
TXD
RXD
SD
VCC2 (An)
Cat
RX
D
VLOG
VCC1
GND
TFDU4300
11
GND
GND
RS232 Physical Layer
IrDA transceiver
TYCO_5747844_6
3V3
3V3
U38
6
MMA7361L
VDD
3V3
XOUT
2
SENSOR_ACCEL_XOUT (p 16,18)
SENSOR_ACCEL_YOUT (p 16,18)
SENSOR_ACCEL_ZOUT (p 16,18)
C147
100N
5
C
GND
VSS
YOUT
RP6
PDV-P9003
R144
10K
3
(p 15,18) SENSOR_POTMETER
(p 15,18) SENSOR_AMBIENT_LIGHT
C
GND
10
(p 9) SENSOR_ACCEL_GSEL
GSEL
7
13
(p 9,16) SENSOR_ACCEL_CONNECT
(p 9) SENSOR_ACCEL_SELFTEST
ZOUT
SLEEP
SELFTEST
0GDET
4
R145
10K
RP7
100K
C148
C149
C150
3N3
3N3
3N3
9
GND
NC
NC
NC
NC
NC
GND
R157
100K
Ambient Light
Potmeter
GND
1
12
11
8
14
R156
100K
GND
GND
3V3 3V3
GND GND
3-axis accelerometer
R159
4K7
R160
4K7
3V3
R161 0R
3V3
R255
0R
(p 15,18) I2C_BUS_SDA
(p 15,18) I2C_BUS_SCL
TP88
R162 0R
U41A
5
6
R272 0R
(p 15,18) SPI_BUS_MOSI
R273
47K
(p 9) SPI_BUS_MICROSD_#CS
R325
47K
NM
R254
0R
R326
47K
NM
R274
47K
R275
47K
1
2
3
P16
1
2
3
4
5
6
7
8
B
(p 15,18) SPI_BUS_MISO
(p 15,18) SPI_BUS_SCLK
R257
0R
3V3 3V3
U45A
5
1
9) SPI_BUS_FLASH_#CS
R256
0R
6
M25PX16
2
Q
D
R172
100K
S
C
HOLD
W
R173
100K
C249
100N
DAT2
CD / DAT3
CMD
VDD
CLK
VSS
DAT0
DAT1
1
2
SDA
SCL
A0
A1
A2
R163
100K
U42A STDS75
WP
SDA
SCL
O.S.
A0
A1
A2
7
3
7
6
5
B
24AA024
GND
R168
4K7
2 Kbit EEPROM
I2C Bus
microSD
GND
Temperature Sensor
GND
7
3
R370
0R
NM
SPI microSD
GND
SPI Flash
GND
Power & Decoupling
6
2
24
A
21
U36B
ADM3315E
C1+
C2+
C3+
C1C2C3-
V-
VCC
C156
100N
GND
V+
C152
C151
100N
100N
100N
Schematic Title
3V3
3V3
3
100N
1
3V3
U45B M25PX16
8
VCC
C159
10U
100N
4
U42B
VCC
C167
100N
VSS
4
8
VDD
C168
10N
VSS
24AA024
4
8
Page Title
C169
10N
GND
STDS75
Designed:
Approved:
JNO
JNO
Size
GND
GND
BOM Doc No:
Sensors, SPI bus, I2C bus and IO
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
GND
GND
A
EFM32 Development Kit - Mainboard
3V3
U41B
C158
GND
GND
<Schematic Path>
TOP
20
4
22
C157
23
C153
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
3 of
21
5
4
3
2
220R
LED103
YELLOW
UIF_DIP[7..0]
LED104
YELLOW
LED106
YELLOW
LED107
YELLOW
2
1
9
LED117
YELLOW
LED118
YELLOW
14
13
1
15
1
16
2
2
2
LED116
YELLOW
1
4
LED115
YELLOW
1
R187
100R
2
LED111
YELLOW
10
1
1
220R
3
LED112
YELLOW
11
2
UIF_LEDS3
SW 3
2
2
LED113
YELLOW
R330
3V3
1
5
1
LED114
YELLOW
12
R186
100K
6
2
2
220R
User switches
R185
100K
LED110
YELLOW
1
1
7
1
8
LED109
YELLOW
R329
UIF_LEDS2
R184
100K
D
2
LED108
YELLOW
1
220R
2
UIF_LEDS1
GND
R183
100K
1
R328
SW _DIP8_SMD
UIF_PB[3..0]
2
1
1
3
1
4
15
14
13
12
11
10
9
1
ON 16
2
1
1
2
3
4
5
6
7
8
UIF_DIP0
UIF_DIP1
UIF_DIP2
UIF_DIP3
UIF_DIP4
UIF_DIP5
UIF_DIP6
UIF_DIP7
UIF_LEDS4
UIF_PB0
UIF_PB1
UIF_PB2
UIF_PB3
C
GND
C
SW 4
C170
C171
C172
C173
1
3
10N
10N
10N
10N
2
4
R188
100R
Inputs
zzz01
zz0z1
z0zz1
0zzz1
zzz10
zz01z
z0z1z
0zz1z
zz1z0
zz10z
z01zz
0z1zz
z1zz0
z1z0z
z10zz
01zzz
GND
GND
GND
GND
SW 5
GND
R189
100R
1
3
2
4
GND
SW 6
(p 8)
LED105
YELLOW
SW 2
D
(p 8) UIF_PB[3..0]
2
2
2
R327
UIF_LEDS0
2
(p 9) UIF_LEDS[4..0]
R175 R176 R177 R178 R179 R180 R181 R182
10K
10K
10K
10K
10K
10K
10K
10K
(p 7) UIF_DIP[7..0]
1
User LEDs
3V3
AEM_PB
R190
100R
1
3V3
3
2
4
GND
R219
100K
SW 10
C246
R220
100R
1
3
2
4
LED
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
10N
BUser pushbuttons
B
GND
3V3
R191 R192 R193 R194 R195
100K 100K 100K 100K 100K
SW 7
1
(p 8)UIF_JOYSTICK[4..0]
6
UIF_JOYSTICK3
UIF_JOYSTICK4
UIF_JOYSTICK0
UIF_JOYSTICK1
UIF_JOYSTICK2
2
5
4
10N
10N
10N
10N
10N
<Schematic Path>
TOP
3
C174 C175 C176 C177 C178
R196
100R
Schematic Title
A
GND
GND
Page Title
Designed:
Approved:
JNO
JNO
Size
Joystick
A
EFM32 Development Kit - Mainboard
BOM Doc No:
User Interfaces
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
4 of
21
5
4
3
2
1
3V3
3V3 3V3
R115
47K
D
(p 7)
(p 7)
(p 7)
(p 7)
(p 7)
DISP1
R114
68K
TP60TP61TP62TP63
DISPLAY_#RESET
DISPLAY_DC
DISPLAY_#RD
DISPLAY_#W R
DISPLAY_#CS
P7
TP130
R267 0R
NM
R268 0R
NM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
R269 0R
NM
(p 9) DISPLAY_W SYNC
DISPLAY_DATA17
DISPLAY_DATA16
DISPLAY_DATA15
DISPLAY_DATA14
DISPLAY_DATA13
DISPLAY_DATA12
DISPLAY_DATA11
DISPLAY_DATA10
DISPLAY_DATA9
DISPLAY_DATA8
DISPLAY_DATA7
DISPLAY_DATA6
DISPLAY_DATA5
DISPLAY_DATA4
DISPLAY_DATA3
DISPLAY_DATA2
DISPLAY_DATA1
(p 7,8,9) DISPLAY_DATA[17..1]
HEADER_2X10_1.27MM_SMD
P17
1
3
5
7
9
11
13
15
17
19
DISPLAY_DATA1
DISPLAY_DATA3
DISPLAY_DATA5
DISPLAY_DATA7
DISPLAY_DATA9
DISPLAY_DATA11
DISPLAY_DATA13
DISPLAY_DATA15
DISPLAY_DATA17
C
2
4
6
8
10
12
14
16
18
20
DISPLAY_DATA2
DISPLAY_DATA4
DISPLAY_DATA6
DISPLAY_DATA8
DISPLAY_DATA10
DISPLAY_DATA12
DISPLAY_DATA14
DISPLAY_DATA16
NM
DISPLAY_#RESET
DISPLAY_DC
GND
(p 9) DISPLAY_16BIT_#EN
3V3
TFT_LEDA
Can be used
to select
SPI mode
TFT_LEDK
R110
47K
NM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DISPLAY_DATA17
DISPLAY_DATA16
DISPLAY_DATA15
DISPLAY_DATA14
DISPLAY_DATA13
DISPLAY_DATA12
DISPLAY_DATA11
DISPLAY_DATA10
DISPLAY_DATA9
DISPLAY_DATA8
DISPLAY_DATA7
DISPLAY_DATA6
DISPLAY_DATA5
DISPLAY_DATA4
DISPLAY_DATA3
DISPLAY_DATA2
DISPLAY_DATA1
TFT_LEDA TFT_LEDK
USMH_8252MD_320X240_RGB
NM
R112
47K
D
P15
VCI
VCI
VSS
VDDIO
VSS
RESB
DC / SDC
E / RD
R/W / WR
CS / SCS
SCL
SDO
SDI
WSYNC
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VSS
DOTCLK
HSYNC
VSYNC
OE
VSS
PS0
PS1
PS2
PS3
VSS
NC
NC
NC
NC
VSS
K
A
VCI
VCI
VSS
VDDIO
VSS
RESB
DC / SDC
E / RD
R/W / WR
CS / SCS
SCL
SDO
SDI
WSYNC
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VSS
DOTCLK
HSYNC
VSYNC
OE
VSS
PS0
PS1
PS2
PS3
VSS
NC
NC
NC
NC
VSS
K
A
USMH-8252MD 320x240 TFT-LCD MODULE
Bus Interface Table
0010
16 bit 8080 style parallel
1011
9 bit 8080 style parallel
1111
4-wire SPI
C
USMH_8252MD_320X240_RGB
GND
GND
GND
B
R363
100R
NM
C292
100N
NM
B
TP120 TFT_LEDA
5V
L11
L5
R276
330K
D1
2
2
10U
U31
C133
C134
1U
100N
NCP5006
VBAT
VOUT
1
GND
R132
10K
GND
GND
EN
2
4
(p 7) DISPLAY_PW R_ENABLE
A
FB
100N
GND
3
TFT_LEDK
R362
R277
1K
<Schematic Path>
TOP
GND
DISPLAY_KSENSE
C113
C114
C115
C131
C144
C129
10U
NM
100N
NM
100N
NM
10U
100N
100N
C293
TP159
GND
R131
15R
100N
GND
GND
TFT-LCD power regulator
GND
A
EFM32 Development Kit - Mainboard
C251
R279
100K
GND
Schematic Title
(p 21)
0R
100N
NM
GND
R278
27K
DFLZ24
2
GND
For P15
(p 21)
C250
D6
5
3V3
For P7
DISPLAY_ASENSE
C132
BLM41P600S
3V3
1
1
1
10UH
Page Title
Designed:
Approved:
JNO
JNO
Size
BOM Doc No:
Display Interface
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
5 of
21
5
4
3
2
1
(p 8) FPGA_DATA[15..0]
(p 8) FPGA_ADDR[23..0]
D
D
U25A
U52A
3V3
R211
47K
C
FPGA_ADDR21
FPGA_ADDR0
FPGA_ADDR1
FPGA_ADDR2
FPGA_ADDR3
FPGA_ADDR4
FPGA_ADDR5
FPGA_ADDR6
FPGA_ADDR7
FPGA_ADDR8
FPGA_ADDR9
FPGA_ADDR10
FPGA_ADDR11
FPGA_ADDR12
FPGA_ADDR13
FPGA_ADDR14
FPGA_ADDR15
FPGA_ADDR16
FPGA_ADDR17
FPGA_ADDR18
FPGA_ADDR19
FPGA_ADDR20
A3
A4
A5
B3
B4
C3
C4
D4
H2
H3
H4
H5
G3
G4
F3
F4
E4
D3
H1
G2
H6
E3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21/GND
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9
IO10
IO11
IO12
IO13
IO14
IO15
B6
C5
C6
D5
E5
F5
F6
G6
B1
C1
C2
D2
E2
F2
F1
G1
FPGA_DATA0
FPGA_DATA1
FPGA_DATA2
FPGA_DATA3
FPGA_DATA4
FPGA_DATA5
FPGA_DATA6
FPGA_DATA7
FPGA_DATA8
FPGA_DATA9
FPGA_DATA10
FPGA_DATA11
FPGA_DATA12
FPGA_DATA13
FPGA_DATA14
FPGA_DATA15
E2
D2
C2
A2
B2
D3
C3
A3
B6
A6
C6
D6
B7
A7
C7
D7
E7
B3
C4
D5
D4
C5
B8
C8
F8
G8
FPGA_ADDR0
FPGA_ADDR1
FPGA_ADDR2
FPGA_ADDR3
FPGA_ADDR4
FPGA_ADDR5
FPGA_ADDR6
FPGA_ADDR7
FPGA_ADDR8
FPGA_ADDR9
FPGA_ADDR10
FPGA_ADDR11
FPGA_ADDR12
FPGA_ADDR13
FPGA_ADDR14
FPGA_ADDR15
FPGA_ADDR16
FPGA_ADDR17
FPGA_ADDR18
FPGA_ADDR19
FPGA_ADDR20
FPGA_ADDR21
FPGA_ADDR22
FPGA_ADDR23
3V3
R117
47K
B5
A6
(p 7) FPGA_SRAM_#CS
(p 11) CTRLMCU_SRAM_#ZZ
A2
G5
(p 7) FPGA_#OE
(p 7) FPGA_#W E
3V3
C
GND
A4
A1
B2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15__A-1
FPGA_DATA0
FPGA_DATA1
FPGA_DATA2
FPGA_DATA3
FPGA_DATA4
FPGA_DATA5
FPGA_DATA6
FPGA_DATA7
FPGA_DATA8
FPGA_DATA9
FPGA_DATA10
FPGA_DATA11
FPGA_DATA12
FPGA_DATA13
FPGA_DATA14
FPGA_DATA15
TP69
R212 0R NM
(p 7) FPGA_SRAM_#LB
(p 7) FPGA_SRAM_#UB
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
E3
H3
E4
H4
H5
E5
H6
E6
F3
G3
F4
G4
F5
G6
F6
G7
LB
UB
F2
CS
NC
FPGA_#OE
G2
FPGA_#W E
A5
OE
WE
B4
F7
CY62147EV30LL-45BVXI
B5
R213
47K
R116
47K
RY/BY
CE
OE
WE
WP/ACC
BYTE
RESET
TP74
S29GLxxx_FBGA
Write Protect
GND
(p 7) FPGA_FLASH_#CS
(p 7) FPGA_FLASH_#BYTE
(p 7) FPGA_FLASH_#RESET
R118
47K
NM
B
B
GND
<Schematic Path>
TOP
3V3
3V3
U25B
G5
U52B
A
D6
E1
C116
100N
C117
100N
VDD
VDD
C118
100N
C119
100N
D1
E6
GND
GND
CY62147EV30LL-45BVXI
GND
D8
F1
H2
E8
H7
VCC
VIO
VIO
VSS
VSS
VSS
RFU1
RFU2
RFU3
RFU4
RFU5
RFU6
RFU7
RFU9
RFU10
S29GLxxx_FBGA
GND
A1
B1
C1
D1
E1
G1
H1
H8
A8
Schematic Title
A
EFM32 Development Kit - Mainboard
Page Title
Designed:
Approved:
JNO
JNO
Size
BOM Doc No:
Parallel bus memory
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
6 of
21
5
4
3
2
1
(p 9,12) CTRLMCU_ADDR[21..16]
D
D
TP26 TP27 TP28 TP29
TP30 TP31
TP33
CTRLMCU_ADDR20
CTRLMCU_ADDR19
CTRLMCU_ADDR21
FPGA_VCCO2
U6C
FPGA_CFG_M0
FPGA_CFG_M1
(p 6) FPGA_FLASH_#CS
(p 6) FPGA_FLASH_#BYTE
(p 6) FPGA_FLASH_#RESET
(p 6) FPGA_SRAM_#CS
(p 5) DISPLAY_PW R_ENABLE
FPGA_CFG_M2
FPGA_CFG_M2
FPGA_CFG_RD#W R
(p 6) FPGA_SRAM_#LB
(p 6) FPGA_SRAM_#UB
(p 6) FPGA_#OE
(p 6) FPGA_#W E
(p 9,12) CTRLMCU_DATA[15..0]
CTRLMCU_DATA11
CTRLMCU_DATA12
FPGA_CFG_D6
FPGA_CFG_D7
(p 5) DISPLAY_#RD
(p 5) DISPLAY_#W R
CTRLMCU_DATA9
CTRLMCU_DATA10
C
FPGA_CFG_D4
FPGA_CFG_D5
(p 5) DISPLAY_#RESET
(p 5) DISPLAY_DC
(p 5) DISPLAY_#CS
DISPLAY_DATA17
DISPLAY_DATA16
(p 5,8,9) DISPLAY_DATA[17..1]
(p 10) FPGA_CLK
(p 12) CTRLMCU_FSMC_CLK
DISPLAY_DATA15
DISPLAY_DATA14
DISPLAY_DATA13
FPGA_CFG_#CS
DISPLAY_DATA12
DISPLAY_DATA11
DISPLAY_DATA10
DISPLAY_DATA9
CTRLMCU_DATA8
CTRLMCU_DATA6
CTRLMCU_DATA7
FPGA_CFG_D3
FPGA_CFG_#INIT
FPGA_CFG_D1
FPGA_CFG_D2
CTRLMCU_DATA3
CTRLMCU_DATA4
CTRLMCU_DATA5
FPGA_CFG_CCLK
FPGA_CFG_D0
3V3
R199
4K7
UIF_DIP7
UIF_DIP6
UIF_DIP5
UIF_DIP4
UIF_DIP3
UIF_DIP2
UIF_DIP1
UIF_DIP0
(p 17) FPGA_#INT
(p 11) CTRLMCU_FPGA_#INT
B
P4
N4
T2
R2
T3
R3
P5
N6
R5
T4
T6
T5
P6
N7
N8
P7
T7
R7
T8
P8
P9
N9
T9
R9
M10
N10
P10
T10
R11
T11
N11
P11
P12
T12
R13
T13
P13
N12
R14
T14
L7
L8
L9
L10
M7
M8
M11
N5
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
IO_L03N_2/VS2
IO_L03P_2/RDWR_B
IO_L04N_2/VS0
IO_L04P_2/VS1
IO_L05N_2
IO_L05P_2
IO_L06N_2/D6
IO_L06P_2/D7
IO_L07N_2
IO_L07P_2
IO_L08N_2/D4
IO_L08P_2/D5
IO_L09N_2/GCLK13
IO_L09P_2/GCLK12
IO_L10N_2/GCLK15
IO_L10P_2/GCLK14
IO_L11N_2/GCLK1
IO_L11P_2/GCLK0
IO_L12N_2/GCLK3
IO_L12P_2/GCLK2
IO_L13N_2
IO_L13P_2
IO_L14N_2/MOSI/CSI_B
IO_L14P_2
IO_L15N_2/DOUT
IO_L15P_2/AWAKE
IO_L16N_2
IO_L16P_2
IO_L17N_2/D3
IO_L17P_2/INIT_B
IO_L18N_2/D1
IO_L18P_2/D2
IO_L19N_2
IO_L19P_2
IO_L20N_2/CCLK
IO_L20P_2/D0/DIN/MISO
VCCO_2
VCCO_2
VCCO_2
VCCO_2
C
IP0_2
IP1_2
IP2_2/VREF_2
IP3_2/VREF_2
IP4_2/VREF_2
IP5_2/VREF_2
IP6_2/VREF_2
IP7_2/VREF_2
B
(p 4) UIF_DIP[7..0]
FPGA Init LED
FPGA_VCCO2
M9
R4
R8
R12
XC3S200A_4_FT256C_SWAP0
<Schematic Path>
TOP
FPGA Configuration Mode
2
Schematic Title
A
A
EFM32 Development Kit - Mainboard
FPGA_CFG_M2
FPGA_CFG_M1
FPGA_CFG_M0
Page Title
1
LED79
YELLOW
R52
1K
NM
R55
2K
R53
1K
NM
R54
1K
Designed:
Approved:
JNO
JNO
Size
GND
GND
GND
BOM Doc No:
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
FPGA_CFG_#INIT
Board Control - Control MCU Interface
Document number
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
7 of
21
5
4
TP34 TP35 TP36 TP37 TP38 TP39 TP40 TP41
3
TP42 TP43 TP44 TP45
2
1
FPGA_VCCO3
U6D
FPGA_DATA0
FPGA_DATA1
FPGA_DATA2
FPGA_DATA3
FPGA_DATA4
FPGA_DATA5
FPGA_DATA6
FPGA_DATA7
FPGA_DATA8
FPGA_DATA9
FPGA_DATA10
FPGA_DATA11
FPGA_DATA12
FPGA_DATA13
FPGA_DATA14
FPGA_DATA15
D
FPGA_ADDR0
FPGA_ADDR1
FPGA_ADDR2
FPGA_ADDR3
FPGA_ADDR4
FPGA_ADDR5
FPGA_ADDR6
FPGA_ADDR7
FPGA_ADDR8
FPGA_ADDR9
FPGA_ADDR10
FPGA_ADDR11
FPGA_ADDR12
FPGA_ADDR13
FPGA_ADDR14
FPGA_ADDR15
FPGA_ADDR16
FPGA_ADDR17
FPGA_ADDR18
FPGA_ADDR19
FPGA_ADDR20
FPGA_ADDR21
FPGA_ADDR22
FPGA_ADDR23
6) FPGA_DATA[15..0]
6) FPGA_ADDR[23..0]
C
(p 4) UIF_PB[3..0]
F4
E4
G5
G6
J7
H7
K6
K5
L6
L5
UIF_PB0
UIF_PB1
UIF_PB2
UIF_PB3
UIF_JOYSTICK4
UIF_JOYSTICK3
UIF_JOYSTICK2
UIF_JOYSTICK1
UIF_JOYSTICK0
(p 4) UIF_JOYSTICK[4..0]
(p 4)
F3
H3
D1
E2
P1
P2
E3
H1
H6
J3
J4
J2
L3
L1
L2
L4
H5
C2
C1
F1
G3
K4
J1
E1
M4
N1
K1
K3
N3
M3
N2
M1
D4
H4
J6
R1
G1
G2
G4
D3
IO_L07P_3
IO_L12P_3/LHCLK2
IO_L03P_3
IO_L05N_3
IO_L22N_3
IO_L23N_3
IO_L05P_3
IO_L11N_3/LHCLK1
IO_L10P_3
IO_L12N_3/IRDY2/LHCLK3
IO_L17P_3
IO_L14P_3/LHCLK4
IO_L18N_3
IO_L16P_3/VREF_3
IO_L16N_3
IO_L19N_3
IO_L10N_3
IO_L01P_3
IO_L01N_3
IO_L08P_3
IO_L09P_3
IO_L18P_3
IO_L14N_3/LHCLK5
IO_L03N_3
IO_L24N_3
IO_L20N_3
IO_L15N_3/LHCLK7
IO_L15P_3/TRDY2/LHCLK6
IO_L24P_3
IO_L19P_3
IO_L22P_3
IO_L20P_3
IO_L02P_3
IO_L09N_3
IO_L17N_3
IO_L23P_3
IO_L08N_3/VREF_3
IO_L11P_3/LHCLK0
IO_L07N_3
IO_L02N_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
D2
H2
J5
M2
D
C
IP_L04N_3/VREF_3
IP_L04P_3
IP_L06N_3/VREF_3
IP_L06P_3
IP_L13N_3
IP_L13P_3
IP_L21N_3
IP_L21P_3
IP_L25N_3/VREF_3
IP_L25P_3
AEM_PB
XC3S200A_4_FT256C_SWAP0
FPGA_VCCO0
U6A
(p 5,7,9) DISPLAY_DATA[17..1]
B
(p 14) BC_BUS_FPGA_#OE[3..0]
(p 14) BC_BUS_FPGA_DIR[3..0]
A
(p 14) BC_BUS_FPGA[27..0]
(p 14) BC_BUS_CONNECT_SPI
DISPLAY_DATA8
DISPLAY_DATA7
BC_BUS_FPGA_#OE1
BC_BUS_FPGA_DIR1
DISPLAY_DATA6
DISPLAY_DATA5
BC_BUS_FPGA_#OE0
BC_BUS_FPGA_#OE2
BC_BUS_FPGA_#OE3
BC_BUS_FPGA_DIR0
BC_BUS_FPGA_DIR2
BC_BUS_FPGA_DIR3
BC_BUS_FPGA27
BC_BUS_FPGA26
BC_BUS_FPGA25
BC_BUS_FPGA24
BC_BUS_FPGA23
BC_BUS_FPGA22
BC_BUS_FPGA21
BC_BUS_FPGA20
BC_BUS_FPGA19
BC_BUS_FPGA18
BC_BUS_FPGA17
BC_BUS_FPGA16
BC_BUS_FPGA15
BC_BUS_FPGA14
BC_BUS_FPGA13
BC_BUS_FPGA12
BC_BUS_FPGA11
BC_BUS_FPGA10
BC_BUS_FPGA9
BC_BUS_FPGA8
BC_BUS_FPGA7
BC_BUS_FPGA6
BC_BUS_FPGA5
BC_BUS_FPGA4
BC_BUS_FPGA3
BC_BUS_FPGA2
BC_BUS_FPGA1
BC_BUS_FPGA0
BC_BUS_CONNECT_SPI
BOARD_REVISION2
BOARD_REVISION1
BOARD_REVISION0
PCB_REVISION2
PCB_REVISION1
PCB_REVISION0
C13
D13
B14
B15
D11
C12
A8
E10
B8
C8
C9
D8
A9
D9
A10
B10
A11
A12
B12
A13
A14
C10
C11
D10
D5
C4
C5
E7
D7
C6
C7
B3
A3
B4
A4
A5
F8
B6
A6
A7
D6
D12
E6
F7
F9
F10
E9
IO_L01N_0
IO_L01P_0
IO_L02N_0
IO_L02P_0/VREF_0
IO_L03N_0
IO_L03P_0
IO_L12P_0/GCLK10
IO_L06N_0/VREF_0
IO_L12N_0/GCLK11
IO_L11P_0/GCLK8
IO_L10P_0/GCLK6
IO_L11N_0/GCLK9
IO_L10N_0/GCLK7
IO_L09N_0/GCLK5
IO_L08N_0
IO_L08P_0
IO_L07N_0
IO_L05N_0
IO_L05P_0
IO_L04N_0
IO_L04P_0
IO_L09P_0/GCLK4
IO_L07P_0
IO_L06P_0
IO_L20N_0/PUDC_B
IO_L20P_0/VREF_0
IO_L17N_0
IO_L14N_0/VREF_0
IO_L16P_0
IO_L16N_0
IO_L13N_0
IO_L19N_0
IO_L19P_0
IO_L18N_0
IO_L18P_0
IO_L17P_0
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L13P_0
IP0_0
IP1_0
IP2_0
IP3_0
IP4_0
IP5_0
IP6_0/VREF_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
B5
E8
B9
B13
FPGA_VCCO0
FPGA_VCCO0
PCB_REVISION2
PCB_REVISION1
PCB_REVISION0
B
R58
100K
NM
R59
100K
NM
R60
100K
NM
R63
100K
R64
100K
R65
100K
PCB_REVISION[2:0]
GND
GND
BOARD_REVISION2
BOARD_REVISION1
BOARD_REVISION0
BOARD_REVISION[2:0]
GND
GND
GND
<Schematic Path>
TOP
Schematic Title
A
EFM32 Development Kit - Mainboard
Page Title
XC3S200A_4_FT256C_SWAP0
Designed:
Approved:
JNO
JNO
Size
BOM Doc No:
Board Control - Memory & BC bus
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
8 of
21
5
D
4
3
2
1
(p 5,7,8) DISPLAY_DATA[17..1]
DISPLAY_DATA4
DISPLAY_DATA3
DISPLAY_DATA2
DISPLAY_DATA1
D
FPGA_VCCO1
U6B
(p 21) ADC_DIN
(p 21) ADC_#CS
(p 4) UIF_LEDS[4..0]
(p 3) SPI_BUS_FLASH_#CS
(p 3) SPI_BUS_MICROSD_#CS
UIF_LEDS4
UIF_LEDS3
(p 3,16) SENSOR_ACCEL_CONNECT
UIF_LEDS2
UIF_LEDS1
UIF_LEDS0
(p 12) CTRLMCU_FSMC_#W AIT
(p 3) SENSOR_ACCEL_GSEL
(p 3) SENSOR_ACCEL_SELFTEST
(p 21) ADC_CLK
(p 15) SENSOR_AMBIENT_LIGHT_CONNECT
(p 15) SENSOR_POTMETER_CONNECT
(p 16) IF_RS232_A_CONNECT
(p 16) IF_RS232_B_CONNECT
(p 3) IF_RS232_SHUTDOW N
(p 15) SPI_BUS_CONNECT
(p 15) IF_I2C_BUS_CONNECT
(p 16) IF_IRDA_CONNECT
(p 3) IF_IRDA_SHUTDOW N
(p 16) ANALOG_SE_CONNECT
(p 16) ANALOG_DIFF_CONNECT
(p 2,16) AUDIO_OUT_CONNECT
(p 2,16) AUDIO_IN_CONNECT
C
(p 5) DISPLAY_16BIT_#EN
(p 17) FPGA_MCU_#RESET
CTRLMCU_DATA15
CTRLMCU_DATA14
CTRLMCU_DATA13
CTRLMCU_DATA2
(p 7,12) CTRLMCU_DATA[15..0]
(p 7,12) CTRLMCU_ADDR[21..16]
CTRLMCU_DATA1
CTRLMCU_DATA0
CTRLMCU_ADDR16
CTRLMCU_ADDR17
CTRLMCU_ADDR18
(p 12)
(p 12)
(p 12)
(p 11)
CTRLMCU_FSMC_#OE
CTRLMCU_FSMC_#W E
CTRLMCU_FSMC_#E1
CTRLMCU_FSMC_#ADV
(p 21) ADC_DOUT
(p 5) DISPLAY_W SYNC
(p 15,18) SPI_BUS_#CS
(p 12) BC_BUS_CONNECT_EBI
N14
N13
P15
R15
N16
P16
M14
M13
K13
L13
M16
M15
L16
L14
J13
J12
K14
K15
J16
K16
H14
J14
H16
H15
F16
G16
G14
H13
F15
E16
F14
G13
F13
E14
D15
D16
D14
E13
C15
C16
K12
K11
J11
J10
H11
H10
G11
G12
F11
F12
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
IO_L02P_1/LDC1
IO_L03N_1/A1
IO_L03P_1/A0
IO_L05N_1/VREF_1
IO_L05P_1
IO_L06N_1/A3
IO_L06P_1/A2
IO_L07N_1/A5
IO_L07P_1/A4
IO_L08N_1/A7
IO_L08P_1/A6
IO_L10N_1/A9
IO_L10P_1/A8
IO_L11N_1/RHCLK1
IO_L11P_1/RHCLK0
IO_L12N_1/TRDY1/RHCLK3
IO_L12P_1/RHCLK2
IO_L14N_1/RHCLK5
IO_L14P_1/RHCLK4
IO_L15N_1/RHCLK7
IO_L15P_1/IRDY1/RHCLK6
IO_L16N_1/A11
IO_L16P_1/A10
IO_L17N_1/A13
IO_L17P_1/A12
IO_L18N_1/A15
IO_L18P_1/A14
IO_L19N_1/A17
IO_L19P_1/A16
IO_L20N_1/A19
IO_L20P_1/A18
IO_L22N_1/A21
IO_L22P_1/A20
IO_L23N_1/A23
IO_L23P_1/A22
IO_L24N_1/A25
IO_L24P_1/A24
IP_L04N_1/VREF_1
IP_L04P_1
IP_L09N_1
IP_L09P_1/VREF_1
IP_L13N_1
IP_L13P_1
IP_L21N_1
IP_L21P_1/VREF_1
IP_L25N_1
IP_L25P_1/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
SUSPEND
E15
H12
J15
N15
R16
R78
10K
GND
C
XC3S200A_4_FT256C_SWAP0
B
B
<Schematic Path>
TOP
Schematic Title
A
A
EFM32 Development Kit - Mainboard
Page Title
Designed:
Approved:
JNO
JNO
Size
BOM Doc No:
Board Control - Misc
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
9 of
21
5
4
3
2
1
2
FPGA_VCCAUX
1
LED80
YELLOW
R68
470R
D
D
U6E
T15
A2
FPGA_CFG_DONE
FPGA_CFG_#PROG
(p 12) FPGA_CFG_DONE
(p 12) FPGA_CFG_#PROG
2
B2
A15
B16
B1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TMS
TCK
TDO
TDI
1
LED81
GREEN
DONE
PROG_B
R71
470R
FPGA_VCCAUX
E11
F5
L12
M6
GND
FPGA_VCCINT
G7
G9
H8
J9
K8
K10
C
U56A 74LVC2G125DC
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
A1
A16
B7
B11
C3
C14
E5
E12
F2
F6
G8
G10
G15
H9
J8
K2
K7
K9
L11
L15
M5
M12
P3
P14
R6
R10
T1
T16
C
XC3S200A_4_FT256C_SWAP0
2
6
P4
1
3
5
7
9
FH_TRST
FH_TDO
FH_TDI
FH_TMS
FH_TCK
GND
1
2
4
6
8
10
U56B 74LVC2G125DC
5
3
2X5_2.54MM_TH
7
GND
RP13
6
1
2
RP14
1
2
3
4
U57A
(p 12) TEST_#RESET
74LVC2G125DC
8
7
6
5
1
2
3
4
22R
(p 11)
(p 11)
(p 11)
(p 11)
5
7
3
CTRLMCU_JTAG_TMS
CTRLMCU_JTAG_TCK
CTRLMCU_JTAG_TDI
CTRLMCU_JTAG_TDO
0R
R294
22R
NM
U57B
8
7
6
5
74LVC2G125DC
R336
CTRLMCU_JTAG_#TRST (p 11)
B
B
0R
R295
47K
GND
3V3
FPGA_VCCINT
3V3
Control MCU and FPGA clock
3V3
FPGA_1V2
TP155
U7A
R72
U56C
0R
C62
C63
C64
C65
C70
C72
C60
C262
10N
10N
100N
100N
100N
10U
47U
100N
R300
33R
U57C
VCC
8
VCC
8
VCC
4
4
GND
74LVC2G125DC
1
GND
2
74LVC2G125DC
C40
100N
GND
24.00MHz
GND
FPGA_VCCAUX
FPGA_VCCO0
FPGA_VCCO1
GND
OUTPUT
3
CTRLMCU_CLK (p 12)
R200
FPGA_CLK
OE
24.00MHz
<Schematic Path>
TOP
R56
22R
4
GND
A
R57
100K
U7B
(p 7)
22R
TP154
GND
Schematic Title
FPGA_VCCO2
3V3
FPGA_VCCO3
A
EFM32 Development Kit - Mainboard
R73
Page Title
0R
C41
10N
C42
100N
C43
100N
C47
10N
C48
100N
C52
10N
C56
100N
C57
10N
C61
100N
C66
10N
C67
100N
C46
10U
C51
10U
C69
47U
Designed:
Approved:
JNO
JNO
Size
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
GND
BOM Doc No:
Board Control - FPGA Power / Debug
Document number
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
10 of
21
5
4
(p 13)
(p 13)
(p 13)
(p 13)
(p 13)
(p 13)
(p 13)
(p 13)
(p 13)
(p 13)
D
3
DEBUG_#TRST_OUT
DEBUG_TDI_OUT
DEBUG_TMS_SW DIO_OUT
DEBUG_TCK_SW CLK_OUT
DEBUG_#TRST_IN
DEBUG_TDI_IN
DEBUG_TMS_SW DIO_IN
DEBUG_TCK_SW CLK_IN
DEBUG_#RESET_IN
DEBUG_TDO_SW O_IN
R79 1K5
TDO_SW O_IN
USBDM
USBDP
R81 22R
C88
C89
18P
18P
GND
(p 13) DEBUG_BUF_#OE
(p 13) DEBUG_TMS_SW DIO_#OE
(p 9) CTRLMCU_FSMC_#ADV
(p 13) DEBUG_#RESET
(p 12,15,17,18) EEPROM_W P
(p 12,17,18,20) CTRLMCU_I2C_SCL
(p 12,17,18,20) CTRLMCU_I2C_SDA
(p 12) CTRLMCU_SPI_#CS
(p 12) CTRLMCU_SPI_SCK
(p 12) CTRLMCU_SPI_MISO
(p 12) CTRLMCU_SPI_MOSI
C
G2
H2
J2
K2
G3
H3
J3
K3
D9
C9
D10
C10
B10
A10
A9
A8
J4
K4
G5
A7
A6
C5
B5
A5
B4
A4
J7
K7
K8
J8
H8
G8
(p 13) DEBUG_EXT_VDD_TARGET
(p 13) DEBUG_EXT_CABLE_ATTACH
(p 20) AEM_VMCU_ENABLE
GND
1
U17A
#TRST_OUT
TDI_OUT
TMS_OUT
TCK_OUT
#TRST_IN
TDI_IN
TMS_IN
TCK_IN
#RESET_IN
R80 22R
(p 19)
(p 19)
2
F1
F2
E2
F3
G4
H4
F10
E10
F9
E9
B9
B8
C8
A2
A1
B1
(p 7) CTRLMCU_FPGA_#INT
(p 13) DEBUG_DH_SW _ENABLE
(p 13) DEBUG_MCU_SW _ENABLE
(p 17,18) MCU_OSC_TEST
(p 6) CTRLMCU_SRAM_#ZZ
(p 3,16,18) CTRLMCU_RS232_B_TX
(p 3,16,18) CTRLMCU_RS232_B_RX
Control MCU
PA0 / WKUP / USART2_CTS / ADC123_IN0 / TIM2_CH1_ETR / TIM5_CH1 / TIM8_ETR
PA1 / USART2_RTS / ADC123_IN1 / TIM5_CH2 / TIM2_CH2
PA2 / USART2_TX / ADC123_IN2 / TIM5_CH3 / TIM2_CH3
PA3 / USART2_RX / ADC123_IN3 / TIM5_CH4 / TIM2_CH4
PA4 / SPI1_NSS / DAC_OUT1 / USART2_CK / ADC12_IN4
PA5 / SPI1_SCK / DAC_OUT2 / ADC12_IN5
PA6 / SPI1_MISO / TIM8_BKIN / ADC12_IN6 / TIM3_CH1 [TIM1_BKIN]
PA7 / SPI1_MOSI / TIM8_CH1N / ADC12_IN7 / TIM3_CH2 [TIM1_CH1N]
PA8 / USART1_CK / TIM1_CH1 / MCO
PA9 / USART1_TX / TIM1_CH2
PA10 / USART1_RX / TIM1_CH3
PA11 / USART1_CTS / CANRX / TIM1_CH4 / USBDM
PA12 / USART1_RTS / CANTX / TIM1_ETR / USBDP
PA13 / JTMS-SWDIO
PA14 / JTCK-SWCLK
PA15 / JTDI
PORT A
D
PB0 / ADC12_IN8 / TIM3_CH3 / TIM8_CH2N
PB1 / ADC12_IN9 / TIM3_CH4 / TIM8_CH3N
PB2 / BOOT1
PB3 / JTDO / TRACESWO / SPI3_SCK / I2S3_CK [TIM2_CH2 / SPI1_SCK]
PB4 / JNTRST / SPI3_MISO [TIM3_CH2 / SPI1_MISO]
PB5 / I2C1_SMBAI / SPI3_MOSI / I2S3_SD [TIM3_CH2 / SPI1_MOSI]
PB6 / I2C1_SCL / TIM4_CH1 [USART1_TX]
PB7 / I2C1_SDA / FSMC_NADV / TIM4_CH2 [USART1_RX]
PB8 / TIM4_CH3 / SDIO_D4 [I2C1_SCL / CANRX]
PB9 / TIM4_CH4 / SDIO_D5 [I2C1_SDA / CANTX ]
PB10 / I2C2_SCL / USART3_TX [TIM2_CH3]
PB11 / I2C2_SDA / USART3_RX [TIM2_CH4]
PB12 / SPI2_NSS / I2S2_WS / I2C2_SMBAI / USART3_CK / TIM1_BKIN
PB13 / SPI2_SCK / I2S2_CK / USART3_CTS / TIM1_CH1N
PB14 / SPI2_MISO / TIM1_CH2N / USART3_RTS
PB15 / SPI2_MOSI / I2S2_SD / TIM1_CH3N
PORT B
PC0 / ADC123_IN10
PC1 / ADC123_IN11
PC2 / ADC123_IN12
PC3 / ADC123_IN13
PC4 / ADC12_IN14
PC5 / ADC12_IN15
PC6 / I2S2_MCK / TIM8_CH1 / SDIO_D6 [TIM3_CH1]
PC7 / I2S3_MCK / TIM8_CH2 / SDIO_D7 [TIM3_CH2]
PC8 / TIM8_CH3 / SDIO_D0 [TIM3_CH3]
PC9 / TIM8_CH4 / SDIO_D1 [TIM3_CH4]
PC10 / UART4_TX / SDIO_D2 [USART3_TX]
PC11 / UART4_RX / SDIO_D3 [USART3_RX]
PC12 / UART5_TX / SDIO_CK [USART3_CK]
PC13 / TAMPER-RTC
PC14 / OSC32_IN
PC15 / OSC32_OUT
C
PORT C
R296 0R
(p 21) AEM_SENSE_VOLTAGE
(p 20,21) AEM_SENSE_CURRENT_RANGE1
TP157
Short to GND to
enter bootloader
mode during power up
R297 0R
3V3
R298 0R
8
7
6
5
(p 20,21) AEM_SENSE_CURRENT_RANGE2
(p 21) AEM_AUX_SENSE_VOLTAGE
RP1
2K2
R359 0R
B
3V3
3V3
3V3
3V3
3V3
LED75
LED76
2
2
2
2
1
2
3
4
B
LED77
LED78
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
2X10 2.54MM
NM
A
CTRLMCU_#TRST
CTRLMCU_TDI
CTRLMCU_TMS_SW DIO
CTRLMCU_TCK_SW CLK
CTRLMCU_RTCK
CTRLMCU_TDO_SW D
R88
100K
NM
R85
100K
NM
R86
100K
NM
YELLOW
YELLOW
YELLOW
CTRLMCU_JTAG_#TRST (p 10)
CTRLMCU_JTAG_TDI (p 10)
CTRLMCU_JTAG_TMS (p 10)
CTRLMCU_JTAG_TCK (p 10)
CTRLMCU_JTAG_TDO (p 10)
CTRLMCU_DEBUG_#RESET (p 12)
R89
100K
NM
R90
100K
NM
<Schematic Path>
TOP
Schematic Title
R87
100K
NM
GND
A
EFM32 Development Kit
GND
GNDGND
YELLOW
1
R84
100K
NM
1
R83
100K
NM
1
R82
100K
NM
1
3V3
P5
GND
Page Title
Designed:
Approved:
JNO
JNO
Size
BOM Doc No:
Control MCU
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
11 of
21
5
4
3
3V3
2
1
3V3 3V3
3V3
R92
1K
R93
1K
ST9
3V3
2
R288
4K7
R241
470R
LED124
BLUE
D
LED123
YELLOW
3V3
5
6
1
(p 7,9) CTRLMCU_DATA[15..0]
D8
E8
B7
C7
FSMC_CLK
D7
FSMC_#OE
B6
FSMC_#W E
FSMC_#W AIT C6
D6
FSMC_#E1
K9
FSMC_D13
J9
FSMC_D14
H9
FSMC_D15
G9
K10
J10
H10
FSMC_D0
G10
FSMC_D1
FSMC_D2
FSMC_D3
(p 7) CTRLMCU_FSMC_CLK
(p 9) CTRLMCU_FSMC_#OE
(p 9) CTRLMCU_FSMC_#W E
(p 9) CTRLMCU_FSMC_#W AIT
(p 9) CTRLMCU_FSMC_#E1
CTRLMCU_DATA13
CTRLMCU_DATA14
CTRLMCU_DATA15
CTRLMCU_ADDR16
CTRLMCU_ADDR17
CTRLMCU_ADDR18
CTRLMCU_DATA0
CTRLMCU_DATA1
(p 10) FPGA_CFG_#PROG
(p 10) FPGA_CFG_DONE
CTRLMCU_ADDR19
CTRLMCU_ADDR20
CTRLMCU_ADDR21
FPGA_CFG_#CS
FPGA_CFG_RD#W R
FPGA_CFG_#INIT
CTRLMCU_DATA4
CTRLMCU_DATA5
CTRLMCU_DATA6
CTRLMCU_DATA7
CTRLMCU_DATA8
CTRLMCU_DATA9
CTRLMCU_DATA10
CTRLMCU_DATA11
CTRLMCU_DATA12
(p 7,9) CTRLMCU_ADDR[21..16]
FSMC_D4
FSMC_D5
FSMC_D6
FSMC_D7
FSMC_D8
FSMC_D9
FSMC_D10
FSMC_D11
FSMC_D12
D4
C4
A3
B3
C3
D3
E3
H5
J5
K5
G6
H6
J6
K6
G7
H7
GND
SDA
SCL
1
2
3
U17B
CTRLMCU_DATA2
CTRLMCU_DATA3
D
U18A
Debug LED
1
J-Link LED
C
1
2
3
4
(p 11,17,18,20) CTRLMCU_I2C_SDA
(p 11,17,18,20) CTRLMCU_I2C_SCL
2
R91
470R
A0
A1
A2
R94
10K
WP
R344
0R
7
24AA024
PD0 / OSC_IN / FSMC_D2 [CANRX]
PD1 / OSC_OUT / FSMC_D3 [CANTX]
PD2 / TIM3_ETR / UART5_RX / SDIO_CMD
PD3 / FSMC_CLK [USART2_CTS]
PD4 / FSMC_NOE [USART2_RTS]
PD5 / FSMC_NWE [USART2_TX]
PD6 / FSMC_NWAIT [USART2_RX]
PD7 / FSMC_NE1 / FSMC_NCE2 [USART2_CK]
PD8 / FSMC_D13 [USART3_TX]
PD9 / FSMC_D14 [USART3_RX]
PD10 / FSMC_D15 [USART3_CK]
PD11 / FSMC_A16 [USART3_CTS]
PD12 / FSMC_A17 [USART3_RTS / TIM4_CH1]
PD13 / FSMC_A18 [TIM4_CH2]
PD14 / FSMC_D0 [TIM4_CH3]
PD15 / FSMC_D1 [TIM4_CH4]
EEPROM_W P (p 11,15,17,18)
GND
(p 11)
(p 11)
(p 11)
(p 11)
CTRLMCU_SPI_MISO
CTRLMCU_SPI_MOSI
CTRLMCU_SPI_#CS
CTRLMCU_SPI_SCK
3V3 3V3
PE0 / TIM4_ETR / FSMC_NBL0
PE1 / FSMC_NBL1
PE2 / TRACECK / FSMC_A23
PE3 / TRACED0 / FSMC_A19
PE4 / TRACED1 / FSMC_A20
PE5 / TRACED2 / FSMC_A21
PE6 / TRACED3 / FSMC_A22
PE7 / FSMC_D4 [TIM1_ETR]
PE8 / FSMC_D5 [TIM1_CH1N]
PE9 / FSMC_D6 [TIM1_CH1]
PE10 / FSMC_D7 [TIM1_CH2N]
PE11 / FSMC_D8 [TIM1_CH2]
PE12 / FSMC_D9 [TIM1_CH3N]
PE13 / FSMC_D10 [TIM1_CH3]
PE14 / FSMC_D11 [TIM1_CH4]
PE15 / FSMC_D12 [TIM1_BKIN]
U19A
5
1
6
D
Q
2
R95
100K
S
C
HOLD
W
C
R96
100K
7
3
M25PX16
R341
0R
NM
GND
Control MCU
B Control MCU Power & Bypass
B
U17C
C1
D1
(p 10) CTRLMCU_CLK
ADC_VREF
(p 11) CTRLMCU_DEBUG_#RESET
OSC_IN
OSC_OUT
VBAT
B2
C91
100N
3V3
TP50
L10
3V3
R266
0R
R203
470R
A
2
4
R290 0R
C95
10U
C97
10N
J1
H1
NM
F8
C263
VDDA
VSSA
VREF+
VREF-
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
GND
E1
BOOT0
NRST
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
E7
E6
E5
E4
C2
4
3V3
C100 C101 C102 C103
100N
GND
GND
GND
8
VCC
C90
10N
VSS
M25PX16
C99
C105
100N
10U
100N 100N 100N 100N
4
8
C92
10N
VSS
24AA024
GND
<Schematic Path>
TOP
GND
Schematic Title
GND
A
EFM32 Development Kit - Mainboard
C98
R331
0R
3V3
U18B
VCC
F7
F6
F5
F4
D2
NC
100N
D5
1
3
3V3
U19B
GND
K1
G1
GND
LED89
RED
R99
10K
1
R289
0R
C96
10N
2
3V3
R98
1R
2
BLM21B102S
(p 10) TEST_#RESET
SW 8
1
Control MCU
Page Title
Designed:
Approved:
JNO
JNO
Size
BOM Doc No:
Control MCU - Board Control interface
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
12 of
21
5
3V3
4
3
DEBUG_EXT_CABLE_ATTACH (p 11)
R101
10K
VMCU
VMCU
VMCU
2
1
VMCU
VTARGET
R204
100K
NM
P6
2
4
6
8
10
12
14
16
18
20
D
1
3
5
7
9
11
13
15
17
19
R205
100K
NM
R206
100K
NM
R208
47K
NM
R371 130R
2
3
9
10
DH_VTARGET
DH_#TRST
DH_TDI
DH_TMS_SW DIO
DH_TCK_SW CLK
DH_RTCK
DH_TDO_SW O
DH_#RESET
1
2X10 2.54MM
2
3
4
5
6
7
1Z
2Z
3Z
4Z
U53A
1
4
8
11
1Y
2Y
3Y
4Y
8
RP3
VESD05A8A-HNH
D8
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
100R
RP22
1
2
3
4
R102
47K
8
7
6
5
SW _TDO_SW O
33R
74LVC4066
9
GNDGND
U20A
8
7
6
5
VTARGET
R106
100K
R105
100K
1
2
3
4
SW _#TRST
SW _TDI
SW _TMS_SW DIO
SW _TCK_SW CLK
13
5
6
12
1E
2E
3E
4E
GND
R104
100K
74LVC4066
2
3
9
10
GND
GND
1Z
2Z
3Z
4Z
1
4
8
11
1Y
2Y
3Y
4Y
100R
5V
U54A
R303
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
R304
1OE
2OE
1DIR
2DIR
33R
R307
4K7
GND
U61A
13
5
6
12
6
DEBUG_HEADER_EN
2
DEBUG_#TRST_OUT (p 11)
DEBUG_TDI_OUT (p 11)
D
DEBUG_TCK_SW CLK_OUT (p 11)
GND
DEBUG_#TRST_IN (p 11)
DEBUG_TDI_IN (p 11)
DEBUG_TMS_SW DIO_IN (p 11)
DEBUG_TCK_SW CLK_IN (p 11)
DEBUG_TDO_SW O_IN (p 11)
DEBUG_#RESET_IN (p 11)
48
25
1
24
3V3
DEBUG_BUF_#OE (p 11)
74LVC16T245
GND
74LVC2G125DC
GND
7
5V
1
1E
2E
3E
4E
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
3
R306
4K7
3
MCU_SW _EN
74LVC4066
(p 17) MCUDBG_#TRST
(p 17) MCUDBG_TDI
(p 17) MCUDBG_TMS_SW DIO
(p 17) MCUDBG_TCK_SW CLK
(p 17) MCUDBG_TDO_SW O
(p 17) MCUDBG_#RESET
DEBUG_TMS_SW DIO_#OE (p 11)
DEBUG_TMS_SW DIO_OUT (p 11)
5
U61B
C
VTARGET
2
3
9
10
1Z
2Z
3Z
4Z
5
U21B
74LVC2G125DC
U58A
1
4
8
11
1Y
2Y
3Y
4Y
74LVC2G125DC
DEBUG_DH_SW _ENABLE
GND
7
C
VMCU
(p 11)
DEBUG_MCU_SW _ENABLE
(p 11)
VTARGET
R103
100K
U21A
R107
DEBUG_#RESET (p 11)
1
13
5
6
12
1E
2E
3E
4E
6
SW _#RESET
100R
2
74LVC2G125DC
GND
Power & Decoupling
B
Ext. Debug Voltage Measurement
VTARGET
VTARGET
B
3V3
5V
R209
0R
L16
5V
U20B
7
18
31
42
C111
100N
C112
100N
VCCB
VCCB
VCCA
VCCA
L25
2
VTARGET
L26
1
2
BLM21B102S
BLM21B102S
1
1
2
R100 100K
DEBUG_EXT_VDD_TARGET (p 11)
BLM21B102S
GND
GND
GND
GND
GND
GND
GND
GND
4
10
15
21
28
34
39
45
U21C
U53B
VCC
8
14
C247
U54B
14
VCC
C248
U58B
14
VCC
C264
U61C
8
VCC
C106
R197
100K
VCC
10N
C110
4
GND
100N
GND
100N
74LVC2G125DC
7
100N
74LVC4066
GND
7
100N
74LVC4066
GND
7
C280
74LVC4066
100N
GND
4
GND
74LVC2G125DC
74LVC16T245
GND
GND
GND
GND
<Schematic Path>
TOP
Schematic Title
A
Mode
DEBUG_MCU_SW_ENABLE
DEBUG_DH_SW_ENABLE
DEBUG_BUF_#OE
DH_VTARGET
VTARGET
Debug Out
0
1
0
External voltage
External voltage
MCU Debug
1
0
0
Disconnected
VMCU
Debug In
1
1
1
VMCU
VMCU
A
EFM32 Development Kit - Mainboard
Page Title
Designed:
Approved:
JNO
JNO
Size
BOM Doc No:
Debug Interface
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
13 of
21
5
(p 8) BC_BUS_FPGA_DIR[3..0]
4
3
2
1
3V3
(p 8) BC_BUS_FPGA_#OE[3..0]
R239
1K8
(p 8) BC_BUS_FPGA[27..0]
2
4
9
10
GND
13
5
6
12
13
5
6
12
C
BC_BUS_AD0
BC_BUS_AD1
BC_BUS_AD2
BC_BUS_AD3
LED86
YELLOW
TS3A4751
COM1
COM2
COM3
COM4
NO1
NO2
NO3
NO4
RP16
1
3
8
11
1
2
3
4
8
7
6
5
BC_BUS_AD4
BC_BUS_AD5
BC_BUS_AD6
BC_BUS_AD7
33R
IN1
IN2
IN3
IN4
COM1
COM2
COM3
COM4
NO1
NO2
NO3
NO4
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
1
3
8
11
1
2
3
4
8
7
6
5
1OE
2OE
1DIR
2DIR
BC_BUS_AD8
BC_BUS_AD9
BC_BUS_AD10
BC_BUS_AD11
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
BC_BUS_FPGA0
BC_BUS_FPGA1
BC_BUS_FPGA2
BC_BUS_FPGA3
BC_BUS_FPGA4
BC_BUS_FPGA5
BC_BUS_FPGA6
BC_BUS_FPGA7
BC_BUS_FPGA8
BC_BUS_FPGA9
BC_BUS_FPGA10
BC_BUS_FPGA11
BC_BUS_FPGA12
BC_BUS_FPGA13
BC_BUS_FPGA14
BC_BUS_FPGA15
48
25
1
24
BC_BUS_FPGA_#OE0
BC_BUS_FPGA_#OE1
BC_BUS_FPGA_DIR0
BC_BUS_FPGA_DIR1
R310
1K8
1
BC_BUS_CONNECT_EBI
R240
10K
Q8
BC846AW
D
2
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
RP17
TS3A4751
3V3
U9A
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
33R
U11A
2
4
9
10
BC_BUS8
BC_BUS9
BC_BUS10
BC_BUS11
8
7
6
5
IN1
IN2
IN3
IN4
U10A
BC_BUS4
BC_BUS5
BC_BUS6
BC_BUS7
1
2
3
4
LED87
YELLOW
3 1
R265
100K
1
3
8
11
GND
1
BC_BUS_CONNECT_SPI
R311
10K
Q7
BC846AW
2
13
5
6
12
NO1
NO2
NO3
NO4
3 1
BC_BUS_CONNECT_EBI
(p 17) BC_BUS_CONNECT_EBI
COM1
COM2
COM3
COM4
2
D
RP15
TS3A4751
U8A
2
4
9
10
BC_BUS0
BC_BUS1
BC_BUS2
BC_BUS3
2
(p 17,18) BC_BUS[27..0]
GND
74LVC16T245
33R
IN1
IN2
IN3
IN4
VMCU
3V3
C
U13B
TS3A4751
U12A
2
4
9
10
BC_BUS12
BC_BUS13
BC_BUS14
BC_BUS15
13
5
6
12
COM1
COM2
COM3
COM4
2
4
9
10
13
5
6
12
B
13
5
6
12
1
2
3
4
8
7
6
5
IN1
IN2
IN3
IN4
TS3A4751
COM1
COM2
COM3
COM4
BC_BUS_AD12
BC_BUS_AD13
BC_BUS_AD14
BC_BUS_AD15
4
10
15
21
28
34
39
45
NO1
NO2
NO3
NO4
RP19
1
3
8
11
1
2
3
4
U13A
8
7
6
5
BC_BUS_ARDY
BC_BUS_ALE
BC_BUS_#W EN
BC_BUS_#REN
8
7
6
5
BC_BUS_#CS0
BC_BUS_#CS1
BC_BUS_#CS2
BC_BUS_#CS3
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
33R
IN1
IN2
IN3
IN4
TS3A4751
U15A
2
4
9
10
BC_BUS20
BC_BUS21
BC_BUS22
BC_BUS23
RP18
1
3
8
11
33R
U14A
BC_BUS16
BC_BUS17
BC_BUS18
BC_BUS19
NO1
NO2
NO3
NO4
COM1
COM2
COM3
COM4
NO1
NO2
NO3
NO4
RP20
1
3
8
11
1
2
3
4
GND
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
33R
IN1
IN2
IN3
IN4
1OE
2OE
1DIR
2DIR
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
BC_BUS_FPGA27
BC_BUS_FPGA17
BC_BUS_FPGA18
BC_BUS_FPGA19
BC_BUS_FPGA20
BC_BUS_FPGA21
BC_BUS_FPGA22
BC_BUS_FPGA23
BC_BUS_FPGA24
BC_BUS_FPGA25
BC_BUS_FPGA26
BC_BUS_FPGA16
2
4
9
10
BC_BUS24
BC_BUS25
BC_BUS26
BC_BUS27
13
5
6
12
BC_BUS_CONNECT_SPI
17) BC_BUS_CONNECT_SPI
R312
100K
COM1
COM2
COM3
COM4
NO1
NO2
NO3
NO4
1
2
3
4
8
7
6
5
C73
C74
C75
C76
100N
100N
100N
100N
GND
GND
VMCU
GND
3V3
B
U9B
48
25
1
24
BC_BUS_FPGA_#OE2
BC_BUS_FPGA_#OE3
BC_BUS_FPGA_DIR2
BC_BUS_FPGA_DIR3
4
10
15
21
28
34
39
45
BC_BUS_SPI_SCK
BC_BUS_SPI_#CS
BC_BUS_SPI_MOSI
BC_BUS_SPI_MISO
33R
IN1
IN2
IN3
IN4
GND
GND
GND
GND
GND
GND
GND
GND
GND
RP21
1
3
8
11
7
18
31
42
74LVC16T245
74LVC16T245
TS3A4751
U16A
VCCB
VCCB
VCCA
VCCA
VCCB
VCCB
VCCA
VCCA
7
18
31
42
GND
GND
GND
GND
GND
GND
GND
GND
C77
C78
C79
C80
100N
100N
100N
100N
74LVC16T245
GND
GND
GND
<Schematic Path>
TOP
GND
Schematic Title
A
3V6
3V6
3V6
U12B
14
14
V+
C81
100N
3V6
U14B
14
V+
C82
GND
7
100N
TS3A4751
3V6
U11B
14
V+
C83
GND
7
100N
TS3A4751
3V6
U8B
14
V+
C84
GND
7
100N
TS3A4751
U10B
14
V+
C85
GND
7
100N
TS3A4751
U15B
14
V+
C86
GND
7
100N
TS3A4751
Page Title
V+
C87
GND
7
100N
TS3A4751
GND
TS3A4751
7
Designed:
Approved:
JNO
JNO
Size
GND
GND
GND
GND
GND
GND
BOM Doc No:
Board Control - EFM32 bus level shift & switch
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
GND
A
EFM32 Development Kit - Mainboard
3V6
U16B
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
14 of
21
5
(p 11,12,17,18,20)
4
3
EXP32_A[83..0] (p 11,12,17,18,20)
EFM32_A[83..0]
EXP32_A81
EXP32_A82
EXP32_A83
EFM32_A40
(p 7,9,11,12,13,14,16,17,18,20)
2
EXP32_B[83..0] (p 2,3,9,11,12,14,16
EEPROM_W P (p 11,12,17,18)
CTRLMCU_I2C_SDA (p 11,12,17,18,20)
CTRLMCU_I2C_SCL (p 11,12,17,18,20)
A: Pins 0 -> 83
13
5
6
12
(p 9) SPI_BUS_CONNECT
D
R174
100K
EXP32_B[83..0] (p 2,3,9,11,12,14,16,17,18,20)
BC_BUS0
BC_BUS1
BC_BUS2
BC_BUS3
EXP32_B16
EXP32_B17
EXP32_B18
EXP32_B19
BC_BUS4
BC_BUS5
BC_BUS6
BC_BUS7
EXP32_B20
EXP32_B21
EXP32_B22
EXP32_B23
BC_BUS8
BC_BUS9
BC_BUS10
BC_BUS11
EXP32_B24
EXP32_B25
EXP32_B26
EXP32_B27
BC_BUS12
BC_BUS13
BC_BUS14
BC_BUS15
EXP32_B28
EXP32_B29
EXP32_B30
EXP32_B31
BC_BUS16
BC_BUS17
BC_BUS18
BC_BUS19
EXP32_B32
EXP32_B33
EXP32_B34
EXP32_B35
BC_BUS20
BC_BUS21
BC_BUS22
BC_BUS23
EXP32_B36
EXP32_B37
EXP32_B38
EXP32_B39
BC_BUS24
BC_BUS25
BC_BUS26
BC_BUS27
EXP32_B40
EXP32_B41
EXP32_B42
EXP32_B43
13
5
6
12
(p 9) SENSOR_POTMETER_CONNECT
(p 9) SENSOR_AMBIENT_LIGHT_CONNECT
R345
100K
BC_BUS0
BC_BUS1
BC_BUS2
BC_BUS3
EFM32_B16
EFM32_B17
EFM32_B18
EFM32_B19
BC_BUS4
BC_BUS5
BC_BUS6
BC_BUS7
EFM32_B20
EFM32_B21
EFM32_B22
EFM32_B23
BC_BUS8
BC_BUS9
BC_BUS10
BC_BUS11
EFM32_B24
EFM32_B25
EFM32_B26
EFM32_B27
BC_BUS12
BC_BUS13
BC_BUS14
BC_BUS15
EFM32_B28
EFM32_B29
EFM32_B30
EFM32_B31
BC_BUS16
BC_BUS17
BC_BUS18
BC_BUS19
EFM32_B32
EFM32_B33
EFM32_B34
EFM32_B35
BC_BUS20
BC_BUS21
BC_BUS22
BC_BUS23
EFM32_B36
EFM32_B37
EFM32_B38
EFM32_B39
BC_BUS25
BC_BUS24
BC_BUS26
BC_BUS27
EFM32_B40
EFM32_B41
EFM32_B42
EFM32_B43
NO1
NO2
NO3
NO4
GND
R346
100K
1
3
8
11
EXP32_B64
EXP32_B65
EXP32_B66
EXP32_B67
EXP32_B64
EXP32_B65
EXP32_B66
EXP32_B67
SPI_BUS_SCLK (p 3,18)
SPI_BUS_#CS (p 9,18)
SPI_BUS_MOSI (p 3,18)
SPI_BUS_MISO (p 3,18)
IN1
IN2
IN3
IN4
D
TS3A4751
COM1
COM2
COM3
COM4
NO1
NO2
NO3
NO4
1
3
8
11
EXP32_B68
EXP32_B69
EXP32_B70
EXP32_B71
EXP32_B68
EXP32_B69
EXP32_B70
EXP32_B71
I2C_BUS_SDA (p 3,18)
I2C_BUS_SCL (p 3,18)
SENSOR_POTMETER (p 3,18)
SENSOR_AMBIENT_LIGHT (p 3,18)
IN1
IN2
IN3
IN4
R166
100K
GND
GND
EFM32_B76
EFM32_B77
EFM32_B78
EFM32_B79
(p 13,17) MCUDBG_TDI
(p 13,17) MCUDBG_TCK_SW CLK
(p 13,17) MCUDBG_TMS_SW DIO
(p 13,17) MCUDBG_TDO_SW O
TP156
EFM32_B80
EFM32_B81
(p 9,17) FPGA_MCU_#RESET
(p 7,17) FPGA_#INT
EFM32_B82
EFM32_B83
C
EXP32_B81
EXP32_B82
EXP32_B83
CTRLMCU_I2C_SDA (p 11,12,17,18,20)
CTRLMCU_I2C_SCL (p 11,12,17,18,20)
EEPROM_W P (p 11,12,17,18)
CTRLMCU_I2C_SDA (p 11,12,17,18
CTRLMCU_I2C_SCL (p 11,12,17,18
B: Pins 64 -> 83
(p 7,9,11,12,13,14,16,17,18,20)
B
EFM32_B72
EFM32_B73
EFM32_B74
EFM32_B75
(p 14,17) BC_BUS_CONNECT_EBI
(p 14,17) BC_BUS_CONNECT_SPI
(p 13,17) MCUDBG_#TRST
(p 13,17) MCUDBG_#RESET
EXP32_B[83..0] (p 2,3,9,11,12,14,16,17,18,20)
EFM32_B[83..0]
EFM32_B[83..0] (p 7,9,11,12,13,14,16,17,18,20)
(p 14,17,18) BC_BUS[27..0]
COM1
COM2
COM3
COM4
U40A
2
4
9
10
EFM32_B68
EFM32_B69
EFM32_B70
EFM32_B71
GND
(p 9) IF_I2C_BUS_CONNECT
C
TS3A4751
U44A
2
4
9
10
EFM32_B64
EFM32_B65
EFM32_B66
EFM32_B67
MCU_OSC_TEST (p 11,17,18)
(p 14,17,18) BC_BUS[27..0]
1
EFM32_B[83..0]
EFM32_B0
EFM32_B1
EFM32_B2
EFM32_B3
EXP32_B0
EXP32_B1
EXP32_B2
EXP32_B3
EFM32_B4
EFM32_B5
EFM32_B6
EFM32_B7
EXP32_B4
EXP32_B5
EXP32_B6
EXP32_B7
EFM32_B8
EFM32_B9
EFM32_B10
EFM32_B11
EXP32_B8
EXP32_B9
EXP32_B10
EXP32_B11
EFM32_B12
EFM32_B13
EFM32_B14
EFM32_B15
EXP32_B12
EXP32_B13
EXP32_B14
EXP32_B15
B
B: Pins 0 -> 15
3V6
U44B
14
C166
100N
3V6
U40B
V+
14
GND
7
V+
C165
100N
GND
TS3A4751
B: Pins 16 -> 43
(p 9)
(p 9)
(p 9)
(p 9)
7
TS3A4751
SPI_BUS_CONNECT
IF_I2C_BUS_CONNECT
SENSOR_POTMETER_CONNECT
SENSOR_AMBIENT_LIGHT_CONNECT
GND
R244
2K
R245
2K
R250
2K
R249
2K
GND
<Schematic Path>
TOP
GND
Ambient Light
GND
GND
Potmeter
I2C Bus
2
LED93
YELLOW
GND
SPI Bus
A
EFM32 Development Kit
Page Title
1
LED92
YELLOW
1
LED91
YELLOW
1
Switch Indicators
1
LED90
YELLOW
2
2
2
Schematic Title
A
Designed:
Approved:
JNO
JNO
Size
BOM Doc No:
EXP32 signal assignments #1
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
15 of
21
5
4
3
2
1
EXP32_B[83..0] (p 2,3,9,11,12,14,15,17,18,20)
(p 7,9,11,12,13,14,15,17,18,20)
EFM32_B[83..0]
TS3A4751
U4A
2
4
9
10
EFM32_B44
EFM32_B45
EFM32_B46
EFM32_B47
D
COM1
COM2
COM3
COM4
13
5
6
12
(p 9) ANALOG_SE_CONNECT
(p 9) ANALOG_DIFF_CONNECT
R45
100K
R46
100K
NO1
NO2
NO3
NO4
1
3
8
11
EXP32_B44
EXP32_B45
EXP32_B46
EXP32_B47
D
TS3A4751
U5A
2
4
9
10
EFM32_B48
EFM32_B49
EFM32_B50
EFM32_B51
GND GND
13
5
6
12
R48
100K
COM1
COM2
COM3
COM4
GND GND
13
5
6
12
(p 9) IF_RS232_A_CONNECT
COM1
COM2
COM3
COM4
NO1
NO2
NO3
NO4
NO1
NO2
NO3
NO4
1
3
8
11
2
4
9
10
13
5
6
12
GND
(p 3,9) SENSOR_ACCEL_CONNECT
R152
100K
GND
COM1
COM2
COM3
COM4
13
5
6
12
(p 9) IF_IRDA_CONNECT
(p 9) IF_RS232_B_CONNECT
R167
100K
EXP32_B52
EXP32_B53
EXP32_B54
EXP32_B55
EXP32_B52
EXP32_B53
EXP32_B54
EXP32_B55
EXP32_B56
EXP32_B57
EXP32_B58
EXP32_B59
EXP32_B56
EXP32_B57
EXP32_B58
EXP32_B59
EXP32_B60
EXP32_B61
EXP32_B62
EXP32_B63
EXP32_B60
EXP32_B61
EXP32_B62
EXP32_B63
AUDIO_OUT_RIGHT (p 2,18)
AUDIO_OUT_LEFT (p 2,18)
AUDIO_IN_RIGHT (p 2,18)
AUDIO_IN_LEFT (p 2,18)
IF_RS232_A_RX (p 3,18)
IF_RS232_A_#CTS (p 3,18)
IF_RS232_A_#RTS (p 3,18)
IF_RS232_A_TX (p 3,18)
TS3A4751
COM1
COM2
COM3
COM4
NO1
NO2
NO3
NO4
1
3
8
11
SENSOR_ACCEL_XOUT (p 3,18)
SENSOR_ACCEL_YOUT (p 3,18)
SENSOR_ACCEL_ZOUT (p 3,18)
ANALOG_DIFF_VCM (p 2,18)
C
IN1
IN2
IN3
IN4
TS3A4751
U37A
2
4
9
10
EFM32_B60
EFM32_B61
EFM32_B62
EFM32_B63
EXP32_B48
EXP32_B49
EXP32_B50
EXP32_B51
IN1
IN2
IN3
IN4
EFM32_B56
EFM32_B57
EFM32_B58
EFM32_B59
C
EXP32_B48
EXP32_B49
EXP32_B50
EXP32_B51
IN1
IN2
IN3
IN4
U39A
R253
100K
1
3
8
11
TS3A4751
U35A
2
4
9
10
EFM32_B52
EFM32_B53
EFM32_B54
EFM32_B55
ANALOG_SE_A (p 2,18)
ANALOG_SE_B (p 2,18)
ANALOG_DIFF_N (p 2,18)
ANALOG_DIFF_P (p 2,18)
IN1
IN2
IN3
IN4
(p 2,9) AUDIO_OUT_CONNECT
(p 2,9) AUDIO_IN_CONNECT
R47
100K
EXP32_B44
EXP32_B45
EXP32_B46
EXP32_B47
NO1
NO2
NO3
NO4
1
3
8
11
IF_IRDA_TXD (p 3,18)
IF_IRDA_RXD (p 3,18)
IF_RS232_B_TX (p 3,11,18)
IF_RS232_B_RX (p 3,11,18)
IN1
IN2
IN3
IN4
R151
100K
B: Pins 44 -> 63
GND GND
(p 9) IF_RS232_B_CONNECT
(p 9) IF_IRDA_CONNECT
(p 3,9) SENSOR_ACCEL_CONNECT
(p 9) IF_RS232_A_CONNECT
(p 2,9) AUDIO_IN_CONNECT
(p 2,9) AUDIO_OUT_CONNECT
(p 9) ANALOG_DIFF_CONNECT
(p 9) ANALOG_SE_CONNECT
B
GND
GND
GND
Differential
Audio Out
Audio In
2
2
LED100
YELLOW
LED101
YELLOW
1
LED99
YELLOW
GND
GND
GND
Accelerometer
IrDA
RS232 B
GND
RS232 A
R248
2K
1
GND
Single Ended
R251
2K
1
LED98
YELLOW
1
LED97
YELLOW
2
R246
2K
2
R247
2K
2
2
R236
2K
LED96
YELLOW
1
LED95
YELLOW
1
1
LED94
YELLOW
Switch Indicators
R235
2K
2
R234
2K
2
R233
2K
1
B
<Schematic Path>
TOP
Power & Bypass
Schematic Title
A
3V6
3V6
U39B
14
C154
100N
0R
U35B
14
V+
GND
7
C155
100N
TS3A4751
2
U37B
14
V+
GND
7
C160
100N
TS3A4751
V+
R238
1
14
L19 BLM21B102S
GND
U5B
3V6
0R
V+
2
R237
1
U4B
14
C39
7
100N
GND
7
L18 BLM21B102S
Page Title
V+
C38
100N
TS3A4751
TS3A4751
GND
TS3A4751
7
Designed:
Approved:
JNO
JNO
Size
GND
GND
GND
GND
BOM Doc No:
EXP32 signal assignments #2
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
GND
A
EFM32 Development Kit - Mainboard
3V6
3V6
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
16 of
21
5
4
(p 7,9,11,12,13,14,15,16,18,20)
(p 11,12,15,18,20)
3
2
1
EFM32_B[83..0]
EFM32_A[83..0]
P13
3V3 VMCU_M_CPU2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
EFM32_A0
EFM32_A1
EFM32_A2
EFM32_A3
D
EFM32_A4
EFM32_A5
EFM32_A6
EFM32_A7
EFM32_A8
EFM32_A9
EFM32_A10
EFM32_A11
EFM32_A12
EFM32_A13
EFM32_A14
EFM32_A15
EFM32_A16
EFM32_A17
EFM32_A18
EFM32_A19
EFM32_A20
EFM32_A21
EFM32_A22
EFM32_A23
EFM32_A24
EFM32_A25
EFM32_A26
EFM32_A27
C
EFM32_A28
EFM32_A29
EFM32_A30
EFM32_A31
EFM32_A32
EFM32_A33
EFM32_A34
EFM32_A35
EFM32_A36
EFM32_A37
EFM32_A38
EFM32_A39
EFM32_A80
EFM32_A81
VMCU_M_CPU2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
3V3
3V3
EFM32_A40
EFM32_A41
EFM32_A42
EFM32_A43
EFM32_B0
EFM32_B1
EFM32_B2
EFM32_B3
EFM32_A44
EFM32_A45
EFM32_A46
EFM32_A47
EFM32_B4
EFM32_B5
EFM32_B6
EFM32_B7
EFM32_A48
EFM32_A49
EFM32_A50
EFM32_A51
EFM32_B8
EFM32_B9
EFM32_B10
EFM32_B11
EFM32_A52
EFM32_A53
EFM32_A54
EFM32_A55
EFM32_B12
EFM32_B13
EFM32_B14
EFM32_B15
EFM32_A56
EFM32_A57
EFM32_A58
EFM32_A59
EFM32_B16
EFM32_B17
EFM32_B18
EFM32_B19
EFM32_A60
EFM32_A61
EFM32_A62
EFM32_A63
EFM32_B20
EFM32_B21
EFM32_B22
EFM32_B23
EFM32_A64
EFM32_A65
EFM32_A66
EFM32_A67
EFM32_B24
EFM32_B25
EFM32_B26
EFM32_B27
EFM32_A68
EFM32_A69
EFM32_A70
EFM32_A71
EFM32_B28
EFM32_B29
EFM32_B30
EFM32_B31
EFM32_A72
EFM32_A73
EFM32_A74
EFM32_A75
EFM32_B32
EFM32_B33
EFM32_B34
EFM32_B35
EFM32_A76
EFM32_A77
EFM32_A78
EFM32_A79
EFM32_B36
EFM32_B37
EFM32_B38
EFM32_B39
EFM32_A82
EFM32_A83
EFM32_B80
EFM32_B81
VMCU_M
P14
VMCU_M
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
3V3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
EFM32_B40
EFM32_B41
EFM32_B42
EFM32_B43
D
EFM32_B44
EFM32_B45
EFM32_B46
EFM32_B47
EFM32_B48
EFM32_B49
EFM32_B50
EFM32_B51
EFM32_B52
EFM32_B53
EFM32_B54
EFM32_B55
EFM32_B56
EFM32_B57
EFM32_B58
EFM32_B59
EFM32_B60
EFM32_B61
EFM32_B62
EFM32_B63
EFM32_B64
EFM32_B65
EFM32_B66
EFM32_B67
C
EFM32_B68
EFM32_B69
EFM32_B70
EFM32_B71
EFM32_B72
EFM32_B73
EFM32_B74
EFM32_B75
EFM32_B76
EFM32_B77
EFM32_B78
EFM32_B79
EFM32_B82
EFM32_B83
5V
5V
GND
BTE_060_01_L_D_A
GND
BTE_060_01_L_D_A
GND
GND
B
B
VMCU_M
VMCU_M_CPU2
VMCU_M
3V3
5V
R364
C211
C212
C213
C214
C215
C216
C217
C218
C219
C221
C222
C223
C224
C225
0R
100N
100N
100N
10U
NM
100N
100N
100N
10U
10U
100N
100N
100N
10U
10U
GND
GND
GND
<Schematic Path>
TOP
Schematic Title
A
VMCU_M_CPU2
3V3
5V
C227
C228
C229
C230
C231
C232
C233
C234
C235
C237
C238
C239
C240
C241
100N
100N
100N
10U
NM
100N
100N
100N
10U
10U
100N
100N
100N
10U
10U
Page Title
Designed:
Approved:
JNO
JNO
Size
GND
GND
GND
A
EFM32 Development Kit - Mainboard
BOM Doc No:
EFM32 Board Connectors
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
17 of
21
5
)
EXP32_B[83..0]
0)
EXP32_A[83..0]
4
P11
3V3 VMCU_M_EXP2
D
EXP32_A0
EXP32_A1
EXP32_A2
EXP32_A3
EXP32_A4
EXP32_A5
EXP32_A6
EXP32_A7
EXP32_A8
EXP32_A9
EXP32_A10
EXP32_A11
EXP32_A12
EXP32_A13
EXP32_A14
EXP32_A15
EXP32_A16
EXP32_A17
EXP32_A18
EXP32_A19
EXP32_A20
EXP32_A21
EXP32_A22
EXP32_A23
C
VMCU_M_EXP2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
EXP32_A24
EXP32_A25
EXP32_A26
EXP32_A27
EXP32_A28
EXP32_A29
EXP32_A30
EXP32_A31
EXP32_A32
EXP32_A33
EXP32_A34
EXP32_A35
EXP32_A36
EXP32_A37
EXP32_A38
EXP32_A39
EXP32_A80
EXP32_A81
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
3
2
1
3V3
3V3
EXP32_A40
EXP32_A41
EXP32_A42
EXP32_A43
EXP32_B0
EXP32_B1
EXP32_B2
EXP32_B3
EXP32_A44
EXP32_A45
EXP32_A46
EXP32_A47
EXP32_B4
EXP32_B5
EXP32_B6
EXP32_B7
EXP32_A48
EXP32_A49
EXP32_A50
EXP32_A51
EXP32_B8
EXP32_B9
EXP32_B10
EXP32_B11
EXP32_A52
EXP32_A53
EXP32_A54
EXP32_A55
EXP32_B12
EXP32_B13
EXP32_B14
EXP32_B15
EXP32_A56
EXP32_A57
EXP32_A58
EXP32_A59
EXP32_B16
EXP32_B17
EXP32_B18
EXP32_B19
EXP32_A60
EXP32_A61
EXP32_A62
EXP32_A63
EXP32_B20
EXP32_B21
EXP32_B22
EXP32_B23
EXP32_A64
EXP32_A65
EXP32_A66
EXP32_A67
EXP32_B24
EXP32_B25
EXP32_B26
EXP32_B27
EXP32_A68
EXP32_A69
EXP32_A70
EXP32_A71
EXP32_B28
EXP32_B29
EXP32_B30
EXP32_B31
EXP32_A72
EXP32_A73
EXP32_A74
EXP32_A75
EXP32_B32
EXP32_B33
EXP32_B34
EXP32_B35
EXP32_A76
EXP32_A77
EXP32_A78
EXP32_A79
EXP32_B36
EXP32_B37
EXP32_B38
EXP32_B39
EXP32_A82
EXP32_A83
EXP32_B80
EXP32_B81
VMCU_M
P12
VMCU_M
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
5V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
3V3
D
EXP32_B40
EXP32_B41
EXP32_B42
EXP32_B43
EXP32_B44
EXP32_B45
EXP32_B46
EXP32_B47
EXP32_B48
EXP32_B49
EXP32_B50
EXP32_B51
EXP32_B52
EXP32_B53
EXP32_B54
EXP32_B55
EXP32_B56
EXP32_B57
EXP32_B58
EXP32_B59
EXP32_B60
EXP32_B61
EXP32_B62
EXP32_B63
C
EXP32_B64
EXP32_B65
EXP32_B66
EXP32_B67
EXP32_B68
EXP32_B69
EXP32_B70
EXP32_B71
EXP32_B72
EXP32_B73
EXP32_B74
EXP32_B75
EXP32_B76
EXP32_B77
EXP32_B78
EXP32_B79
EXP32_B82
EXP32_B83
5V
B
GND
BTE_060_01_L_D_A
GND
GND
VMCU_M
VMCU_M
BTE_060_01_L_D_A
3V3
B
GND
5V
C179
C180
C181
C182
C183
C184
C185
C187
C188
C189
C190
C191
C192
C193
100N
100N
100N
10U
NM
100N
100N
100N
10U
10U
100N
100N
100N
10U
10U
VMCU_M_EXP2
R365
GND
GND
GND
0R
<Schematic Path>
TOP
Schematic Title
A
VMCU_M_EXP2
3V3
5V
C195
C196
C197
C198
C199
C200
C201
C202
C203
C205
C206
C207
C208
C209
100N
100N
100N
10U
NM
100N
100N
100N
10U
10U
100N
100N
100N
10U
10U
Page Title
Designed:
Approved:
JNO
JNO
Size
GND
GND
GND
A
EFM32 Development Kit - Mainboard
BOM Doc No:
EXP32 Board Connectors
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
18 of
21
5
4
3
2
1
J3
L4
5V
D2
1
1
3
2
2
TP116
1
SW 9
4
1
D7
3
BLM41P600S
2 1
L12
2UH2
C244 L17
2UH2
TP117
ZEN056V130
3
3
12CW Q03FN
R216
1K
P8
TYCO_292304_1
GND
GND
2
1
2
GND
1
2
3
SW
L6
C138
C139
10U
100N
R372
0R
EN
GND
FB
2
30P
NM
C136
C137
10U
100N
R373
0R
NM
1
BLM41P600S
R232
10K
GND
USBDM
(p 11)
USBDP
(p 11)
GND
GND
GND
GND
GND
Q3
BC846AW
GND
GND
R133 0R
TP164 TP165
C
LED122
GREEN
4
LM3674MF-1.2
1
2UH2
5
C297
3
GND
4
L7
VIN
R231
1K
BLM41P600S
1
5
2
3
U73
1
D
FPGA_1V2
L15
1
1
4
TP121
5V
LED119
GREEN
GND
LED120
GREEN
6
5V
2
2
10U
2
C245
10U
3 1
6A SPDT
R217
1K1
2
D
2
RAPC722X
GND
C
C135
100N
NM
GND
Power input
FPGA core voltage regulator
TP119
TP163
3V3
5V
5V
R282
100K
L13
VINA
VIND
R369
100K
BLM41P600S
6
B
C142
C143
22U
100N
LM2830ZSD
L8
SW
3
5V_SENSE
D9
GND
DAP
FB
1
R138
45K3
C140
C141
22U
100N
R230
470R
LED121
GREEN
R139
10K
R283
100K
100N
TP81 TP82 TP83 TP84 TP85 TP86 TP87
3V3
B
GND
1
R284
100K
M1
3V3_SENSE
GND
GND
(p 21)
C257
EN
2
7
2UH2
2
5
4
2
2
1
U72
1
GND
GND
GND
GND
GND
R285
100K
M4
(p 21)
GND
GND
GND
GND
GND
GND
GND
100N
R258
0R
3.3V power regulator
FPGA_1V2
R286
1K
GND
GND
3.6V power regulator
FPGA_1V2_SENSE (p 21)
5V
C259
3V6
TP166
R287
100K
100N
<Schematic Path>
TOP
U70
2
C145
C294
10U
IN
R366
10K
7
100N
3
9
OUT1
OUT2
SET
1
4
GND
SHDN
FAULT
GND
GND_HEAT
CC
Schematic Title
R367
130K
5
8
C146
C296
10U
100N
Page Title
6
C295
R368
68K
33N
GND
Designed:
Approved:
JNO
JNO
Size
GND
GND
BOM Doc No:
Power
Document number
<Cage Code>
BRD3200C
Design Created Date:
W ednesday, December 03, 2008
Sheet Created Date
Saturday, March 21, 2009
A3
GND
A
EFM32 Development Kit - Mainboard
3.64V
LP3982ILD-ADJ
GND
M3
GND
C258
A
M2
Revision
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
19 of
21
5
4
3
TP113
TP112 VMCU_R
D
GND
GND
GND
GND_HEAT
6
C122
100N
IN
V+
U68A
GND
R353
0R
NM
C286
33N
8
A
R348
7
B
1
U74A
MCP6001T
AD5245-100K
R123
56K
1
5
4
R214 0R
2
2
C260
100N
TS5A3159A
33N
GND
GND
ST6
C124
100N
GND
GND
100mA calibration switch
R349
0R
SET
7
FAULT
3
9
GND
GND
5
GND
GND_HEAT
CC
8
U69A
6
8
C289
LP3982ILD-ADJ
GND
R350
18K
SHDN
C
R351
56K
33N
MCU power regulators
C281
C288
100N
10U
3 1
100N
1
C285
10U
GND
A
B
1
(p 11) AEM_VMCU_ENABLE
W
C284
LED102
GREEN
1
4
R242
10K
7
GND
GND
MCU power switch LED
AD5245-100K
VMCU_S
TP137
C194
1N
VMCU_R
VMCU_S
2
OUT
GND
1
6
7
3
5
9
TLV272
AEM_SENSE_CURRENT_RANGE1
R126
12K
LTC6102CDD
GND
4
R375
1K
NM
GND
B
1
2
R292
0R
-INS
-INF
IN+
R379
10K
5
R380
10K
VREG
V+
C204
1N
6
VVV- (HEAT)
OUT
4
GND
7
AEM_SENSE_CURRENT_RANGE2
(p 11,21)
TLV272
R376
0R
(p 11,21)
LTC6102CDD
D10
3 BAT54S
NM
R127
10K
GND
GND
2
MCU power current sense
U75B
8
1
C261
10U
C126
100N
C186
1N
VREG
V+
VVV- (HEAT)
R125
U30
4R7
U75A
3
-
3
5
9
R293
0R
IN+
R378
10K
1
6
7
1
BLM21B102S
-INS
-INF
R377
10K
8
2
2
U29
1
2
VCS
+
L22
5V
R291
43R
TP138
C210
1N
VCS
C125
100N
C
GND
GND
VMCU_R
R124
1K8
Q5
BC846AW
2
OUT1
OUT2
-
IN
R218
10K
+
2
VMCU
2
TP158
GND
R128
1K
R354
0R
U60
D
5V
GND
5V
R122
22K
VMCU_M
ST8
C287
3
18K
GND
GND
GND
3
2
C121
10U
VMCU_FB
6
CC
LP3982ILD-ADJ
GND
R358
1R8
8
FAULT
3
9
TP167
1
10U
NO
1
SHDN
1
100N
SET
7
C123
W
C120
NC
COM
4R7
R352
0R
NM
5
4
-
R215
10K
1
TP115
5V
U26
R121
1
4
OUT1
OUT2
1
IN
2
TP114
3
R120
0R
U27
2
VMCU_S
+
5V
R382
0R
R381
1K
NM
B
GND
GND
5V
GND
L23
2
5V
1
BLM21B102S
GND
L28 BLM21B102S
R355
1
1R
2
C283
1U
R357
10K
2
4
5
6
U74B
C282
VDD
SCL
SDA
AD0
R374
1R
U68B
C298
1U
C299
100N
VDD
5
100N
GND
3
2
GND
GND
MCP6001T
AD5245-100K
GND
(p 11,12,17,18) CTRLMCU_I2C_SCL
(p 11,12,17,18) CTRLMCU_I2C_SDA
GND
<Schematic Path>
TOP
5V
5V
L24
A
2
1
BLM21B102S
L27 BLM21B102S
Schematic Title
U69B
R360
2
1R
4
5
6
C290
1U
C130
100N
VDD
SCL
SDA
AD0
GND
1
2
R361
1R
3
C278
100N
VDD
4
GND
TLV272
GND
GND
Page Title
Designed:
Approved:
JNO
JNO
Size
GND
GND
Power & Decoupling
8
10K R356
AD5245-100K
A
EFM32 Development Kit - Mainboard
U75C
C291
1U
A3
BOM Doc No:
<Cage Code>
Design Created Date:
W ednesday, December 03, 2008
EFM Power and AEM
Document number
Revision
BRD3200C
Sheet Created Date
W ednesday, August 19, 2009
C
Sheet Modified Date
Tuesday, January 19, 2010
Sheet
20 of
21
5
4
3
2
1
D
D
VMCU voltage sense
TP139
TP131 TP132 TP133 TP134
TP135
U67A
2
3V3_ADC
-
VMCU_FB
R332
1
1
(p 9)
ADC_DOUT
(p 9)
(p 9)
(p 9)
ADC_DIN
ADC_#CS
ADC_CLK
AEM_SENSE_VOLTAGE (p 11)
U55A
47K
3
R333
100K
+
C272
TLV272
1N
17
18
19
10
TP140
GND
C
U67B
6
-
VMCU
7
2
1
2
3
4
5
6
7
8
(p 11) AEM_SENSE_VOLTAGE
(p 11,20) AEM_SENSE_CURRENT_RANGE1
(p 11,20) AEM_SENSE_CURRENT_RANGE2
(p 19) 5V_SENSE
(p 19) 3V3_SENSE
(p 19) FPGA_1V2_SENSE
(p 5) DISPLAY_ASENSE
(p 5) DISPLAY_KSENSE
R334
9
AEM_AUX_SENSE_VOLTAGE (p 11)
47K
5
DOUT
BUSY
15
16
ADC_VREF
SHDN
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Vref
11
C
C252
100N
COM
GND
ADS7844EB
R335
100K
+
DIN
CS
CLK
C273
TLV272
GND
1N
3V3_ADC
GND
ADC_VREF
TP136
3V3
TP160
3V3_ADC
R281
10R
C255
C256
C254
10U
100N
10U
14
13
C279
B
4
GND
D5
8
100N
2
VDD
VCC
VCC
1
20
12
5V
U67C
R280
1K
U55B
GND
GND
LM4040CIM3-3.0
B
ADS7844EB
TLV272
GND
GND
GND
GND
GND
GND
/
TOP
Schematic Title
A
A
EFM32 Development Kit - Mainboard
Page Title
Designed:
Approved:
JNO
JNO
Size
A3
4
3
Revision
BRD3200C
<Cage Code>
Sheet Created Date
Tuesday, September 08, 2009
Design Created Date:
W ednesday, December 03, 2008
5
Power Monitoring
Document number
BOM Doc No:
2
C
Sheet Modified Date
Tuesday, January 19, 2010
1
Sheet
21 of
21
R216
LED120
C245
R133
C244
C193
C187
C192
R156
R157
R350
C149
C150
C148
U69
R356
R368
R217
LED119
C153
C158
C159
C157
L3
R252
R6
R10
C4
R11
C8
R13
R12
C1
R1
R280
C135
C256
R281
C252
C188
R370
TP100
ST2
P2
C2
R2
R254
R5
R90
R266
R83
R256
R233
C237
LED94
R89
C239
ST3
U19
TP103
P3
R9
C5
R200
TP153
R96
R14
LED76
LED75
R344
C92
R94
R28
C35
TP110
U2
C16
J2
R22
R20
C9
R262
R19
C12
C13
C17
TP104
TP105
L2
R29
C11
C36
C37
R41
R16
C21
R21
R30
TP24
R35
C26
R38
R93
U18
R263
TP111
R92
R203
C25
RP1
R43
C238
C232
LED89
LED77
LED78
C240
R341
R36
C230
C227
R367
R86
R84
R87
U7
C235
C233
U45
R172
P5
P13
C98
R99
C229
C147
C90
C60
ST1
C7
R152
R173
R257
R88
C69
C6
TP102
U38
R4
C3
TP81
L10
R78
C46
C231
P1
R3
U1
R8
TP101
R95
C61
C241
C228
TP99
R7
L24
R85
R80
C89
C88
R81
R79
C101
C99
C96
C95
R57
R300
C43
C234
R295
SW8
C65
R56
P4
C42
C284
C167
R52
U56
R168
R331
R100
R359
C102
R98
C40
C32
R82
C70
C66
R199
C103
R288
C63
R54
R53
R118
C48
R116
C262
C97
R117
U60
R255
R290
C41
U6
C263
C52
U17
C105
C64
C67
C56
C116
C62
C117
C118
U52
LED95
C33
R351
C285
C145
TP157
C91
C47
R211
R104
R212
R197
C57
LED79
C119
U57
R161
C80
C106
C79
C100
R73
R311
R208
R101
Q7
U25
C289
R354
C294
R209
C76
R234
C34
C273
RP13 RP14
R336
U70
C281
R335
R213
R241
LED123
L25
R334
C75
R42
D7
R365
C288
C295
L12
C191
C185
R218
R366
SW9
L17
TP25
C180
C168
C112
C110
C296
U13
U21
C146
R306
U9
U61
TP116
C190
C189
C181
C169
R55
R294
R162
L26
C280
LED101
TP85
P12
C130
C78
C152
C179
R360
C77
R248
U36
U41
U42
R160
C74
U20
R304
R60
R65
C87
RP19
D2
RP3
R58
R63
R72
LED81
C82
RP20
RP21
RP15
R239
R310
C111
RP22
C290
U15
C156
C183
R163
C81
C224
C83
U14
L4
R91
C182
R159
C223
C204
C225
C72
R59
R64
R68
R103
R71
LED80
R102
U12
C51
R205
C248
U54
R206
R106
C86
RP16
RP17
RP18
C73
U58
LED87
R105
C84
U11
R240
C264
D8
LED86
U10
R307
C247
R204
Q8
C217
U8
R265
R380
LED124
C184
U75
R107
C215
C213
R364
U53
C210
C151
LED98
L6
TP137
R303
C211
R127
C291
P10
R247
D5
R361
C278
R289
C194
U40
TP138
C251
C254
R242
R377
P14
C214
R371
L16
P6
C255
C259
R379
U44
R287
P9
TP86
J3
D10
U37
R286
P8
U55
R382
C219
U35 U39
C258
R376
U5
U4
R285
C250
C221
U16
Q5
C222
C216
R284
R128
C260
C122
C121
U29
R126
C212
C257
R296
R381
C165
R282
R375
C166
R283
L27
C126
TP112
R166
C160
L22
R358
C279
R167
C154
R378
C155
C272
R298
C186
R253
C39
R293
R47
C38
C261
R45
C85
ST9
R333
R332
U26 LED102
TP114
C125
R312
C124
R297
R121
R215
R352
R214
R122
R291
L19
R292
R348
U67
R124
R238
R125
R123
C287
R120
U27
L28
ST8
U30
C120
R174
R237
R48
TP158
C218
TP115
R357
U68
R151
L18
L15
TP121
C283
C298
U74
R349
C123
C282
C286
LED93
TP82
R374
C142
C138
R250
LED92
R138
C139
C136
R232
R369
C299
C143
R355
R353
R139
C141
L23
L13
TP119
R46
R258
U72
C140
Q3
LED99
R249
D9
R373
C137
R246
L8
R230
C297
U73
R372
R231
L7
ST6
TP113
LED121
LED122
R15
R236
LED97
L1
R40
C29
R326
C30
P15
C205
R132
C132
U31
TP23
P11
R235
C202
R279
LED96
R251
C195
C201
LED100
U43
C207
C208
P7
R171
RP6
C162
R277
R165
TP89
R169
R145
R244
R164
R170
LED90
R144
R345
C164
R131
C163
R362
D6
TP107
C161
TP120
C293
R276
C114
J1
C28
R17
D1
R278
R268
R267
R115
R269
R114
R275
R110
R112
C115
R23
R363
C134
C133
C113
C19
R39
R25
TP106
C14
C292
P16
U3
C206
C20
C199
R273
C10
C200
C196
R26
C18
C197
R33
R24
L5
R32
R27
C131
L11
C144
C129
R272
C203
C22
R325
TP108
C31
C27
TP109
C209
C198
C15
C249
C23
R274
RP7
TP84
R182
R181
R180
R179
R178
R177
R176
R175
TP87
TP83
C178
LED118
LED117
LED116
R330
LED115
R329
LED114
LED113
LED112
LED111
LED110
R327
R328
LED109
C176
LED108
R193
C175
LED107
C177
R192
R245
LED91
SW10
LED106
C174
SW7
LED105
R194
LED104
R191
LED103
SW6
R195
R346
C246
R219
R196
R220
SW5
C173
R186
R190
SW4
C172
R185
R189
SW3
R187
SW2
C171
R184
R188
C170
R183
TP139
TP136
TP167
TP135
TP163
TP131
TP160
TP88
TP140
TP166
TP164
TP36
TP165
TP37
TP45
TP43
TP40
TP44
TP42
TP26
TP35
TP28
TP29
TP34
TP117
TP69
TP134
TP39
TP133
TP50
TP41
TP132
TP30
TP27
TP154
TP38
TP33
TP155
TP162
TP156
TP161
TP98
TP61
TP60
P17
TP63
TP130
TP62
TP159
TP74
TP31
Preliminary
...the world's most energy friendly microcontrollers
Table of Contents
1. Introduction .............................................................................................................................................. 2
1.1. Features ....................................................................................................................................... 2
1.2. Board Configuration ........................................................................................................................ 2
2. Kit Block Diagram ..................................................................................................................................... 3
3. Mainboard hardware layout ......................................................................................................................... 4
4. Power supply ........................................................................................................................................... 5
4.1. USB ............................................................................................................................................. 5
4.2. External power supply ..................................................................................................................... 5
5. Reset infrastructure ................................................................................................................................... 6
5.1. MCU ............................................................................................................................................ 6
5.2. Board controller .............................................................................................................................. 6
6. Peripherals ............................................................................................................................................... 7
6.1. Pushbuttons ................................................................................................................................... 7
6.2. DIP switches .................................................................................................................................. 7
6.3. Joystick ......................................................................................................................................... 7
6.4. LEDs ............................................................................................................................................ 7
6.5. Differential analog input ................................................................................................................... 7
6.6. Single ended analog inputs .............................................................................................................. 7
6.7. Line in / Audio in ............................................................................................................................ 7
6.8. Line Out / Audio out ........................................................................................................................ 8
6.9. RS232 .......................................................................................................................................... 8
6.10. Accelerometer .............................................................................................................................. 8
6.11. IrDA ............................................................................................................................................ 8
6.12. Potmeter ..................................................................................................................................... 8
6.13. Ambient light sensor ...................................................................................................................... 8
2
6.14. I C EEPROM ............................................................................................................................... 9
2
6.15. I C Temperature sensor ................................................................................................................. 9
6.16. SPI Flash .................................................................................................................................... 9
6.17. microSD ...................................................................................................................................... 9
6.18. TFT LCD ..................................................................................................................................... 9
6.19. SRAM ......................................................................................................................................... 9
6.20. NOR Flash .................................................................................................................................. 9
7. Board Support Package ............................................................................................................................ 10
7.1. Installation location ........................................................................................................................ 10
7.2. Resource usage ............................................................................................................................ 10
7.3. Application Programming Interface ................................................................................................... 10
7.4. Example Applications ..................................................................................................................... 11
7.5. How to include in your own applications ............................................................................................ 12
7.6. Chip errata .................................................................................................................................. 12
8. Configuration .......................................................................................................................................... 13
8.1. MCU voltage ................................................................................................................................ 13
8.2. Debug settings ............................................................................................................................. 13
8.3. Peripheral configuration .................................................................................................................. 13
8.4. Program MCU .............................................................................................................................. 13
8.5. Upload files .................................................................................................................................. 13
9. Advanced Energy Monitor ......................................................................................................................... 14
9.1. AEM Display ................................................................................................................................ 14
9.2. AEM configuration ......................................................................................................................... 14
9.3. AEM theory of operation ................................................................................................................. 14
9.4. AEM accuracy and performance ...................................................................................................... 14
10. Board controller ..................................................................................................................................... 15
10.1. Register Map .............................................................................................................................. 15
10.2. Register Description ..................................................................................................................... 16
11. Connectivity .......................................................................................................................................... 30
11.1. Resource connections .................................................................................................................. 30
12. Connectors ........................................................................................................................................... 33
12.1. EFM32 and EXP32 connectors ...................................................................................................... 33
12.2. Debug connector ......................................................................................................................... 33
13. Debugging ............................................................................................................................................ 34
14. IDEs .................................................................................................................................................... 35
14.1. IAR ........................................................................................................................................... 35
14.2. KEIL ......................................................................................................................................... 35
15. Gecko Commander and Upgrades ............................................................................................................ 36
15.1. Available commands .................................................................................................................... 36
15.2. Upgrades ................................................................................................................................... 36
16. Version information ................................................................................................................................ 37
17. MCU board ........................................................................................................................................... 38
18. Prototyping Board .................................................................................................................................. 39
18.1. Overview .................................................................................................................................. 39
19. Errata .................................................................................................................................................. 40
19.1. DVK hardware errata ................................................................................................................... 40
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Preliminary
...the world's most energy friendly microcontrollers
19.2. DVK firmware errata .................................................................................................................... 40
20. Schematic ............................................................................................................................................ 42
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Preliminary
...the world's most energy friendly microcontrollers
List of Figures
2.1. EFM32-G8XX-DK Block Diagram ............................................................................................................... 3
3.1. EFM32-G8XX-DK hardware layout ............................................................................................................. 4
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Preliminary
...the world's most energy friendly microcontrollers
List of Tables
7.1. GPIO Usage ........................................................................................................................................
9.1. AEM accuracy ......................................................................................................................................
11.1. Connections .......................................................................................................................................
11.2. Nomenclature .....................................................................................................................................
12.1. Debug connector pinout ........................................................................................................................
13.1. Debug modes .....................................................................................................................................
15.1. Gecko Commander ..............................................................................................................................
16.1. Current versions ..................................................................................................................................
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14
30
32
33
34
36
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