Download PowerPC 405GPr Embedded Processor Data Sheet

Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
PPC405GPr New Mode Strapping Pin Assignments
Function
Option
PLL Tuning
See the PowerPC 405GPr
Embedded Processor User’s
Manual for details.
PLL Forward Divider A
Ball Strapping
AF3
(UART0_Tx)
AF2
AD16
(UART0_DTR) (UART0_RTS)
Choice 1; TUNE[9:0] = 1010111100
0
0
0
Choice 2; TUNE[9:0] = 0100111000
0
0
1
Choice 3; TUNE[9:0] = 0100110110
0
1
0
Choice 4; TUNE[9:0] = 0100111100
0
1
1
Choice 5; TUNE[9:0] = 0100111000
1
0
0
Choice 6; TUNE[9:0] = 1000111100
1
0
1
Choice 7; TUNE[9:0] = 1000111110
1
1
0
Choice 8; TUNE[9:0] = 1011111110
1
1
1
D16
(DMAAck0)
B15
(DMAAck1)
AC9
GPIO5[TS3]
Divide by 8
0
0
0
Divide by 7
0
0
1
Divide by 6
0
1
0
Divide by 5
0
1
1
Divide by 4
1
0
0
Divide by 3
1
0
1
Divide by 2
1
1
0
2
Divide by 1
PLL Forward Divider B
(Part 1 of 3)
1
1
1
P25
(EMCTxD3)
L24
(EMCTxD2)
AE8
GPIO6[TS4]
Divide by 8
0
0
0
Divide by 7
0
0
1
Divide by 6
0
1
0
Divide by 5
0
1
1
Divide by 4
1
0
0
Divide by 3
1
0
1
Divide by 2
1
1
0
Divide by 1
1
1
1
2
53