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OPB Multi Channel HDLC
Interface
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Product Overview
Introduction
LogiCORE™ Facts
This document provides the design specification for the
OPB High Level Data Link Control (HDLC) Interface Intellectual Property (IP) solution. It defines the architecture and
interface requirements to this module. This includes registers the user must initialize for proper operation. This module is compatible with {ITU Q.921}. See the Specification
Exceptions of the full datasheet.
The Xilinx HDLC design allows the customer to tailor the
HDLC to suit their application by setting certain parameters
to enable/disable features. The parameterizable features of
the design are discussed in HDLC Design Parameters.
Core Specifics
Supported Device
Family
Virtex™-II, Virtex-II Pro™
Resources Used
(minimum settings)
The OPB HDLC interface is a soft IP core designed for Xilinx FPGAs and contains the following features:
LUTs
FFs
Block
RAMs
6
1203
604
2
Special Features
RPM Core
Provided with Core
Documentation
Features
I/O
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Design File Formats
VHDL
Constraints File
N/A
•
Support for one to eight independent full duplex HDLC
channels
Verification
N/A
•
Each independent channel may have 1 to 32 TDM
sub-channels.
Instantiation
Template
N/A
•
Receive FIFO buffer of selectable depth
N/A
•
Transmit FIFO buffer of selectable depth
Reference Designs
& application notes
•
Selectable 8/16 bit address receive address detection
Additional Items
N/A
•
Selectable receive frame address discard
•
Selectable receive broadcast address detection.
Broadcast address = 0xFF.
•
Selectable 16 bit (CRC-CCITT) or 32 bit (CRC-32)
frame check sequence
•
16-bit CRC error counter and Aborted frame counter
Verification
ModelSim PE 5.7d
•
Multiple Events/Interrupts including:
Simulation
ModelSim PE 5.7d
Synthesis
XST - ISE 6.1i
Design Tool Requirements
-
Rx FCS error interrupt
-
Rx frame alignment error interrupt
-
Memory buffer overrun/underrun interrupts
-
Interrupt generated when either error counter rolls
over
ISE 6.1i or later
Xilinx
Implementation
Tools
with latest EDK
Support
•
Tx frame abort control
•
Memory mapped direct I/O interface to registers and
memory buffers.
•
Flag sharing between back to back frames
•
Independent Rx and Tx data rates for each physical
channel
Support provided by Xilinx, Inc.
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
Product Overview
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