Download Embedded Linux Primer: A Practical, Real-World

Command
Activatecommandenablesagivenrowforsubsequentaccess,suchasduringa
toNext
0x1 burstcycle.ThistimingparameterenforcestheminimumtimebetweenPrecharge
Activate
toasubsequentActivatecycleandisdictatedbytheSDRAMchip.Thecorrect
(PTA)
valuemustbeobtainedfromtheSDRAMchipspecification.Inthiscase,0x1
representstwoclockcycles,asdeterminedfromthe405GPuser'smanual.
Read/Write
to
ThistimingparameterenforcestheminimumtimedelaybetweenagivenSDRAM
Precharge
readorwritecommandtoasubsequentPrechargecommand.Thecorrectvalue
0x2
Command
mustbeobtainedfromtheSDRAMchipspecification.Inthiscase,0x2represents
Minimum
threeclockcycles,asdeterminedfromthe405GPuser'smanual.
(CTP)
SDRAM
Thistimingparameterenforcestheminimumtimedelaybetweenassertionof
Command
addressorcommandcycletobankselectcycle.Thecorrectvaluemustbe
0x1
Leadoff
obtainedfromtheSDRAMchipspecification.Inthiscase,0x1representstwo
(LDF)
clockcycles,asdeterminedfromthe405GPuser'smanual.
ThefinaltimingparameterconfiguredbytheU-BootexampleinListingD-1istherefreshtiming
registervalue.Thisregisterrequiresasinglefieldthatdeterminestherefreshintervalenforcedbythe
SDRAMcontroller.Thefieldrepresentingtheintervalistreatedasasimplecounterrunningatthe
SDRAMclockfrequency.Intheexamplehere,weassumed100MHzastheSDRAMclockfrequency.
Thevalueprogrammedintothisregisterinourexampleis0x05f0_0000.FromthePowerPC405GP
User'sManual,wedeterminethatthiswillproducearefreshrequestevery15.2microseconds.As
withtheothertimingparameters,thisvalueisdictatedbytheSDRAMchipspecifications.
AtypicalSDRAMchiprequiresonerefreshcycleforeachrow.Eachrowmustberefreshedin
theminimumtimespecifiedbythemanufacturer.InthechipreferencedinSectionD.4.1,"Suggestions
for Additional Reading," the manufacturer specifies that 8,192 rows must be refreshed every 64
milliseconds. This requires generating a refresh cycle every 7.8 microseconds to meet the
specificationsforthisparticulardevice.