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Generating Test Patterns
Setting Up Design and Tool Behavior
Setting the Test Cycle Width
When you set the test cycle width, you specify the number of timeframes needed per test cycle.
The larger the number you enter for timeframes, the better the resolution you have when adding
pin constraints. The smaller the number of timeframes you specify per cycle, the better the
performance FlexTest has during ATPG.
By default, FlexTest assumes a test cycle of one timeframe. However, typically you will need to
set the test cycle to two timeframes. And if you define a clock using the Add Clocks command,
you must specify at least two timeframes. In a typical test cycle, the first timeframe is when the
data inputs change (forced and measured) and the second timeframe is when the clock changes.
If you have multi-phased clocks, or want certain data pins to change when the clock is active,
you should set three or more timeframes per test cycle.
At least one input or set of inputs should change in a given timeframe. If not, the timeframe is
unnecessary. Unnecessary timeframes adversely affect FlexTest performance. When you
attempt to exit Setup mode, FlexTest checks for unnecessary timeframes, just prior to design
flattening. If the check fails, FlexTest issues an error message and remains in Setup mode.
To set the number of timeframes in a test cycle, you use the Set Test Cycle command. This
command’s usage is as follows:
SET TEst Cycle integer
Or, if you are using the graphical user interface, you can select the SET TEST CYCLE palette
menu item or the Setup > Test Cycle... pulldown menu item.
Defining the Cycle Behavior of Primary Inputs
As discussed previously, testers are naturally cyclic and the test patterns FlexTest generates are
also cyclic. Events occur repeatedly, or in cycles. Cycles further divide into timeframes. Clocks
exhibit cyclic behavior and you must define this behavior in terms of the test cycle. Thus, after
setting the test cycle width, you need to define the cyclic behavior of the circuit’s primary
inputs.
There are three components to describing the cyclic behavior of signals. A pulse signal contains
a period (that is equal to or a multiple of test cycles), an offset time, and a pulse width.
Constraining a pin lets you define when its signal can change in relation to the defined test
cycle. To add pin constraints to a specific pin, you use the Add Pin Constraints command. This
command’s usage is as follows:
ADD PIn Constraints primary_input_pin... constraint_format
The only way to define a constant value signal is by using the constant constraint formats. And
for a signal with a hold value, the definition includes a period and an offset time.
There are eleven constraint formats from which to chose. The constraint values (or waveform
types) further divide into the three waveform groups used in all automatic test equipment:
Scan and ATPG Process Guide, V8.2004_2
April 2004
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