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Table of Contents TABLE OF CONTENTS [continued] Generating Patterns for a Boundary Scan Circuit............................................. 9-94 Dofile and Explanation .................................................................................. 9-95 TAP Controller State Machine....................................................................... 9-96 Test Procedure File and Explanation ............................................................. 9-97 Creating Instruction-Based Test Sets (FlexTest) ............................................ 9-102 Instruction-Based Fault Detection................................................................ 9-102 Instruction File Format................................................................................. 9-104 Verifying Design and Test Pattern Timing..................................................... 9-106 Simulating the Design with Timing ............................................................. 9-106 Checking for Clock-Skew Problems with Mux-DFF Designs..................... 9-110 Chapter 10 Test Pattern Formatting and Timing ............................................................... 10-1 Test Pattern Timing Overview.......................................................................... 10-2 Timing Terminology......................................................................................... 10-2 Defining Scan-Related Event Timing............................................................... 10-3 Converting Test Procedures to Test Cycles ................................................... 10-4 Test Procedure Timing Examples .................................................................. 10-5 Test Procedure Timing Issues ...................................................................... 10-11 Defining Non-Scan Related Event Timing..................................................... 10-13 FastScan Non-Scan Event Timing ............................................................... 10-13 FlexTest Non-Scan Event Timing................................................................ 10-17 Global Timing Issues in the Timing File ..................................................... 10-19 Performing Timing Checks for Tester Formats.............................................. 10-20 Tester Format Restrictions for FastScan ...................................................... 10-21 Tester Format Restrictions for FlexTest ...................................................... 10-23 Saving the Patterns ......................................................................................... 10-23 Features of the Formatter ............................................................................. 10-24 Pattern Formatting Issues............................................................................ 10-25 Saving Patterns in Basic Test Data Formats ................................................ 10-27 Saving in ASIC Vendor Data Formats......................................................... 10-40 ASIC/IC Design-for-Test Process Guide, V8.6_1 December 1997 xiii
