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Chapter 1: Xilinx Blockset
CIC Compiler 4.0
This block is listed in the following Xilinx Blockset libraries: AXI4, DSP and Index.
The Xilinx CIC Compiler provides the ability to design and implement
AXI4-Stream-compliant Cascaded Integrator-Comb (CIC) filters for a
variety of Xilinx FPGA devices.
CIC filters, also known as Hogenauer filters, are multi-rate filters
often used for implementing large sample rate changes in digital
systems. They are typically employed in applications that have a
large excess sample rate. That is, the system sample rate is much
larger than the bandwidth occupied by the processed signal as in
digital down converters (DDCs) and digital up converters (DUCs).
Implementations of CIC filters have structures that use only adders,
subtractors, and delay elements. These structures make CIC filters appealing for their
hardware-efficient implementations of multi-rate filtering.
Sample Rates and the CIC Compiler Block
The CIC Compiler block must always run at the system rate because the CIC Compiler block
has a programmable rate change option and Simulink cannot inherently support it. You
should use the "ready" output signal to indicate to downstream blocks when a new sample
is available at the output of the CIC Compiler block.
The CIC will downsample the data, but the sample rate will remain at the clock rate. If you
look at the output of the CIC Compiler block, you will see each output data repeated R
times for a rate change of R while the data_tvalid signal pulses once every R cycles. The
downstream blocks can be clocked at lower-than-system rates without any problems as
long as the clock is never slower than the rate change R.
There are several different ways this can be handled. You can leave the entire design
running at the system rate then use registers with enables, or enables on other blocks to
capture data at the correct time. Or alternatively, you can use a downsample block
corresponding to the lowest rate change R, then again use enable signals to handle the
cases when there are larger rate changes.
If there are not many required rate changes, you can use MUX blocks and use a different
downsample block for each different rate change. This might be the case if the downstream
blocks are different depending on the rate change, basically creating different paths for
each rate. Using enables as described above will probably be the most efficient method.
If you are not using the CIC Compiler block in a programmable mode, you can place an
up/down sample block after the CIC Compiler to correctly pass on the sample rate to
downstream blocks that will inherit the rate and build the proper CE circuitry to
automatically enable those downstream blocks at the new rate.
Vivado: Designing with System Generator
UG958 (v2015.3) September 30, 2015
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