Download Power Aware Simulation User`s Manual

UPF Commands and Reference
Accessing Generate Blocks in UPF
•
For ONE_HOT resolution, if at any point in time more than one supply source
that is driving the net is anything other than OFF
•
For PARALLEL resolution, if any of the potentially conducting paths can be
traced to more than one root supply driver
For UPF 1.0, under these conditions the state of the supply net was set to OFF.
o
For UPF 2.0, the default state of supply nets and ports is set to OFF. You can change
this to FULL_ON with the vopt option -pa_disable=defaultoff.
Accessing Generate Blocks in UPF
In order to access hierarchy as defined in individual languages or as Power Aware simulation
accepts it, UPF uses square bracket pairs, [ ]. This is because UPF is written in Tcl, so in some
contexts square brackets can be interpreted as special command substitution characters—though
you usually need to use escape characters with them for that purpose. The exception to this
when using a UPF command argument that takes a list of values enclosed in braces, { }, because
that is not actually command substitution.
The following examples show how to generate references in UPF for both Verilog and VHDL.
create_power_domain pd -elements { top_vh/for_genvh__1/bot_vh_inst
top_vl/forgen_vl[1]/bot_vl_inst }
create_power_domain pd
-elements { top_vh/for_genvh(1)/bot_vh_inst
top_vl/forgen_vl[1]/bot_vl_inst }
Limitation
Connections from UPF to HDL port of inout type are not supported for inout capability. These
connections are made in such a way that UPF is driving data to the HDL port.
Supported UPF Attributes
Power Aware simulation supports the use of UPF attributes used to express the power intent in
an HDL model. You can specify these attributes using the following methods:
•
UPF commands (set_design_attributes, set_port_attributes, set_isolation,
set_pin_related_supply, set_simstate_behavior, set_retention_elements)
Power Aware Simulation User’s Manual, v10.2c
261