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Page Table Search Operation
TLB. When this occurs, the processor automatically saves information about the access and
the executing context. Table 5-9 provides a summary of the implementation-specific
exceptions, registers, and instructions that can be used by the TLB miss exception handler
software in 603e systems. Refer to Chapter 4, “Exceptions,” for more information about
exception processing.
Table 5-9. Implementation-Specific Resources for Table Search Operations
Resource
Exceptions
Registers
Instructions
Name
Description
Instruction TLB miss
exception
(vector offset 0x1000)
No matching entry found in ITLB.
Data TLB miss on load
exception
(vector offset 0x1100)
No matching entry found in DTLB for a load data access.
Data TLB miss on store
exception—also caused
when changed bit must
be updated
(vector offset 0x1200)
No matching entry found in DTLB for a store data access or matching DLTB
entry has C = 0 and access is a store.
IMISS and DMISS
When a TLB miss exception occurs, the IMISS or DMISS register contains
the 32-bit effective address of the instruction or data access that caused the
miss exception.
ICMP and DCMP
The ICMP and DCMP registers contain the word to be compared with the
first word of a PTE in the table search software routine to determine if a PTE
contains the address translation for the instruction or data access. The
contents of ICMP and DCMP are automatically derived by the 603e when
a TLB miss exception occurs.
HASH1 and HASH2
The HASH1 and HASH2 registers contain the primary and secondary
PTEG addresses that correspond to the address causing a TLB miss.
These PTEG addresses are automatically derived by the 603e by
performing the primary and secondary hashing function on the contents of
IMISS or DMISS, for an ITLB or DTLB miss exception, respectively.
RPA
The system software loads a TLB entry by loading the second word of the
matching PTE entry into the RPA register and then executing the tlbli or
tlbld instruction (for loading the ITLB or DTLB, respectively).
tlbli rB
Loads the contents of the ICMP and RPA registers into the ITLB entry
selected by <ea> and SRR1[WAY].
tlbld rB
Loads the contents of the DCMP and RPA registers into the DTLB entry
selected by <ea> and SRR1[WAY].
In addition, the 603e contains the following features that do not specifically control the
603e MMU, but that are implemented to increase performance and flexibility in the
software table search routines whenever one of the three TLB miss exceptions occurs:
•
5-32
Temporary GPR0–GPR3. These registers are available as r0–r3 when MSR[TGPR]
is set. The 603e automatically sets MSR[TGPR] for these cases, allowing these
exception handlers to have four registers that are used as scratchpad space, without
having to save or restore this part of the machine state that existed when the
exception occurred. Note that MSR[TGPR] is cleared when the rfi instruction is
MPC603e RISC Microprocessor User’s Manual