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FlexModel User’s Manual
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Chapter 2: Using FlexModels
Developing VERA Interrupt Routines
To use interrupts in VERA Command Mode, follow the same procedures described in
“Developing HDL Interrupt Routines” on page 33. However, do not include the interrupt
signal in the VERA testbench. Instead, define the interrupt signal in the top-level VHDL
or Verilog testbench, just as if you were in HDL Command Mode.
Note that in VERA, as in HDL, you cannot use model commands with the wait_mode
parameter set to true (FLEX_WAIT_T) or result (model_rslt) commands within
interrupt routines.
Defining the Interrupt Signal
When you define the interrupt signal in the VERA testbench, you must pass in the full
path to the signal in the top-level VHDL testbench or reg in the top-level Verilog
testbench. The following example shows how to define an interrupt signal in a top-level
Verilog testbench:
#include <vera_defines.vrh>
#include “flexmodel_pkg.vrh”
#include “model_pkg.vrh”
program my_test
{
// Create an instance of the model class.
ModelFx model = new(“modelInstName”, “u1.CLK”);
// Define the Intr Signal
// NOTE : here INTR_SIGNAL is the name of a reg in the top
//
level verilog testbench and we pass the full path
//
to the interrupt signal.
model.define_intr_signal(“model_test_top.INTR_SIGNAL”, status);
}
Monitoring the Interrupt Signal
The following example illustrates one way to monitor the interrupt signal in a top-level
VHDL testbench. For other methods of determining when the interrupt signal has been
toggled in the Verilog or VHDL testbench, and for more information on VERA syntax,
refer to the Vera Verification System User’s Manual.
#include <vera_defines.vrh>
#include “flexmodel_pkg.vrh”
#include “model_pkg.vrh”
// Create A VERA Port data type.
port my_port { intrSignal; }
program my_test
{
// Create an instance of the model class.
August 28, 2001
Synopsys, Inc.
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