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DesignWare IP Family Quick Reference Guide 100111001 RAM DW_ram_rw_a_dff Asynchronous Single Port RAM (Flip-Flop-Based) 001101001 DW_ram_rw_a_dff Asynchronous Single Port RAM (Flip-Flop-Based) rw_addr ● Parameterized word depth ● Parameterized data width ● Asynchronous static memory wr_n ● Parameterized reset implementation test_mode ● High testability using DFT Compiler data_in cs_n data_out test_clk rst_n Table 1: Pin Description Pin Name rst_n cs_n wr_n test_mode test_clk rw_addr Width Direction 1 bit Input 1 bit Input 1 bit Input 1 bit Input 1 bit Input ceil(log2[depth]) bit(s) Input Function Reset, active low Chip select, active low Write enable, active low Enables test_clk Test clock to capture data during test_mode Address bus data_in data_out data_width bit(s) data_width bit(s) Input data bus Output data bus Input Output Table 2: Parameter Description Parameter data_width depth rst_mode Values 1 to 256 2 to 256 0 or 1 Description Width of data_in and data_out buses Number of words in the memory array (address width) Determines if the rst_n input is used. 0 = rst_n initializes the RAM, 1 = rst_n is not connected Table 3: Synthesis Implementations Implementation Name str April 2003 Function Synthesis model Synopsys, Inc. License Required DesignWare-Foundation 169
