Download 15-1

— Optional pin usable as an external event counter (pulse accumulator) with
overflow and interrupt capability after a pre-determined number of external
events
— Usable as a regular free-running up-counter
— Capable of driving a dedicated 16-bit counter bus to provide timing information
to action submodules — the value driven is the contents of the 16-bit upcounter register
— Optional pin to externally force a load of the counter with modulus value
• Ten MIOS double action submodules (MDASM), each with these features:
— Versatile 16-bit dual action unit allowing two events to occur before software
intervention is required
— Six software selectable modes allowing the MDASM to perform pulse width
and period measurements, PWM generation, single input capture and output
compare operations as well as port functions
— Software selection of one of the two possible 16-bit counter buses used for timing operations
— Flag setting and possible interrupt generation after MDASM action completion
— Software selection of output pulse polarity
— Software selection of totem-pole or open-drain output
— Software readable output pin status
• Eight MIOS pulse width modulation submodules (MPWMSM), each with these
features:
— Output pulse width modulated (PWM) signal generation with no software involvement
— Built-in 8-bit programmable prescaler clocked by the MCPSM
— PWM period and pulse width values provided by software:
• Double-buffered for glitch-free period and pulse width changes
• 2-cycle minimum output period/pulse-width increment
(50 ns at fSYS = 40 MHz)
• 50% duty-cycle output maximum frequency: 10 MHz
• Up to 16 bits output pulse width resolution
• Wide range of periods:
— 16 bits of resolution: period range from 3.27 ms (with 50 ns steps) to 6.71
s (with 102.4 µs steps)
— 8 bits of resolution: period range from 12.8 µs (with 50 ns steps) to 26.2 ms
(with 102.4 µs steps)
• Wide range of frequencies:
— Maximum output frequency at fSYS = 40 MHz with 16 bits of resolution and
divide-by-2 prescaler selection: 305 Hz (3.27 ms.)
— Minimum output frequency at fSYS = 40 MHz with 16 bits of resolution and
divide-by-4096 prescaler selection: 0.15 Hz (6.7 s.)
— Maximum output frequency at fSYS = 40 MHz with 8 bits of resolution and
divide-by-2 prescaler selection: 78125 Hz (12.8 µs.)
— Minimum output frequency at fSYS = 40 MHz with 8 bits of resolution and
divide-by-4096 prescaler selection: 38.14 Hz (26.2 ms.)
— Programmable duty cycle from 0% to 100%
— Possible interrupt generation after every period
MPC555
USER’S MANUAL
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 15 September 1999
MOTOROLA
15-2