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External Signal Description Table 22-2. Pin Function Selected MTMOD0 = 0 MTMOD0 = 1 Pin Name Module selected BDM JTAG — Pin Function — BKPT DSI DSO DSCLK TCK TMS TDI TDO TRST TCK BKPT DSI DSO DSCLK When one module is selected, the inputs into the other module are disabled or forced to a known logic level as shown in Table 22-3, in order to disable the corresponding module. Table 22-3. Signal State to the Disable Module MTMOD0 = 0 MTMOD0 = 1 Disabling JTAG TRST = 0 TMS = 1 — Disabling BDM — Disable DSCLK DSI = 0 BKPT = 1 NOTE The MTMOD0 does not support dynamic switching between JTAG and BDM modes. 22.2.1.2 Test Clock Input (TCK) The TCK pin is a dedicated JTAG clock input to synchronize the test logic. Pulses on TCK shift data and instructions into the TDI pin on the rising edge and out of the TDO pin on the falling edge. TCK is independent of the processor clock. The TCK pin has an internal pull-up resistor and holding TCK high or low for an indefinite period does not cause JTAG test logic to lose state information. 22.2.1.3 Test Mode Select/Breakpoint (TMS/BKPT) The TMS pin is the test mode select input that sequences the TAP state machine. TMS is sampled on the rising edge of TCK. The TMS pin has an internal pull-up resistor. The BKPT pin is used to request an external breakpoint. Assertion of BKPT puts the processor into a halted state after the current instruction completes. 22.2.1.4 Test Data Input/Development Serial Input (TDI/DSI) The TDI pin is the LSB-first data and instruction input. TDI is sampled on the rising edge of TCK. The TDI pin has an internal pull-up resistor. The DSI pin provides data input for the debug module serial communication port. MCF547x Reference Manual, Rev. 5 Freescale Semiconductor 22-3
