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The 6502 microprocessor runs from a constant clock and so its
requirements for memory access are predictable. Every 250 nanoseconds,
control of the RAM address lines is switched between the microprocessor
and the CRTC. Thus, in each one microsecond period, the microprocessor
has two RAM accesses and the CRTC has two RAM accesses. Because the
CRTC generates a sequence of addresses in order to refresh the VDU
display, all the row address lines of the RAMs are constantly cycled.
The addressing methods have been designed so that in each screen mode
the dynamic RAMs are automatically refreshed by virtue of the
sequential CRTC accesses.
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