Download Xilinx PlanAhead User Guide
Transcript
Outputs for ISE Implementation Table A-6: Outputs For ISE Implementation (Cont’d) Output Exported IP Description Exporting IP writes the EDIFs and UCF s for specified netlist modules for use when creating reusable IP blocks. When you run the Export IP command on a selected module instance in the design it exports the Pblock logical hierarchy and placement constraints. The exported files include the EDIF netlist and UCF physical constraints in the original logical netlist format. This allows for easier implementation in the next design by keeping the interface identical. You can use the exported UCF to re-create the Pblock placement constraints. You can duplicate identical placement for multiple modules by moving the modules after they are imported. Figure 10-20, page 329 is an example of how Export Pblock and Export IP can be used to export different parts of the design, based on either logical (Export IP) or physical (Export Pblock) hierarchy. ISE Launch Scripts (jobx.bat/sh & runme.bat/sh & .ISE_command.rst) When you launch a run, the PlanAhead tool creates ISE launch scripts automatically. These scripts contain commands and command-line options specified in the PlanAhead Strategy. The jobx.bat/sh scripts are located under the project run directory in a /jobs subdirectory. These scripts sequentially launch each selected run. The script calls each run-specific runme.bat|sh script. You can launch these scripts independently also. PlanAhead User Guide UG632 (v13.4) January 18, 2012 www.xilinx.com 419
Related documents
Xilinx PlanAhead User Guide
GigaBee XC6SLX Series User Manual
Xilinx Vivado Design Suite User Guide: Design Flows Overview
Xilinx ISim User Guide (UG660)
Paper Title (use style: paper title)
Xilinx Partial Reconfiguration User Guide
GigaBee XC6SLX Series User Manual
EDK Reference Manual
Vivado Design Suite User Guide
Xilinx Spartan -6 FPGA LX9 MicroBoard User Guide
SPEDE User`s Manual.2
Sequoia++ User Manual