Download SmartFusion2 High Speed DDR Interfaces User's Guide

SmartFusion2 SoC FPGA High Speed DDR Interfaces User’s Guide
PHY_FIFO_WE_SLAVE_RATIO_4_CR
Table 1-132 • PHY_FIFO_WE_SLAVE_RATIO_4_CR
Bit
Number
Name
Reset
Value
Description
[31:7]
Reserved
0x0
Software should not rely on the value of a reserved
bit. To provide compatibility with future products, the
value of a reserved bit should be preserved across a
read-modify-write operation.
[6:0]
REG_PHY_FIFO_WE_SLAVE_RATIO
0x0
[54:48] bits of REG_PHY_FIFO_WE_SLAVE_RATIO
Lowest 11 bits are from data slice 0, next 11 bits are
for data slice 1, etc.
PHY_GATELVL_INIT_MODE_CR
Table 1-133 • PHY_GATELVL_INIT_MODE_CR
Bit
Number
Name
Reset
Value
[31:1]
Reserved
0x0
0
REG_PHY_GATELVL_INIT_MODE
0x0
Description
Software should not rely on the value of a reserved
bit. To provide compatibility with future products, the
value of a reserved bit should be preserved across a
read-modify-write operation.
The user programmable init ratio selection mode.
1: Selects a starting ratio value based
REG_PHY_GATELVL_INIT_RATIO port.
on
0: Selects a starting ratio value based on write
leveling of the same data slice.
PHY_GATELVL_INIT_RATIO_1_CR
Table 1-134 • PHY_GATELVL_INIT_RATIO_1_CR
Bit
Number
Name
Reset
Value
Description
[31:16]
Reserved
0x0
Software should not rely on the value of a reserved
bit. To provide compatibility with future products, the
value of a reserved bit should be preserved across a
read-modify-write operation.
[15:0]
REG_PHY_GATELVL_INIT_RATIO
0x0
[15:0] of REG_PHY_GATELVL_INIT_RATIO
Lowest 11 bits are from data slice 0, next 11 bits are
for data slice 1, etc.
Revision 2
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