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The Table below summarises the available choices:
SCLK_G_DOMAIN
INTERNAL_SCLK_A
Function
True
True
FPGA drives common sample clock for both
channels
Ext CLK jumpers = not fitted
A/B jumper = fitted to A/B
True
False
External clock used for both channels
Ext CLK jumpers = fitted
A/B jumper = fitted to A/B
False
True
FPGA drives different sample clocks for each
channel
Ext CLK jumpers = not fitted
A/B jumper = fitted to B
False
False
External clock used for channel A, and the
FPGA drives the sample clock for Channel B
Ext CLK jumpers = fitted
A/B jumper = fitted to B
In the case of example1 the ADCs are not used, so the setting of these parameters is not
necessary.
4. DAC Clocks
The timing requirements of the DAC components inputs are not as strict as the ADC input
timings. Hence a DLL is never necessary, and so there are no items in the configuration
package regarding the DAC clocks.
User Timing Constraints
As with all FPGA designs it is necessary to apply some timing constraints to the design to
ensure that the tools generate a design that will operate at the frequency that you require.
Example1 has these defined in the .ucf file.
Although you can use the configuration package to set the frequency of the FIFO clocks to
be 50Mhz, you can still use the stricter timing constraints needed when those clocks run at
100Mhz. So in the case of example1 you do not need to change any of the timing
constraints. When you make changes to the design however you may find that you
introduce more clock nets that need to be added to the ucf file. In some cases you may find
that the tools are unable to achieve your desired clock frequency and then (if you are using
an HEPC8) you should change the constraints to reflect you true needs.
For more details on Timing Constraints please refer to the Xilinx tools documentation.
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HUNT ENGINEERING HERON-IO2 USER MANUAL