Download TDR Pattern Register User Manual - NPG
Transcript
GREAT 8d 8e 8f 90 91 92 93 94 95 96 97 98 – 9f A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Aa Ab Ac Ad Ae Af B0 14/1/2004 Irq5 Irq6 Irq7 Iackinn Iackoutn Sharc_clock Sharc_ack Sharc data0 Sharc data1 Sharc data2 Sharc data3 NYI Fifo pafn Fifo paen Fifo hfn Fifo ffn Fifo efn Fifo erclk Fifo erenn Fifo rclk Fifo rcsn Fifo renn Fifo oen Fifo prsn Fifo mrsn Fifo ready Fifo rdreq Vme req Lost track Interrupt line Interrupt line Interrupt line Interrupt cycle chain token in Interrupt cycle chain token out SHARC bus clock pulses. SHARC bus acknowledge SHARC data bit FIFO programmable almost full FIFO programmable almost empty FIFO Half empty FIFO full FIFO empty Fifo erclk ????? Fifo erenn ???? Fifo read clock Fifo read chip select Fifo read enable Fifo output enable Fifo partial reset Fifo master reset Fifo data has been read, and is ready for use Request from sharc software for a fifo read Request from vme for a read of fifo data Output of the track comparison system ? [email protected] 15