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Download Arria V Avalon-MM Interface for PCIe Solutions User Guide
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5-6 UG-01105_avmm 2014.12.15 Type 1 Configuration Space Registers Type 1 Configuration Space Registers Figure 5-2: Type 1 Configuration Space Registers (Root Ports) 31 24 23 Device ID Status 16 15 87 Vendor ID Command 0 0x0000 0x004 Class Code Revision ID 0x008 BIST Header Type Primary Latency Timer Cache Line Size 0x00C BAR Registers 0x010 BAR Registers 0x014 Primary Bus Number 0x018 Secondary Latency Timer Subordinate Bus Number Secondary Bus Number Secondary Status I/O Limit I/O Base 0x01C 0x020 Memory Limit Memory Base Prefetchable Memory Limit Prefetchable Memory Base 0x024 0x028 Prefetchable Base Upper 32 Bits 0x02C Prefetchable Limit Upper 32 Bits 0x030 I/O Limit Upper 16 Bits I/O Base Upper 16 Bits 0x034 Reserved Capabilities Pointer 0x038 Expansion ROM Base Address Bridge Control Interrupt Pin Interrupt Line 0x03C PCI Express Capability Structures Figure 5-3: MSI Capability Structure 31 0x050 0x054 0x058 0x05C Altera Corporation 24 23 16 15 Message Control Configuration MSI Control Status Next Cap Ptr Register Field Descriptions Message Address Message Upper Address Reserved 87 0 Capability ID Message Data Registers Send Feedback
