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REGISTER SET
ST10F269 USER’S MANUAL
22.2 - General Purpose Registers (GPRs)
The GPRs form the register bank that the CPU works with. This register bank may be located anywhere
within the internal RAM via the Context Pointer (CP). Due to the addressing mechanism, GPR banks can
only reside within the internal RAM. All GPRs are bit-addressable.
Table 54 : General purpose registers (GPRs)
Name
Physical
Address
8-bit
Address
R0
(CP) + 0
F0h
CPU General Purpose (word) Register R0
UUUUh
R1
(CP) + 2
F1h
CPU General Purpose (word) Register R1
UUUUh
R2
(CP) + 4
F2h
CPU General Purpose (word) Register R2
UUUUh
R3
(CP) + 6
F3h
CPU General Purpose (word) Register R3
UUUUh
R4
(CP) + 8
F4h
CPU General Purpose (word) Register R4
UUUUh
R5
(CP) + 10
F5h
CPU General Purpose (word) Register R5
UUUUh
R6
(CP) + 12
F6h
CPU General Purpose (word) Register R6
UUUUh
R7
(CP) + 14
F7h
CPU General Purpose (word) Register R7
UUUUh
R8
(CP) + 16
F8h
CPU General Purpose (word) Register R8
UUUUh
R9
(CP) + 18
F9h
CPU General Purpose (word) Register R9
UUUUh
R10
(CP) + 20
FAh
CPU General Purpose (word) Register R10
UUUUh
R11
(CP) + 22
FBh
CPU General Purpose (word) Register R11
UUUUh
R12
(CP) + 24
FCh
CPU General Purpose (word) Register R12
UUUUh
R13
(CP) + 26
FDh
CPU General Purpose (word) Register R13
UUUUh
R14
(CP) + 28
FEh
CPU General Purpose (word) Register R14
UUUUh
R15
(CP) + 30
FFh
CPU General Purpose (word) Register R15
UUUUh
Description
Reset
Value
The first 8 GPRs (R7...R0) may also be accessed byte wise. Other than with SFRs, writing to a GPR byte
does not affect the other byte of the respective GPR. The respective halves of the byte-accessible
registers receive special names:
Table 55 : General purpose registers (GPRs) bit wise addressing
Name
Physical
Address
8-bit
Address
RL0
(CP) + 0
F0h
CPU General Purpose (byte) Register RL0
UUh
RH0
(CP) + 1
F1h
CPU General Purpose (byte) Register RH0
UUh
RL1
(CP) + 2
F2h
CPU General Purpose (byte) Register RL1
UUh
RH1
(CP) + 3
F3h
CPU General Purpose (byte) Register RH1
UUh
RL2
(CP) + 4
F4h
CPU General Purpose (byte) Register RL2
UUh
RH2
(CP) + 5
F5h
CPU General Purpose (byte) Register RH2
UUh
RL3
(CP) + 6
F6h
CPU General Purpose (byte) Register RL3
UUh
RH3
(CP) + 7
F7h
CPU General Purpose (byte) Register RH3
UUh
Description
Reset
Value
RL4
(CP) + 8
F8h
CPU General Purpose (byte) Register RL4
UUh
RH4
(CP) + 9
F9h
CPU General Purpose (byte) Register RH4
UUh
RL5
(CP) + 10
FAh
CPU General Purpose (byte) Register RL5
UUh
RH5
(CP) + 11
FBh
CPU General Purpose (byte) Register RH5
UUh
RL6
(CP) + 12
FCh
CPU General Purpose (byte) Register RL6
UUh
RH6
(CP) + 13
FDh
CPU General Purpose (byte) Register RH6
UUh
RL7
(CP) + 14
FEh
CPU General Purpose (byte) Register RL7
UUh
RH7
(CP) + 15
FFh
CPU General Purpose (byte) Register RH7
UUh
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