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Download User Manual ST10F272
Transcript
Parallel ports UM0381 Figure 31. Block diagram of input section of a P1L pin Internal Bus Channel Select Analog Switch to Sample + Hold Circuit Read Port P1L.x P1L.x/ANy Clock XP1DIDIS.x Input Latch Read Buffer x = 7...0 y = 23 ...16 Figure 32. Block diagram of a PORT1 pin Write DP1H.y / DP1L.y “1” 1 MUX Direction Latch 0 Read DP1H.y / DP1L.y Alternate Function Enable Internal Bus Alternate Data Output Write P1H.y / P1L.y 1 Port Output Latch Port Data Output MUX Output Buffer 0 Read P1H.y / P1L.y P1H.y P1L.y XP1DIDIS.y Clock 1 MUX 0 6.4 Input Latch y = 7...0 Port2 If this 16-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP2. Each port line can be switched into push-pull or open drain mode via the open drain control register ODP2. 142/537
