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Download User Manual ST10F272
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UM0381 XBUS asynchronous / synchronous serial interface Figure 111. Synchronous mode of serial channel XASC Reload Register CPU Clock 2 S1R S1M = 000b S1REN S1OEN S1LB Output TDX0 P8.7 4 Baud Rate Timer S1OE Receive Interrupt Request Clock Serial Port Control Shift Clock Transmit Interrupt Request Error Interrupt Request Receive Input / Output RXD1 P8.6 0 1 Transmit MUX Receive Shift Register Transmit Shift Register Receive Buffer Register XS1RBUF Transmit Buffer Register XS1TBUF Internal X-Bus Synchronous transmission begins within 4 CPU clock cycles after data has been loaded into XS1TBUF, provided that S1R is set and S1REN = ‘0’ (half-duplex, no reception). Data transmission is double buffered. When the transmitter is idle, the transmit data loaded into XS1TBUF is immediately moved to the transmit shift register thus freeing XS1TBUF for the next data to be sent. This is indicated by the transmit buffer interrupt request flag being set. XS1TBUF may now be loaded with the next data, while transmission of the previous one is still going on. The data bits are transmitted synchronous with the shift clock. After the bit time for the 8th data bit, both pins TXD1 and RXD1 will go high, the transmit interrupt request flag is set, and serial data transmission stops. Pin TXD1/P8.7 must be configured for alternate data output, P8.7 = ’1’ and DP8.7 = ’1’, in order to provide the shift clock. Pin RXD1 / P8.6 must also be configured for output (P8.6 = ’1’ and DP8.6 = ’1’) during transmission. Synchronous reception is initiated by setting bit S1REN = ’1’. If bit S1R = 1, the data applied at pin RXD1 are clocked into the receive shift register synchronous to the clock which is output at pin TXD1. After the 8th bit has been shifted in, the content of the receive shift register is transferred to the receive data buffer XS1RBUF, the receive interrupt request flag is set, the receiver enable bit S1REN is reset, and serial data reception stops. Pin TXD1 / P8.7 must be configured for alternate data output, P8.7 = ’1’ and DP8.7 = ’1’, in order to provide the shift clock. Pin RXD1 / P8.6 must be configured as alternate data input (DP8.6 = ’0’). Synchronous reception is stopped by clearing bit S1REN. A currently received byte is completed including the generation of the receive interrupt request and an error interrupt request, if appropriate. Writing to the transmit buffer register while a reception is in progress has no effect on reception and will not start a transmission. 259/537
