Download UM10314 LPC3130/31 User manual

UM10314
NXP Semiconductors
Chapter 7: LPC3130/31 Internal Static RAM (ISRAM) memory controller
2.1.3 DMA transfers
The ISRAM module does not make use of flow control, but it is able to make use of DMA
via the DMA module.
3. Register overview
The latency configuration signal is programmed by software through the
SYSCREG_ISRAM0/1_LATENCY_CFG registers in the SysCReg block (see
Section 26–4.4).
4. Functional description
The CPU can read or write data from or to the RAM via the ISRAM module. The CPU will
address the ISRAM module, which will translate the incoming AHB address in a RAM
address. Based on this address the RAM will provide the ISRAM module with data, which
is stored on that address or will store data from the ISRAM module into the RAM. Then
the ISRAM module will transport the data read from the RAM to the CPU, in case of a read
operation, or transport data from the CPU to the RAM in case of a write operation.
By changing the latency through the memory controller less or more pipeline stages will
be added. The more pipeline stages are used, the higher the frequency is which can be
used, but the bigger the latency through the ISRAM module is.
5. Power optimization
This section describes the power optimization possibilities that are included in the ISRAM
module.
• Internal power consumption is minimized by extensive use of enable signals, thus
limiting the switching power dissipated. The user cannot influence this process.
• SRAM is designed to support the low power features of memory. According to the low
power use of memory specifications, the address, data, WEB and BSEL inputs to
memory remain still when no memory transfer is under progress. The user cannot
influence this process.
• When the memory is not used the addresses remain as still as much as possible.
• When memory is inactive, keep the CL input activated (CL = H) to prevent any
toggling on the address, DATA and BSEL inputs, from consuming any power within
the RAM.
• The CS input should be inactive (CS = L) to prevent the memory from being activated
and consuming any read or write power when clock is activated (CL transition L to H).
• The Write Enable (low-active) input should be placed in the read position (WEB = H)
when the RAM is not selected as this will stop any transition on the DATA and BSEL
inputs from consuming any power within the RAM.
• When the memory is not used the DATA and BSEL inputs should either remain stable
as much as is possible or the memory should be placed in the read mode (WEB = H)
or the memory should be placed in inactive mode with CL input activated (CL = H).
UM10314_1
User manual
© NXP B.V. 2009. All rights reserved.
Rev. 1 — 4 March 2009
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