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Download DLV11 -E and 0 LV11-F asynchronous line interface user's manual
Transcript
5.4.1 CSR Data Flow RCSR operation differs between the DLVII-E and DLVll-F only in those areas concerned with the peripheral interface requirements (Figures 5-6 and 5-7). Some bits are set by the peripheral interface circuit, receiver active circuit, and the RBUF, while others are set by the program via three-state bus lines DATOO H through DAT06 H. All RCSR bits except the DLVII-F's Reader Run Enable bit may be read by the program. Refer to Chapter 4 for a listing of how the bits are set and cleared. SOURCE RCSR ----PERIPHERAL INTERFACE CIRCUIT DATA SET INTERRUPT DAT15 H RING DAT14 H ,.----. CLEAR TO SEND DAT13 H r----- CARRIER DETECT DAT12 H reo RECEIVER ACTIVE OATH H SECONDARY RECEI VE DATlO H RECEIVER DONE DATO? H r-- rRECEIVER ACTIVE CIRCUIT RBUF DESTINATION ~ t-- DAT06 H - RECEIVER INTERRUPT ENABLE DAT05 H - DATA SET INTERRUPT ENABLE DAT03 H - SECONDARY TRANSMIT DAT02 H - REQUEST TO SEND DATOl H - DATA TERMINAL READY ~ L--. INTERRUPT LOGIC PERIPHERAL INTERFACE CIRCUIT 11-4916 Figure 5-6 DLVII-E RCSR Data Flow 5-8
