Download Texas Instruments SLAU081 User's Manual

 User’s Guide
January 2002
AAP Data Acquisition (Dallas)
SLAU081
IMPORTANT NOTICE
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Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright  2002, Texas Instruments Incorporated
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING
DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to
be fit for commercial use. As such, the goods being provided may not be complete in terms
of required design-, marketing-, and/or manufacturing-related protective considerations,
including product safety measures typically found in the end product incorporating the
goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may not meet the technical
requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide,
the kit may be returned within 30 days from the date of delivery for a full refund. THE
FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO
BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR
STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods.
Further, the user indemnifies TI from all claims arising from the handling or use of the
goods. Please be aware that the products received may not be regulatory compliant or
agency certified (FCC, UL, CE, etc.). Due to the open construction of the product, it is
the user’s responsibility to take any and all appropriate precautions with regard to
electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER
PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL,
INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement
with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions
notice in the EVM User’s Guide prior to handling the product. This notice contains
important safety information about temperatures and voltages. For further safety
concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory
practice standards.
No license is granted under any patent right or other intellectual property right of TI
covering or relating to any machine, process, or combination in which such TI products
or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright  2002, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of ±12 V and the output
voltage range of ±12 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
60°C. The EVM is designed to operate properly with certain components above 60°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright  2002, Texas Instruments Incorporated
Running Title—Attribute Reference
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
EVM Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1 Stand-Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.2 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Analog Input Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Analog Output Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Prototype Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
Shipping (Default Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.1 Analog I/O Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.2 Channel 0 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.3 Channel 0 Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.4 Signal Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.5 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.6 ADC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.7 Clock/Timer Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3.1 Stand-Alone-Mode, SW1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.4
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.5
ADC and DAC Direct Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.6
Host Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.6.1 Common Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.6.2 Legacy Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
A
Bill of Materials, Board Layout, and Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Chapter Title—Attribute Reference
1-1
1-2
1-3
1-3
1-3
1-3
1-3
v
Running Title—Attribute Reference
Figures
2–1
SAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Tables
2–1
2–2
2–3
vi
Default Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Default Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Jumper/Function Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Chapter 1
Introduction
This chapter contains an overview of the features and functions of the EVM.
Topic
Page
1.1
EVM Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
1.2
Analog Input Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
1.3
Analog Output Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
1.4
Prototype Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
1-1
EVM Modes
This user’s guide has been written to help you get the most from your
evaluation module (EVM). The TLC4541 EVM is a member of the
multipurpose (MP) family of serial EVMs. It provides a platform to demonstrate
the performance and functionality of the TLC4541 ADC and the
TLV5636 DAC.
TI’s websites are regularly updated. They present the latest software
additions, development information, troubleshooting help, general
background, as well as all applicable data sheets.
For specific questions related to this EVM or device send an email to the
Analog Applications Team at [email protected] and reference the
orderable tool description – TLC4541 EVM.
This user’s guide is divided into the following chapters:
- Chapter 1 offers an overview of the EVM and introduces the general
features and functions of the system.
- Chapter 2 describes the operation of the EVM from a user’s view. It details
options that can be modified, connectors used, and pinout details.
- Appendix A details the bill of materials (BOM) and the schematic, along
with explanations of certain EVM features.
1.1 EVM Modes
This EVM has been designed, tested, and shipped in a condition that enables
the user to begin evaluation with minimal effort.
There are basically two operating modes for the EVM. These modes are
mutually exclusive. They are:
- Stand-Alone Mode (SAM)
Stand-alone mode enables the user to check the system without the
support of a signal generator, pattern generator, or DSP. In this mode, the
digital output from the ADC is fed into the companion DAC and
reconstructed.
User mode is deselected if SAM is selected. The DSP will be unable to
communicate with either the ADC or the DAC.
- User Mode
The EVM typically operates via a DSP or a microprocessor. In this mode
the user is responsible for generating all the control signals. If user mode is
selected, SAM is deselected.
1-2
Analog Input Conditioning
1.1.1
Stand-Alone Mode
A unique feature of this EVM is the facility it offers the user to closely couple
the ADC and DAC with a minimum of user intervention. This feature allows the
serial bit stream from the digitized analog output to be fed directly to the DAC.
Therefore, the signal that is fed into the ADC can be reconstructed via the
DAC. No DSP need be present.
SAM is selected by:
- Switching SW1-1 to the on position, LED is on.
1.1.2
User Mode
The user can connect the ADC to a DSP or to a microprocessor in two ways:
- Via IDC ribbon cable
- Via daughterboard connectors J16 and J17
User mode is selected by:
- Switching SW1-1 to the off position, LED is off.
For example, TI’s range of DSP starter kits (DSK modules) provides a simple
low-cost solution, offering a range of DSK modules for most needs. The EVM
also supports the TMS320C6000 daughtercard specification (SPRA711), in
addition to providing support for the Motorola specification for data
transfer (SPI).
1.2 Analog Input Conditioning
There are a number of methods to connect analog input signals to the EVM.
Chapter 2 discusses these alternatives.
1.3 Analog Output Conditioning
There are a number of methods to connect analog output signals to the EVM.
Chapter 2 discusses these alternatives.
1.4 Prototype Area
An area of the PWB has been set aside if none of the signal conditioning
options provided are suitable.
The prototype area has the following features:
- A matrix of plated-through holes (PTH)
- SMT pads in a standard 14-pin JEDEC footprint
- Convenient points to pick up all power options
Introduction
1-3
Chapter 2
Getting Started
This chapter describes how the user can modify the various options of
this EVM.
Topic
Page
2.1
Shipping (Default Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.4
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.5
ADC and DAC Direct Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.6
Host Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Getting Started
2-1
Shipping (Default Configuration)
It is very important that users feel comfortable with the EVM from the
beginning. To achieve this, each unit is manufactured and shipped in a
predetermined condition. This allows the user to begin evaluation of the
system immediately and to have confidence that the EVM is working.
To confirm that the EVM is working properly, follow the steps below:
1)
2)
3)
4)
5)
6)
Apply power to the system. The green LED will illuminate.
Ensure stand-alone mode (SAM) LED is on.
Check TP7 via oscilloscope. This will be a sine wave.
Press the reset button SW3.
Press the start button SW2.
Check TP20 with an oscilloscope. If the system is working properly, the
signal at TP20 will also be a sine wave.
The system works as illustrated below. Any analog input supplied to the ADC
will be digitized and reconstructed by the DAC.
Figure 2–1. SAM Configuration
TP7
ADC
Data
Control
Electronics
DAC
DSP / Micro
Interface
Data
TP20
The user may probe the data and control signals to observe the signals that
allow stand-alone mode to function.
2.1 Shipping (Default Configuration)
The EVM is tested and shipped with jumpers and switches in a predetermined
arrangement. This arrangement enables users to verify at once that the EVM
is working. The tables below list switch and jumper settings that the EVM
should be set to upon receipt.
2-2
Shipping (Default Configuration)
Table 2–1. Default Switch Settings
Switch Settings
Default
Configuration
Description
SW1-1
On
Stand-alone mode is selected, LED is on
SW1-2
Off
Reserved
SW1-3
Off
Reserved
SW1-4
Off
Reserved
Table 2–2. Default Jumper Settings
Jumper Settings
Default Configuration
Description
Pins 1–2
Pins 2–3
W1
Inserted
Not inserted
Input for channel 0 is via BNC connector J1.
W2
Not inserted
Inserted
Sine wave test signal is selected for channel 0.
W3
Not inserted
Inserted
Sine wave test signal is output for channel 0.
W4
Not inserted
Inserted
Onboard conditioned input for channel 0 is selected.
W5
Not populated
Not populated
W6
Not populated
Not populated
W7
Not populated
Not populated
W8
Not populated
Not populated
W9
Not inserted
Disables onboard sine and triangle wave generator
W10
Inserted
Not inserted
SCLK routed to ADC
W11
Not inserted
Inserted
Signal conditioning output selected for channel 0
W12
Inserted
Not inserted
FS routed to ADC
W13
Not Inserted
W14
Inserted
W15
Not populated
5-V analog
EVM reference or DAC’s on-chip reference selected.
Not populated
W16
Inserted
Not inserted
Selects internal or external reference
W17
Inserted
Not inserted
Determines EVM reference voltage
W18
Not inserted
Inserted
FS routed to DAC
W19
Inserted
Not inserted
Selects source of signal conditioning output from DAC
W20
Not inserted
W21
Inserted
Not inserted
W22
Inserted
Not inserted
W23
Inserted
Not inserted
W24
Not inserted
W25
Not populated
These jumpers determine various options for supplying system
clock. This has been designed to be as flexible as possible
ossible to
accommodate many potential options.
Not populated
The hardware that can be reconfigured falls into one of the following sections:
- Jumpers
- Switches
- Connectors
Getting Started
2-3
Jumpers
2.2 Jumpers
The table below lists the functions that users can reconfigure along with the
shipping condition.
Table 2–3. Jumper/Function Reference
Function
Reference Designator
Subsection
Analog input
W1, W11, W4, W2, W3
3.2.3
Analog output
W14, W19, W18
3.2.4
Disable onboard signal generator
W9
3.2.7
Voltage reference
W16, W17
3.2.8
3.3-V/5-V analog supply select
W13
3.2.9
Clock/timer routing
W20, W21, W22, W23, W24
3.2.10
Channel 0
2.2.1
Analog I/O Signal Conditioning
The TLC4541 supports various signal conditioning configurations.
The user has the following options:
- Bypass signal conditioning
- Use the onboard signal conditioning. This consists of an operational
amplifier for each input channel configured with a gain of 1.
- Use the prototype area for signal conditioning.
- Use the expansion connector via a TI universal operational amplifier
evaluation module (such as SLOP224/SLOP249).
2.2.2
Channel 0 Analog Input
This is the primary analog input and can always be connected externally.
Analog Input Configuration Channel 0
Reference
Designator
2-4
Functional Description
W1
W1 allows the user to select between an analog input via BNC – J1 or IDC – J4 pin 1.
W11
W11 allows selection of either the conditioned or nonconditioned analog input signal.
W4
W4 allows the user to select either the prototype area output or the output from W11.
W2
W2 enables the user to select either the output from the expansion connector or the output
from the onboard signal generator.
W3
W3 completes the selection choices for channel 0 by determining if the output from W2 or W4
is chosen to be presented to the ADC.
Jumpers
2.2.3
Channel 0 Analog Output
With a one-channel DAC installed, this signal is the primary analog output
(output A).
With a two-channel DAC installed, the pinout of these devices effectively
resolves this channel to be the secondary analog output (output B).
Analog Input Configuration Channel 0
Reference
Designator
W19
Functional Description
This jumper selects the source for the analog output on channel 0.
When a jumper is installed between pins 1 and 2, the output from the expansion connector’s
B-channel is routed out.
When the jumper is installed between pins 2 and 3, the output from the onboard signal
conditioning is directed through channel 0.
2.2.4
Signal Generator
Signal Generator
Reference
Designator
W9
2.2.5
Functional Description
W9 controls the generation of both onboard test signals. A jumper installed between pins 1 and 2
disables the waveform generator.
Voltage Reference
Voltage Reference
Reference
Designator
Functional Description
W16
W16 selects either the onboard reference or an external reference supplied by the user.
W17
W17 allows the user to vary the reference voltage.
W14
There are a number of possible DACs that a user can install on this EVM. Some have an internal
reference that the user can select via software, and some do not have an internal reference. For
the DACs that support an internal reference, it is important to have the facility to remove the
external reference supplied by the EVM (or user) to avoid conflicts between the DAC’s internal
reference and the external reference.
2.2.6
ADC Supply Voltage
ADC Supply Voltage
Reference
Designator
W13
Functional Description
This jumper controls the analog supply voltage.
When the jumper is installed, the supply voltage to the ADC is 3.3 V.
When the jumper is not installed, the supply voltage to the ADC is 5 V.
Getting Started
2-5
Switches
2.2.7
Clock/Timer Routing
A variety of options are available to the user. Be careful about altering these.
Clock/Timer Routing
Reference
Designator
Functional Description
W21
This jumper defines the clock that the ADC and DAC use for all their timing. The user can select
either the output from W23 or the output from W22 to be the base clock for the system.
W23
This jumper allows the user to select either an external clock, or the onboard 20-MHz oscillator for
conversion. In addition, this signal is fed to W20.
W20
W20 provides a route for the EVM to generate CLKS for a DSP if so desired.
W22
This jumper enables the user to select either the transmit clock from a DSP, or the output
from W24.
W24
W24 connects or isolates the timer output from a DSP.
2.3 Switches
There are three switches present on the EVM:
- One 8-pin DIL switch which houses four individual switches; these are
denoted SW1-1, SW1-2, SW1-3, and SW1-4.
- Two momentary push-button switches
Features and functions of each switch:
2.3.1
Reference
Designator
Function
Default
Condition
SW1-1
Selects either stand-alone mode (SAM) or user mode
SAM
SW1-2
Reserved
SW1-3
Reserved
SW1-4
Reserved
Stand-Alone-Mode, SW1-1
SW1-1 chooses either stand-alone mode or user mode. If the switch is set to
the off position, SAM is selected and the EVM ignores all signals generated
by a DSP. In addition, the EVM will not output any signals to a DSP or
microprocessor.
In this mode, SW2 and SW3 are used to reset the EVM’s logic and initiate
automatic conversions from the ADC, in addition to automatically routing the
serial bit stream from the ADC to the DAC for reconstruction.
Reference
Designator
2-6
Function
SW2
Initiates ADC and DAC conversions in SAM
SW3
Forces the EVM’s control logic into a known state
Connectors
If SW1-1 is set to the on position, user mode is selected. In this case the user
has absolute control of the data and control signals for the ADC and DAC. With
SW1-1 in the on position, the logic that generates the control for SAM is
disabled and plays no active part in the process.
2.4 Connectors
In addition to jumpers and switches, the user also has access to various
connectors. This section details the pinout of each connector.
Reference
Designator
Description
J1
Analog input option for channel 0, miniature BNC
Cells in grey are not supported (tracked) directly by this EVM.
Reference
Designator
J3
Description
Analog
g input option
for universal
operational-amplifier
evaluation board, SIL
PTH not installed.
Pin
Number
Function
1
Noninverting input signal to dual operational amplifier, (2)
2
Noninverting input signal to dual operational amplifier, (2)
3
Inverting input signal to dual operational amplifier, (2)
4
Inverting input signal to dual operational amplifier, (2)
5
Nonfiltered output from dual operational amplifier, (2)
6
Filtered output from dual operational amplifier, (2)
7
+V supply
8
Operational amplifier (2) shutdown signal
9
Reference voltage
10
Analog ground
11
Operational amplifier (1) shutdown signal
12
–V supply
13
Nonfiltered output from dual operational amplifier, (1)
14
Filtered output from dual operational amplifier, (1)
15
Noninverting input signal to dual operational amplifier, (1)
16
Noninverting input signal to dual operational amplifier, (1)
17
Inverting input signal to dual operational amplifier, (1)
18
Inverting input signal to dual operational amplifier, (1)
Getting Started
2-7
Connectors
Reference
Designator
J4
Description
Analog
g input option,, 26-pin
DIL header
Pin
Number
1
Channel 0 input
2
AGND
3
Channel 1 input
4
AGND
5
Not connected
6
AGND
7
Not connected
8
AGND
9
Not connected
10
AGND
11
Not connected
12
AGND
13
Not connected
14
AGND
15
Not connected
16
AGND
17
Not connected
18
AGND
19
Not connected
20
AGND
21
Not connected
22
AGND
23
Not connected
24
AGND
25
External reference voltage
26
AGND
Reference
Designator
J5
2-8
Function
Description
Analog output for one-channel DAC
Connectors
Reference
Designator
J7
J8
Description
EVM power
Analog
g output option,,
26-pin DIL header
Pin
Number
Function
1
5V
2
–12 V
3
0V
4
12 V
1
No output
2
AGND
3
Analog output for one-channel DAC
4
AGND
5
Not connected
6
AGND
7
Not connected
8
AGND
9
Not connected
10
AGND
11
Not connected
12
AGND
13
Not connected
14
AGND
15
Not connected
16
AGND
17
Not connected
18
AGND
19
Not connected
20
AGND
21
Not connected
22
AGND
23
Not connected
24
AGND
25
Not connected
26
AGND
Getting Started
2-9
Connectors
Reference
Designator
J9
2-10
Description
Analog
g input option
for universal
operational-amplifier
evaluation board, SIL
PTH not installed.
Pin
Number
Function
1
Noninverting input signal to dual operational amplifier, (2)
2
Noninverting input signal to dual operational amplifier, (2)
3
Inverting input signal to dual operational amplifier, (2)
4
Inverting input signal to dual operational amplifier, (2)
5
Nonfiltered output from dual operational amplifier, (2)
6
Filtered output from dual operational amplifier, (2)
7
+V supply
8
Operational amplifier (2) shutdown signal
9
Reference voltage
10
Analog ground
11
Operational amplifier (1) shutdown signal
12
–V supply
13
Nonfiltered output from dual operational amplifier, (1)
14
Filtered output from dual operational amplifier, (1)
15
Noninverting input signal to dual operational amplifier, (1)
16
Noninverting input signal to dual operational amplifier, (1)
17
Inverting input signal to dual operational amplifier, (1)
18
Inverting input signal to dual operational amplifier, (1)
ADC and DAC Direct Access
2.5 ADC and DAC Direct Access
J10 and J11 offer users the facility to directly inspect the digital signals coming
from and going to the ADC and DAC.
Reference
Designator
J10
J11
Description
Allows the user direct access to all digital
g
signals
g
for the ADC
Allows the user direct access to all digital
g
signals
g
for the DAC
Pin
Number
Signal
1
Digital ground
2
SDO
3
Digital ground
4
SCLK
5
Digital ground
6
CS or CS/FS
7
Digital ground
8
FS
1
Digital ground
2
SDI
3
Digital ground
4
SCLK
5
Digital ground
6
CS
7
Digital ground
8
FS
2.6 Host Communication
There are two ways to connect a host system (DSP/microprocessor):
- Texas Instruments’ new DSKs provide two dedicated 80-pin connectors.
The EVM can be plugged directly onto these DSKs. This connector
standard is referred to as the common connector.
- Legacy DSKs not equipped with the 80-pin common connectors will
communicate via the daisy-chained legacy header.
The following sections discuss each connection method.
Getting Started
2-11
Host Communication
2.6.1
Common Connector
Reference
Designator
J16
2-12
Description
80-pin memoryy interface connector for ’C5000 and ’C6000 DSK
EVMs. Pins unused by this EVM are omitted for clarity.
Pin
Number
Function
1
5V
2
5V
11
PCI ground
12
PCI ground
21
5V
22
5V
29
PCI ground
30
PCI ground
31
PCI ground
32
PCI ground
41
3.3 V
42
3.3 V
51
PCI ground
52
PCI ground
61
PCI ground
62
PCI ground
71
PCI ground
72
PCI ground
79
PCI ground
80
PCI ground
Host Communication
Reference
Designator
J17
Description
80-pin peripheral and control connector for ’C5000 and ’C6000
DSK EVMs. Pins unused by this EVM are omitted for clarity.
Pin
Number
Function
1
12 V
2
–12 V
3
PCI ground
4
PCI ground
5
5V
6
5V
7
PCI ground
8
PCI ground
9
5V
10
5V
35
FSX
33
CLKX
36
DX
25
PCI ground
26
PCI ground
39
CLKR
41
FSR
42
DR
31
PCI ground
32
PCI ground
37
PCI ground
38
PCI ground
43
PCI ground
44
PCI ground
45
TOUT
49
XF
51
PCI ground
52
PCI ground
61
PCI ground
62
PCI ground
76
PCI ground
77
PCI ground
79
PCI ground
80
PCI ground
Getting Started
2-13
Host Communication
2.6.2
Legacy Connector
J12, J13, and J15 are three 2x20 headers daisy-chained together and are
collectively referred to as the legacy connector. The principle behind this
arrangement is to eliminate the confused and untidy custom cabling that is
typically present when connecting a legacy DSP to an EVM. This
daisy-chained connector method is flexible, robust, and makes it possible to
use a standard flat signal-cable assembly, improving reliability of
communications between host and EVM.
Two shorting bars are inserted in J12 and J15; these bars permit alternate pins
on J13 to be DGND. If the user has complete discretion over signal routing at
the host end, it is recommended that the host-end connector should reflect the
same pinout as J13.
However, if the host-end connector does not (or cannot) mirror the pinout for
J13, then some degree of signal-twisting is necessary. This is accomplished
on the EVM by removing the shorting bars on J12 and J15 and typically
wire-wrapping directly onto the appropriate header.
For example, if the host connector on the DSP has the pin assignment
described in the following table, then a 1:1 mapping is possible and the user
should plug a flat 20-way ribbon cable into J13.
Host Connector
EVM Connector – J13
Pin No.
Signal
Pin No.
Signal
Pin No.
Signal
Pin No.
Signal
1
XF
2
DGND
1
XF
2
DGND
3
CLKX
4
DGND
3
CLKX
4
DGND
5
CLKR
6
DGND
5
CLKR
6
DGND
7
DX
8
DGND
7
DX
8
DGND
9
DR
10
DGND
9
DR
10
DGND
11
FSX
12
DGND
11
FSX
12
DGND
13
FSR
14
DGND
13
FSR
14
DGND
15
Resvd
16
DGND
15
Resvd
16
DGND
17
CLKS
18
DGND
17
CLKS
18
DGND
19
TOUT
20
DGND
19
TOUT
20
DGND
However, if the host connector has a different signal pinout, the user should
remove the shorting bars from J12 and J15. A flat 20-way IDC ribbon cable can
still be used; in this case, the user should plug the connector into J12 of the
EVM. Since the cable is now plugged into J12, and all the signals on both sides
of the J12 pins are routed to adjacent connector pins (J13 and J15), the user
can typically wire-wrap the associated host signal to the relevant EVM signal.
The example shown below demonstrates the steps that must be taken to
reassign the connector and wire-wrap the correct signals.
2-14
Host Communication
Consider a host cable signal assignment as shown below:
Host Connector
Pin No.
Signal
Pin No.
Signal
1
NA
2
DGND
3
NA
4
DGND
5
CLKX
6
CLKR
7
TOUT
8
DGND
9
DX
10
DR
11
FSX
12
FSR
13
NA
14
DGND
15
XF
16
DGND
17
NA
18
NA
19
NA
20
CLKS
The host connector mates with J12. Signals on either side of J12 are available
on J13 and J15.
J13
Host Connector Plugged into J12
J15
Pin No.
Pin No.
Signal
Pin No.
Signal
Pin No.
2
1
N/A
2
DGND
1
4
3
N/A
4
DGND
3
6
5
CLKX
6
CLKR
5
8
7
TOUT
8
DGND
7
10
9
DX
10
DR
9
12
11
FSX
12
FSR
11
14
13
N/A
14
DGND
13
16
15
XF
16
DGND
15
18
17
N/A
18
N/A
17
20
19
N/A
20
CLKS
19
Getting Started
2-15
Host Communication
For clarity, the above table can be redrawn with J12 removed.
J13
J15
Pin No.
Signal
Pin No.
Signal
2
NA
1
DGND
4
NA
3
DGND
6
CLKX
5
CLKR
8
TOUT
7
DGND
10
DX
9
DR
12
FSX
11
FSR
14
NA
13
DGND
16
XF
15
DGND
18
NA
17
NA
20
NA
19
CLKS
The table below shows the signal names and pin assignments that the
composite connector shown above must be mapped onto.
J13
2-16
Pin No.
Signal
1
XF
3
CLKX
5
CLKR
7
DX
9
DR
11
FSX
13
FSR
15
Resvd
17
CLKS
19
TOUT
Host Communication
All of the signals required to interface the EVM to the host are now available
on either J13 or J15. This is simply a matter of wire-wrapping in the following
way:
Wire Wrap
J13
Pin No.
Signal
2
NA
4
NA
6
J13
Pin No.
Signal
CLKX
3
CLKX
8
TOUT
19
TOUT
10
DX
7
DX
12
FSX
11
FSX
14
NA
16
XF
1
XF
18
NA
20
NA
Wire Wrap
J15
J13
Pin No.
Signal
Pin No.
1
DGND
3
DGND
5
CLKR
7
DGND
9
DR
YES
9
11
FSR
YES
13
13
DGND
15
DGND
17
NA
19
CLKS
YES
5
Signal
Jumper
Between
B
t
Pin No.
Signal
YES
2
DGND
YES
4
DGND
6
DGND
8
DGND
DR
10
DGND
FSR
12
DGND
YES
14
DGND
YES
16
DGND
18
DGND
20
DGND
CLKR
YES
YES
17
J15
CLKS
Getting Started
2-17
Host Communication
All of these connectors are shown below:
Reference
Designator
J12
2-18
Description
20-pin connector
Pin
Number
Signal Name/Function
1
J13 pin 2
2
J15 pin 1
3
J13 pin 4
4
J15 pin 3
5
J13 pin 6
6
J15 pin 5
7
J13 pin 8
8
J15 pin 7
9
J13 pin 10
10
J15 pin 9
11
J13 pin 12
12
J15 pin 11
13
J13 pin 14
14
J15 pin 13
15
J13 pin 16
16
J15 pin 15
17
J13 pin 18
18
J15 pin 17
19
J13 pin 20
20
J15 pin 19
Host Communication
Reference
Designator
J13
Description
20-pin signal connector
Pin
Number
Signal Name/Function
1
ADC select signal
2
J12 pin 1
3
CLKX/transmit clock
4
J12 pin 3
5
CLKR receive clock
6
J12 pin 5
7
DX/data transmit
8
J12 pin 7
9
DR/data receive
10
J12 pin 9
11
FSX/frame sync transmit
12
J12 pin 11
13
FSR/frame sync receive
14
J12 pin 13
15
Reserved
16
J12 pin 15
17
CLKS/sync clock
18
J12 pin 17
19
TOUT/host timer output
20
J12 pin 19
Getting Started
2-19
Host Communication
Reference
Designator
J15
2-20
Description
20-Pin connector
Pin
Number
Signal Name/Function
1
J12 pin 2
2
DGND
3
J12 pin 4
4
DGND
5
J12 pin 6
6
DGND
7
J12 pin 8
8
DGND
9
J12 pin 10
10
DGND
11
J12 pin 12
12
DGND
13
J12 pin 14
14
DGND
15
J12 pin 16
16
DGND
17
J12 pin 18
18
DGND
19
J12 pin 20
20
DGND
Appendix A
Bill of Materials, Board Layout, and
Schematics
This appendix contains the bill of materials, board layouts, and the EVM
schematics.
Bill of Materials, Board Layout, and Schematics
A-1
1
2
3
4
5HYLVLRQ+LVWRU\
5(9
(&11XPEHU
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Input Config
D
ADC
J1
Interface
BNC_0
ADC_Data_out
D
User connectors
DSP_CLKS
ADC_Data_out
DSP_TOUT
DSP_CLKS
DSP_TOUT
J2
BNC_1
SENSE
SENSE
VREFP
VREFP
FS
J4
2
4
6
8
10
12
14
16
18
20
22
24
26
C
LCL_CS_ADC*
1
3
5
7
9
11
13
15
17
19
21
23
25
IDC_0
IDC_1
DSP_FSX
DSP_FSX
DSP_FSR
LCL_CS_ADC*
DSP_FSR
LCL_CLKX
FS
LCL_CLKX
DSP_DX
DSP_DX
DSP_DR
DSP_DR
DSP_XF
DSP_XF
C
Channel_0
In_0
Channel_1
In_1
B
DSP_CLKX
DSP_CLKR
DAC
LCL_CLKX
J8
2
4
6
8
10
12
14
16
18
20
22
24
26
DSP_CLKX
DSP_CLKR
1
3
5
7
9
11
13
15
17
19
21
23
25
LCL_CS_DAC*
J6
LCL_CS_DAC*
DAC_Data_in
DAC_Data_in
DAC_Write*
DAC_Write*
PCI_+5v
VREFP
PCI_+12V
J5
AOUT
B
PCI_GND
PCI_-12V
AOUT_A
Power & Reference
J7
4
+Supply
3
Ground
EXT_VREFP
VREFP
VREFP
+Supply
SENSE
SENSE
PCI_+5v
Ground
PCI_+12V
2
-Supply
-Supply
PCI_GND
12500 TI Boulevard. Dallas, Texas 75243
A
1
+5V_IN
PCI_-12V
Block Diagram
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$SSURYHG
040500
D
Power
FL2
1
+Supply
3
+VIN
+Vs
+ C11
10uF
R70
+ C57
10uF
2
PCI_+12V
+VS
0
GND
FL3
1
Ground
REF_IN
R68
2
PCI_GND
3
0
C
GND
GND
C
FL4
3
-VIN
-Vs
R69
C10
10uF
2
+
0
+
PCI_-12V
-VS
1
-Supply
C56
10uF
GND
+DVdd
FB13
+5V_IN
+DVdd
+DVdd
SM_FB_27--044447
PCI_+5v
R58
0
Reference
B
B
+VIN
SENSE
1
FL1
3
VREFP
VREFP
EXT_REFP
2
EXT_VREFP
SENSE
12500 TI Boulevard. Dallas, Texas 75243
A
A
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Power & Reference
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DOCUMENT CONTROL #:
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Power & Reference
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TP16
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040500
+DVdd
+DVdd
D2
D
C51 +
C53
4.7uF
C50
C58
0.1uF
0.01uF
C59 +
0.1uF
D
C44 +
10uF
10uF
TP18
TP12
FB3
C
C
+Vs
BLM11A121SGPB
U6
TPS77801D
3
4
+VIN
+
+
C25
10uF
B
2
D1
Green
C26
4.7uF
R17
1K
C27
0.1uF
R18
20K
IN
IN
PG
/ENA
OUT
OUT
8
GND
SENSE / FB
+AVdd
BLM11A121SGPB
R63
357K
1
TP9
FB2
6
5
7
R24
590K
C24 +
+
C31
4.7uF
C34
0.1uF
C28
4.7uF
C29
C42 +
0.1uF
0.01uF
C20 +
10uF
10uF
B
REF_IN
R14
0
W13
R62
0
TP11
R64
110K
FB1
-VIN
TP13
-Vs
+
A
C33
10uF
BLM11A121SGPB
12500 TI Boulevard. Dallas, Texas 75243
A
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R25
Not Installed
D
D
+Vs
7
C46
0.1uF
TLE2081
1
C
2.2uF
NR
3
VRE3050
Vout
TRIM
W17
RV9
10k
R20
0
4
8
GND
C30 +
+Vin
REF GND
2
+VIN
Temp
U7
6
5
+In
Vout
V-
3
Trim
Trim
-In
V+
U11
2
SENSE
C
R23
0
RV10
100K
6
5
RV7
10k
R66
4k
-Vs
C45
R50
TP10
W16
R29
10K
5K
VREFP
B
4
7
0.1uF
+ C38
R65
6k
B
2.2uF
EXT_REFP
R67
10K
12500 TI Boulevard. Dallas, Texas 75243
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Reference
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2
3
4
2
+AVdd
040500
5HYLVLRQ+LVWRU\
5(9
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C22
0.1uF
D
D
C19
C47
0.01uF
10uF
6
2
SENSE
ADC_REF
3
ADC_REF
R19
0
U501
AIN0
4
AIN1
5
8
MSOP ADC
6
C14
0.1uF
2
C23
10uF
3
VREFP
+DVdd
AIN0
In_0
4
1
CS* or CS*/FS
8
C1
100pF
J10
1
FS or SCLK
SCLK or AIN1 or AIN(-)
SDO
7
5
R10
10K
AIN or AIN0 or AIN(+)
SOCKETED ADC
AIN1
U5
7
AGND
VDD
C
Vref
C
1
3
5
7
B
In_1
2
4
6
8
ADC_Data_out
LCL_CLKX
B
W10
LCL_CS_ADC*
FS
W12
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2
D
DAC Out
C43
DAC_OUT
0.1uF
(&11XPEHU
C21
0.1uF
D
C41
OUT/OUTB
$SSURYHG
040500
VREFP
R54
10K
10uF
W14
REF
J9
AOUT
W19
V2+
7
TP20
6
8
U8
REF
C
9
12
Vcc
V2-
C32
0.1uF
-VS
5
VREF2
R55
10K
10
AGND
GND
C
+VS
B2/SD
B201B
6
B202B2_FLT
B203+
5
B2_OUT
B204+
1
CS*
SCLK
DAC_Data_in
LCL_CLKX
11
2
3
18
U801
7
8
DAC SOP(D)
J11
1
3
5
7
1
4
2
4
6
8
B
3
4
A2/SD
DIN
SOCKETED DAC
FS/OUTA
REF
+AVdd
17
5
A201-
16
OUT/OUTB
4
A202-
7
6
A203+
A2_OUT
15
8
A204+
2
13
A2_FLT
3
14
2
LCL_CS_DAC*
1
DAC_Write*
AOUT_A
W15
DAC Out
TP21
OUTA
W18
DAC_OUTA
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R33
5(9
2
(&11XPEHU
$SSURYHG
040500
0
RV11
100K
D
C49
0.1uF
R32
0
R30
D
V-
1
4
0
R35
6
DAC_OUTA
+In
3
OUTA
Trim
TLE2081
Trim
5
U12
Vout
V+
4.7K
-In
2
R31
NI
7
C52
C
C
C48
+Vs
0.1uF
R34
0
-Vs
R51
5K
RV8
100K
R28
0
R27
0
C39
0.1uF
B
R26
6
3
OUT/OUTB
Trim
U9
DAC_OUT
+In
Trim
5
V-
1
4
B
Vout
V+
4.7K
-In
2
R22
NI
7
C36
C40
A
0.1uF
12500 TI Boulevard. Dallas, Texas 75243
+Vs
A
TITLE:
DAC Output
Engineer:
R21
Joe Purvis
DOCUMENT CONTROL #:
0
1
2
FILE:
3
Joe Purvis
Output conditioning
REV:
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SIZE:
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A4
SHEET:
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OF:
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1
2
3
4
5HYLVLRQ+LVWRU\
5(9
Memory Interface Connector
FB12
DSP_CLKX
+5v
FB11
DSP_CLKR
+3.3v
FSX
FB4
FSR
BLM11A121SGPB
FB6
DX
DSP_DX
BLM11A121SGPB
FB7
DR
DSP_DR
BLM11A121SGPB
FB9
XF
DSP_XF
BLM11A121SGPB
FB10
TOUT
DSP_TOUT
BLM11A121SGPB
FB8
CLKS
DSP_CLKS
BLM11A121SGPB
B
J13
XF
CLKX
CLKR
DX
DR
FSX
FSR
A
CLKS
TOUT
1
3
5
7
9
11
13
15
17
19
J12
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
+5v
D
BLM11A121SGPB
C
$SSURYHG
PCI_-12V
FB5
DSP_FSR
(&11XPEHU
040500
CLKR
BLM11A121SGPB
DSP_FSX
F
CLKX
BLM11A121SGPB
D
Peripheral & Control Connector
1
3
5
7
9
11
13
15
17
19
+3.3v
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
PCI_+12V
PCI_+5V
CLKX
FSX
CLKR
FSR
TOUT
XF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
J16
J15
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
2
4
6
8
10
12
14
16
18
20
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
CLKS
DX
C
DR
B
J17
PCI_GND
12500 TI Boulevard. Dallas, Texas 75243
A
TITLE:
User Connectors
Engineer:
Joe Purvis
DOCUMENT CONTROL #:
FILE:
1
2
3
Joe Purvis
User connectors
REV:
6430333
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SIZE:
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OF:
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1
2
3
4
5HYLVLRQ+LVWRU\
5(9
(&11XPEHU
$SSURYHG
TO / FROM USER
CONNECTIONS
DSP_TOUT
DSP_TOUT
D
SYSCLK
DSP_CLKS
DSP_CLKS
D
EVM_CLKX
+DVdd
DSP_CLKX
DSP_CLKX
DSP_FSR
DSP_CLKR
DSP_CLKR
X1
8
DSP_DX
DSP_DX
C64
0.01uF
DSP_DR
DSP_DR
DSP_FSX
DSP_FSX
C65
0.1uF
4
VCC
OE
1
R40
DSP_FSX
33
GND
OUT
SYSCLK
5
W24
DSP_TOUT
W22
DSP_FSR
DSP_FSR
DSP_XF
DSP_XF
33
C
SYSCLK
SYSCLK
FS
W21
R45
DSP_CLKX
Stand Alone Mode
FS
EVM_CLKX
EVM_CLKX
R71
33
DSP_CLKR
W20
R43
DSP_CLKS
C
33
LCL_CS_ADC*
LCL_CS_ADC*
R44
DSP_XF
DSP_XF
LCL_CLKX
LCL_CLKX
DSP_FSX
DSP_FSX
W23
33
+DVdd
J14
R6
DSP_DX
DSP_DX
1K
MOM*
MOM
B
DAC_Data_in
LCL_CS_DAC*
R57
DAC_Write*
R37
SAM*
SAM*
R38
430
R56
430
DAC_Write*
B
+DVdd
DAC_Data_in
LCL_CS_DAC*
D5
+DVdd
DAC_Type
DAC_Type
R46
49.9K
R11
1K
3
TO / FROM ADC
430
DSP_DR
DSP_DR
1K
In
ADC_Data_out
D4
Out
ADC_Data_out
6
TO DAC
SW1C
2
D3
In
SW1A
7
5
A
Out
1
In
SW1D
In Out
Out
4
SW1B
12500 TI Boulevard. Dallas, Texas 75243
A
TITLE:
8
Digital Interface
Engineer:
Joe Purvis
DOCUMENT CONTROL #:
FILE:
1
2
3
Joe Purvis
Digital
Interface
EVM-0309R2.DDB
REV:
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SIZE:
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2
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4
5HYLVLRQ+LVWRU\
U16B
14
U13A
+DVdd
GND
DSP_DR
28
Vcc
C63
0.1uF
D
LCL_CS_ADC*
DSP_DR
17
MOM
18
ADC_CS*
19
DAC_Data_in 20
DAC_Data_in
TP15
21
U13B
+DVdd
14
GND
28
Vcc
C55
0.1uF
Q0
23
Q1
24
Q2
25
Q3
26
INIT*
27
U14B
5(9
I12/O0/Q0
I11
I13/O1/Q1
I10
I14/O2/Q2
I9
I15/O3/Q3
I8
I16/O4/Q4
I7
I17/O5/Q5
I6
I18/O6/Q6
I5
I19/O7/Q7
I4
I20/O8/Q8
I3
I21/O9/Q9
I2
+DVdd
14
GND
I1
TP14
28
Vcc
C
1
8
15
22
C54
0.1uF
NC
NC
NC
NC
(&11XPEHU
$SSURYHG
16
CLK/I0
13
ADC_Data_n3
12
ADC_Data_out
MOM
11
DSP_DX
EVM_CLKX
10
ADC_TC*
SYSCLK
9
START*
DSP_FSX
7
SAM*
DSP_DX
6
DAC_Type
DSP_XF
5
DSP_FSX
SAM*
4
DSP_XF
DAC_Type
3
RESET
ADC_Data_out
2
SYSCLK
START*
D
MOM
EVM_CLKX
SYSCLK
DSP_FSX
DSP_DX
DSP_XF
+DVdd
SAM*
R39
10K
DAC_Type
ADC_Data_out
C
START
+DVdd
SW2
U10
U16A
U14A
RESET
17
FS
TP19
18
19
LCL_CS_DAC*
20
LCL_CLKX
ADC_Data_n3
B
21
23
24
25
26
ADC_Data_out
TP17
27
I12/O0/Q0
I11
I13/O1/Q1
I10
I14/O2/Q2
I9
I15/O3/Q3
I8
I16/O4/Q4
I7
I17/O5/Q5
I6
I18/O6/Q6
I5
I19/O7/Q7
I4
I20/O8/Q8
I3
I21/O9/Q9
I2
I1
1
8
15
22
NC
NC
NC
NC
CLK/I0
ADC_TC*
16
17
13
Q0
18
12
Q1
19
11
Q2
20
10
Q3
21
9
MOM
23
7
DAC_Type
24
6
EVM_CLKX
25
5
DSP_FSX
26
4
DSP_XF
27
3
RESET
2
SYSCLK
I12/O0/Q0
I11
I13/O1/Q1
I10
I14/O2/Q2
I9
I15/O3/Q3
I8
I16/O4/Q4
I7
I17/O5/Q5
I6
I18/O6/Q6
I5
I19/O7/Q7
I4
I20/O8/Q8
I3
I21/O9/Q9
I2
I1
1
8
15
22
NC
NC
NC
NC
CLK/I0
3
16
13
Q0
12
Q1
11
10
OUT
RESET
+DVdd
DISCH
8
Q2
5
C60
0.1uF
Q3
C62 1
9
7
DAC_Type
6
INIT*
5
DSP_FSX
4
DSP_XF
3
RESET
2
SYSCLK
R42
10K
4
7
C61
VCC
THRES
6
R41
10K
CONT
TRIG
2
B
GND
NE555D
RESET
SW3
12500 TI Boulevard. Dallas, Texas 75243
A
A
TITLE:
Stand Alone
DAC_Write*
Engineer:
Joe Purvis
DOCUMENT CONTROL #:
FILE:
1
2
3
Joe Purvis
Stand Alone Mode
REV:
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SIZE:
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5HYLVLRQ+LVWRU\
5(9
2
Signal Conditioning
(&11XPEHU
$SSURYHG
040500
Prototype Area
D
D
IN_0
OUT_0
BB_Output_0
W4
IN_0
TP7
W3
R9
W11
BNC_0
33
W1
Channel_0
C8
6800pF
J3
1
2
3
IDC_0
4
C
8
11
18
BNC_1
17
16
W5
15
B204+
B2_OUT
B203+
B2_FLT
5
6
W2
B202-
Signal Generator
B201-
C
Test signal 0
B2/SD
A2/SD
Test signal 1
A201A202A2_OUT
W6
13
A203+
A204+
A2_FLT
14
+Vs
7
B
IDC_1
12
9
-Vs
10
V2+
W7
V2-
TP6
33
VREF2
B
R12
Channel_1
C9
6800pF
GND
Signal Conditioning
Prototype Area
OUT_1
BB_Output_1
W8
IN_1
IN_1
12500 TI Boulevard. Dallas, Texas 75243
A
A
TITLE:
W25
Input Configuration
Engineer:
Joe Purvis
DOCUMENT CONTROL #:
FILE:
1
2
3
Joe Purvis
Input configuration
REV:
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Drawn By:
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5HYLVLRQ+LVWRU\
5(9
2
+Vs
(&11XPEHU
$SSURYHG
040500
R8
D
D
4.7K
C6
C5
+
-Vs
0.1uF
10uF
TP5
C13
0.1uF
4
RV3
R5
U3
U4A
2
1
4.7K
Test Signal 0
3
R60
R72
5
49.9K
4
100K
V+
TLE2082D
8
6
Duty adj.
+Vs
Duty Adj.
Sine Out
2
49.9K
C
+Vs
12
1
10
8
W9
7
C17
RV4
Sine Adj
10K
Sine Adj
Square Out
14
13
11
R7
4.7K
-Vs
FM Sweep Input
FM Bias
C
4.7K
C7
0.1uF
9
Timing Cap.
Triangle Out
1nF
C12
0.1uF
R59
3
Not Connected
Not connected
R61
V- / GND
4.7K
TP8
B
B
RV6
ICL8038
R16
U4B
6
7
4.7K
Test Signal 1
5
100K
C18
10uF
C15
0.1uF
TLE2082D
+Vs
+
RV5
R13
-Vs
10K
4.7K
C16
0.1uF
A
R15
4.7K
12500 TI Boulevard. Dallas, Texas 75243
A
TITLE:
Signal Generator
-Vs
Engineer:
Joe Purvis
DOCUMENT CONTROL #:
FILE:
1
2
3
Joe Purvis
Signal Generator
REV:
6430333
Drawn By:
DATE:
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A4
SHEET:
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OF:
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1
2
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5HYLVLRQ+LVWRU\
5(9
2
(&11XPEHU
$SSURYHG
040500
D
D
TP1
TP2
IN_0
BB_Output_0
C
C
IN_1
BB_Output_1
TP3
TP4
PT1
1
14
2
13
3
12
4
11
5
10
6
9
7
8
B
B
12500 TI Boulevard. Dallas, Texas 75243
A
A
TITLE:
Prototype Area
Engineer:
Joe Purvis
DOCUMENT CONTROL #:
FILE:
1
2
3
Joe Purvis
Prototype Area
REV:
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Drawn By:
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2
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5HYLVLRQ+LVWRU\
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F
D
R3
R4
NI
0
(&11XPEHU
$SSURYHG
040500
D
+Vs
-In
U2
TLE2081
+In
6
OUT_1
C
5
3
4
1
IN_1
Vout
V-
C
Trim
Trim
2
V+
7
C2
0.1uF
R36
0
C37
0.1uF
R47
0
RV2
100K
-Vs
R1
R2
NI
R52
0
+Vs
5K
C4
0.1uF
B
7
B
-In
U1
V+
2
6
OUT_0
5
+In
Vout
1
V-
3
IN_0
Trim
Trim
TLE2081
4
R48
0
R49
0
C3
0.1uF
A
RV1
100K
12500 TI Boulevard. Dallas, Texas 75243
Signal Conditioning
R53
Engineer:
5K
Drawn By:
FILE:
1
2
A
TITLE:
-Vs
3
Joe Purvis
Joe Purvis
Signal Conditioning
DOCUMENT CONTROL #:
REV:
6430333
DATE:
28-Nov-2001
SIZE:
4
A4
SHEET:
14
OF:
14