Download MiTAC 8399 User's Manual

SERVICE MANUAL FOR
8399
BY: Grass Ren
Repair Technology Research Department /EDVD
Aug.2004
8399 N/B Maintenance
Contents
1. Hardware Engineering Specification …………………………………………………………………..
1.1 Introduction ……………………………………………………………………………………………
1.2 Hardware Specification …………………………………………………………………………………
1.3 System Hardware Parts …………………………………………………………………………………
1.4 Other Functions …………………………………………………………………………………….….
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3. Definition & Location of Connectors / Switches
Setting ………………………………………………
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4. Definition & Location of Major Component …………………………………………………………..
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5. Pin Description of Major Component…………………………………………………………………..
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6. System Block Diagram ……………………………………………………….……………………….....
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2. System View & Disassembly…………………………………………………………………………….
2.1 System View…………………………………………………………………………………….………
2.2 System Disassembly …………………………………………………………………………………….
5.1 AMD Mobile Athlon 64 (ClawHammer) Processor
5.2 VIA K8N800 North Bridge
5.3 VIA VT8235CD South Bridge
7. Maintenance Diagnostics ………………………………………………………………………………..
7.1 Introduction ……………………………………………………………………………………………
7.2 Diagnostic Tool for Mini PCI Slot ………………………………………………………………………
7.3 Error code……………………………………………………………………………………….……..
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Contents
8. Trouble Shooting ……………………………………………………………………………………..…. 95
8.1 Base Work Condition …………………………………………………………………………………… 96
8.2 No Power ………………………………………………………………………………………………. 101
8.3 Battery Can not Be Charged …………………………………………………………………………….. 104
8.4 No Display ………………………………… …………………………………………………………... 106
8.5 External Monitor No Display ……………………………………………………………………………. 108
8.6 Memory Test Error …………………………………………………………………………………….. 110
8.7 Keyboard/Touch-pad Test Error ………………………………………………………………………... 112
8.8 USB Port Test error……………………………………………………………………………………... 114
8.9 Hard Disk Drive Test Error……………………………………………………………………………… 116
8.10 CD-ROM Test Error ………………………………………………………………………………….. 118
8.11 Audio Test Failure………………………………………………………………………………..….… 120
8.12 LAN Test Error ……………………………………………………………………………………….. 123
8.13 Modem Test Error…………… …………………………………………………………………..…… 125
8.14 Mini-PCI Test Error……….. ……… ……………………………………………………………….... 127
8.15 Card Bus&Reader Test Error…………………………………………………………………………... 129
8.16 TV Encoder Test Error ………………………………………………………………………………… 131
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9. Spare Parts List ………………………………………………………………………………….…..…...
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10. System Exploded View ……………………………………………………………………………...…..
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11. Circuit Diagram ………………………………………………………………………………………....
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12. Reference Material …………………………………………………………………………………..….
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1. Engineer Hardware Specification
1.1 Introduction
The 8399 motherboard would support the AMD K8 62W Dublin (32 bit) with 256KB L2 cache/ Hammer (64 bit)
with 1MB L2 cache with uPGA Package. This system is based on PCI architecture, which have standard hardware
peripheral interface. The power management complies with Advanced Configuration and Power Interface (ACPI)
1.0b. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can be
pop-up by pressing F2 at system start up or warm reset. System also provides icon LEDs to display system status,
such as AC/Battery Power, Battery, WIRELESS LAN status, CD-ROM, HDD, NUM LOCK, CAP LOCK, and
SCROLL LOCK status. It also equipped 6 USB2.0 ports.
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The memory subsystem supports 0MB on board; Expandable up to 1024MB Expandable with combination of
optional 128/256/512 MB memory 200-pin DDR 266/333/400 DRAM Memory Module x2, PC-2100/2700/3200
specification.
The “K8N800”chipset is a high performance, cost-effective and energy efficient solution for the implementation of
desktop personal computer systems with 8 / 16-bit 800 / 600 / 400 / 200MHz HyperTransport. CPU host interface
based on AMD K8 / ClawHammer. Processors. The K8N800 north bridge supports a high speed 8-bit 8x66 Mhz
Quad Data Transfer interconnect (V-Link) to the VT8235 South Bridge. These chips also contain a built-in bus-tobus bridge to allow simultaneous concurrent operations on each bus. Five levels (double words) of post write buffers
are included to allow for concurrent CPU and V-Link operation. For V-Link Host operation, forty-eight levels
(double words) of post write buffers and sixteen levels (double words) of prefetch buffers are included for
concurrent V-Link bus and DRAM / cache accesses. When combined, the V-Link host / Client controllers realize a
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Complete PCI sub-system and support enhanced PCI bus commands such as “ Master-Read-Line”, “memory-ReadMultiple” and “Memory-Write-Invalid” commands to minimize snoop overhead. In addition, advanced features are
supported such as snoop ahead, snoop filtering, L1 write-back forward to PCI master, and L1 write-back merged
with PCI post write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read
caching mechanisms are also implemented for further improvement of overall system performance.
The VT8235CD “V-Link Client Controller” is a highly integrated PCI /LPC controller. Its internal bus structure is
based on a 66 MHz PCI bus that provides 2x bandwidth compared to previous generation PCI bridge chips. The
VT8235CD also provides a 533 MB/sec bandwidth Host / Client V-Link interface with V-Link-PCI and V-LinkLPC controllers. It supports six PCI slots of arbitration and decoding for all integrated functions and LPC bus.
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To provide for the increasing number of multimedia applications, the AC97 CODEC VT1617/1617A is integrated
onto the motherboard
A full set of software drivers and utilities are available to allow advanced operating systems such as Windows XP
and Windows 2000 to take full advantage of the hardware capabilities such as bus mastering IDE, Plug & Play, and
Advance configuration and power interface(ACPI).
Following chapters will have more detail description for each individual sub-systems and functions.
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1.2 Hardware Specification(1)
CPU
AMD K8 62W Dublin (32 bit)/Hammer (64 bit) with uPGA Package
Thermal Ceiling 62W TDP
Core Logic
VIA K8N800 + VT8235CD
L2 Cache
256KB for Dublin / 1MB for Hammer
System BIOS
Inside 256 KB Flash EPROM (Include System BIOS and VGA BIOS)
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ACPI 1.0b; DMI 2.3.1 compliant
Plug & Play capability
OSD
Audio Volume Up/Down status, Brightness status, RF Antenna On/Off status, Display Status
Memory
0MB on board; Expandable up to 1024MB
Expandable with combination of optional 128/256/512 MB memory
200-pin DDR 333/400 DRAM Memory Module x2, PC-2700/3200 specification
ROM Driver
12.7mm Height
CD / DVD Rom Drive
Combo Drive
Super Combo Drive
HDD
2.5” (9.5 mm height): 40/60/80 GB; ATA 100/133 Support
Removable for Distributor
Display
15” XGA TFT Display; Resolution: 1024X768
Video Controller
VIA K8N800 integrated(64MB SMA)
Keyboard
19mm key pitch/ 3.0mm key stroke/ 307mm length
Windows Logo Key x 1; Application Key x 1
Pointing Device
Glide pad with 2x buttons and 2 direction scroll button
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1.2 Hardware Specification(2)
Continue to previous page
PCMCIA
Cardbus Controller: ENE CB1410
one type II slots CardBus / no ZV port support/ no wakeup from S3
Power switch: ENE CP-2211
Indicator
3 LEDs for Power/Battery/Charge status
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1 LED for Radio wave status Power LED (BTO: Wireless LAN only )
5 LEDs for HDD Access, ODD Access , Num lock, Cap lock and Scroll Lock
Audio System
Sound Blaster Pro compatible
AC97 V2.2 Codec
Built-in Mono Microphone
2X 2W Speakers
I/O Port
USB port (2.0, backward compatible with USB1.1) x 6
RJ-11 port x 1
RJ-45 port x 1
DC input x 1
VGA monitor port x1
Audio-out x 1
Mic-in x 1
S/W Volume Control
7-Pin S Video TV-Out x 1 (NTSC/PAL)
Communication
Built-in 56Kbps V.90 modem support ISN standard
Built-in 10/100 M based-T LAN
One Mini PCI slot and antenna reserved for wireless LAN
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1.2 Hardware Specification(3)
Continue to previous page
AC Adapter
Universal AC adapter 90W ; Input: 100-240V, 50/60Hz AC (support power on charge)
Battery
6/8 cell (2000/2200mAH,3.7V) Li-ion smart battery
Dimensions
335*280*30(min) , 335x280x42 (max)
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1.3 System Hardware Parts T
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1.3.1 Processor
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Weight
3.5kg (P)
Accessories
Power Cord, AC Adapter, RJ-11 Phone Cable (p),System Driver CD-Title
Architecture
Microsoft WHQL Designed for Windows XP
Options
128/256/512MB DDR RAM, AC Adapter w/o Power Cord, Battery, Notebook Carry Bag
The AMD K8 Hammer processor family is designed to support performance desktop and workstation applications. It
provides a high-performance HyperTransport. link to I/O, as well as a single 64-bit high-performance DDR memory
controller.
Compatible with Existing 32-bit Code Base
Including support for SSE, SSE2, MMXTM, 3DNow!TM, technology and all legacy x86 instructions
Runs existing operating systems and drivers
Local APIC on-chip
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AMD x86-64 Technology
AMD.s 64-bit x86 instruction set extensions
64-bit integer registers, 48-bit virtual addresses, 40-bit physical addresses
Eight new 64-bit integer registers (16 total)
Eight new 128-bit SSE/SSE2 registers (16 total)
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Integrated Memory Controller
Low-latency, high-bandwidth
72-bit DDR at 100, 133, 166 and 200MHz
HyperTransport. Technology to I/O Devices
Two 8-bit links each support 1600 mega-transfers (MT) per second or 1.6 Gbytes/s in each direction
Can be configured as single 16-bit link supporting 1600 MT/s or 3.2 Gbytes/s in each direction
64-Kbyte 2-way Associative ECC-Protected L1 Data Cache
Two 64-bit operations per cycle, 3-cycle latency
64-Kbyte 2-way Associative Parity-Protected L1 Instruction Cache
With advanced branch prediction
16-way Associative ECC-Protected L2 Cache
Exclusive cache architecture.storage in addition to L1 caches
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256 KB, 512 KB, and 1 MB options
Machine Check Architecture
Includes hardware scrubbing of major ECC-protected arrays
Power Management
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Multiple low-power states
System Management Mode (SMM)
ACPI 2.0 compliant, including support for processor performance states
Electrical Interfaces
HyperTransport. Technology: LVDS-like differential, unidirectional
DDR: SSTL_2 per JEDEC DDR specification
Clock, reset, and test signals also use DDR-like electrical specifications
Packaging
754-pin lidded micro PGA
1.27-mm pin pitch
29x29 row pin array
40mm x 40mm organic substrate
Organic C4 die attach
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1.3.2 K8N800 North Bridge
The “K8N800”chipset is a high performance, cost-effective and energy efficient solution for the implementation of
mobile personal computer systems with 8 / 16-bit 800 / 600 / 400 / 200 MHz HyperTransport. CPU host interface
based on AMD K8 / Claw Hammer processors.
Defines Highly Integrated Solutions for Performance PC Desktop Designs
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High performance North Bridge with HyperTransport. interface to AMD K8 CPU plus AGP 8x external bus
to external Graphics Controller plus high-speed V-Link interface to South Bridge.
Combines with VIA VT8235CD V-Link South Bridge for integrated LAN, Audio, ATA133 IDE, and 6
USB 2.0 ports
587 Ball Grid Array package with 35 x 35 mm body size, 1.27mm ball pitch
1.5V core, 0.15 u process
High Performance HyperTransport CPU Interface
Chipset support for AMD. K8 / ClawHammer. Processor
Processor interface via HyperTransport. Bus
Separate “transmit” and “receive” buses for no lost “bus turnaround” cycles
All transmit and receive signals use 2 pin low-voltage-swing differential signalling for high-reliability and
high speed
8 or 16-bit control / address / data transfer both directions
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800 / 600 / 400 / 200 MHz clock rates with “Double Data Rate”-style operation for 1600/1200/800/400
MT/s in both directions simultaneously (total 6.4GB/sec using 16-bit transfer mode)
Default 8-bit / 200 MHz operation on startup for high reliability with speedup to dual 16-bit, 800 MHz
operation (6.4 GB/sec total bandwidth) under software control (transmit and receive may be different widths
and / or speeds)
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Full Featured Accelerated Graphics Port (AGP) 8x Controller
Supports 533 MHz 8x, 266 MHz 4x, and 133 MHz 2x transfer modes for AD and SBA signaling
AGP v3.0 compliant with 8x transfer mode
Pseudo-synchronous with the host CPU bus with optimal skew control
Supports SideBand Addressing (SBA) mode (non-multiplexed address / data)
AGP pipelined split-transaction long-burst transfers up to 1GB/sec
Eight level read request queue
Four level posted-write request queue
Thirty-two level (quadwords) read data FIFO (256 bytes)
Sixteen level (quadwords) write data FIFO (128 bytes)
Intelligent request reordering for maximum AGP bus utilization
Supports Flush/Fence commands
Graphics Address Relocation Table (GART)
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One level TLB structure
Sixteen entry fully associative page table
LRU replacement scheme
Independent GART lookup control for host / AGP / PCI master accesses
Windows 95 OSR-2 VXD and integrated Windows 98 / 2000 / XP mini port driver support
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High Bandwidth 533 MB / Sec 8-bit V-Link Host Controller South Bridge Interface
Supports 66 MHz V-Link Host interface with total bandwidth of 533 MB/sec
Operates in 2x, 4x, and 8x modes
Full duplex commands with separate command / strobe for 4x / 2x mode, half-duplex for 8x mode
Request / Data split transaction
Configurable outstanding transaction queue for Host to V-Link Client accesses
Supports Defer / Defer-Reply transactions
Transaction assurance for V-Link Host to Client access eliminates V-Link Host-Client Retry cycles
Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer Latency
All V-Link transactions for both Host and Client have a consistent view of transaction data depth and buffer
size to avoid data overflow
Highly efficient V-Link arbitration with minimum overhead
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All V-Link transactions have predictable cycle length with known command / data duration
Integrated Graphics / Video Accelerator
Optimized Share Memory Architecture (SMA)
16 / 32 / 64 MB frame buffers using system memory
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Internal AGP 8x equivalent performance
Separate 128-bit data paths between north bridge and graphics core for pixel data flow and texture/command
access
Graphics engine clock up to 200MHz decoupled form memory clock
High quality DVD video playback
Internal hardware VGA controller with true-color / high-color sprite for hardware cursor implementation
128-bit 2D graphics engine
128-bit 3D graphics engine
Floating point triangle setup engine
Microsoft DirectX texture compression
4.5M triangles/second setup engine
400M texels/second bilinear fill rate
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Extensive Display Support
CRT display interface with 24-bit true-color RAMDAC up to 300MHz pixel rate with gamma correction
capability
DFP” flat panel interface supporting single-channel or dual-channel LVDS encoders
DVI” Flat Panel Monitor 12-bit DVI 1.0-compatible interface designed for use with external TMDS encoder
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AGP 8x / 4x functions muxed on DFP/DVI pins for optional external graphics controller upgrade module
Dedicated 12-bit interface to TV Encoder for NTSC or PAL TV display (may be optionally configured as
12-bit DVI 1.0 interface to external TMDS encoder for driving a Flat Panel Monitor)
DuoView+ Dual Image Capability
Direct Win98, WinME and WinXP multi-monitor, extended desktop support
Independent resolution and color depth for secondary desktop
Improved display flexibility with simultaneous LCD/CRT, CRT/DVI, CRT/TV, LCD/TV, DVI/TV
operation capability
CRT, LCD or TV refresh rates are independently programmable to allow optimum image quality
Enables different images on different displays simultaneously for true multitasking
Full Media capabilities on all displays
Support for CRT resolutions up to 1920x1440 and panel resolutions up to 1600x1200
Automatic panel power sequencing and VESA DPMS CRT power-down
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Built-in reference voltage generator and monitor sense circuits
I2C Serial Bus and DDC Monitor Communications for CRT Plug-and-Play configuration
Video Support
High quality 5-tap horizontal and 5-tap vertical scaler (up or down) for both horizontal and vertical scaling
(linear interpolation for horizontal and vertical p-scaling filtering for horizontal and vertical down-scaling)
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Color space conversion
Color enhancement (contrast, hue, saturation, brightness, and gamma correction)
Color and chroma key support
Hardware sub-picture blending
Bob / weave de-interlacing mode and advanced de-interlacing to improve video quality
Video gamma correction
PAL / NTSC TV output capability using external TV encoder
Support CCIR601 standard
MPEG-2/1 Video Decoder
MPEG-2 hardware slice layer, iDCT, and motion compensation for full speed DVD playback
2-D Hardware Acceleration Features
BitBLT 9bit block transfer) functions including alpha blts
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Text function
Bresenham line drawing / style line function
ROP3, 256 operation
Color expansion
Source and destination color keys
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Transparency mode
Window clipping
8, 16, and 32 bpp mode acceleration
3-D Hardware Acceleration Features
Microsoft DirectX 7.0 and 8.0 compatible
OpenGL driver available
Floating-point setup engine
Triangle rate up to 4.5-million triangles per second and Pixel rate up to 400 million pixels per second for 2
texture, depth test and alpha blending
8K Texture Cache
Microsoft DirectX Texture Compression (S3TC)
Flat and Gouraud shading
Hardware back-face culling
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16-bit, 32-bit Z test, and 24+8 Z+ Stencil test support
Z-Bias support
Stipple Test, Line-Pattern test, Text re-Transparence test, Alpha test support
Edge anti-aliasing support
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Two textures per pass
Tremendous Texture Format: 16/32 bpp ARGB, 1/2/4/8 bpp Luminance, 1/2/4/8 bpp Intensity, 1/2/4/8 bpp
Paletized (ARGB) , YUV 422/420 format
Texture sizes up to 2048x2048
High quality texture filter modes: Nearest, Linear, Bi-linear, Tri-linear, Anisotropic
LOD-Bias support
Vertex Fog and Fog Talbe
Specular Lighting
Alpha Blending
Bump mapping
High quality dithering
ROP2 support
Internal full 32-bit ARGB format for high rendering quality
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System balance to achieve high performance
Advanced System Power Management
Power down of SDRAM (CKE)
Independent clock stop controls for CPU, DDR SDRAM, VLINK interface, graphics engine (2D,3D, video,
display) and on-chip AGP bus
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Suspend power plane for preservation of memory data
Suspend-to-DRAM and self-refresh power down
Low-leakage I/O pads
ACPI 1.0B and PCI Bus Power Management 1.1 compliant
Full Software Support
Drivers for major operating system and APIs (windows 9x, Windows NT, Windows2000,Windows XP,
Direct3D, DirectDraw and DirectShow, OpenGL ICD for Windows 9x, NT, 2000, and XP)
Chipset and Video BIOS support (including all standard VESZA CRT display modes)
1.3.3 VIA VT8235CD BGA PCI-LPC/ISA South Bridge
The VT8235CD South Bridge is a high integration, high performance, power-efficient, and high compatibility
device that supports Intel and non-Intel based processor to V-Link bus bridge functionality to make a complete
Microsoft PC2001-compliant PCI/LPC system. The VT8235CD includes standard intelligent peripheral controllers:
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IEEE 802.3 compliant 10 / 100 Mbps PCI bus master Ethernet MAC with standard MII interface to external
PHYceiver.
Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel
commands. Dedicated FIFO coupled with scatter and gather master mode operation allows high
performance transfers between PCI and IDE devices. In addition to standard PIO and DMA mode operation,
the VT8235CD also supports the UltraDMA-133, 100, 66, and 33 standards to allow reliable data transfer at
rates up to 133 MB/sec. The IDE controller is SFF-8038i v1.0 and Microsoft Windows-family compliant.
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Universal Serial Bus controller that is USB v2.0 / 1.1 and Universal HCI v2.0 / 1.1 compliant. The
VT8235CD includes three root hubs with six function ports with integrated physical layer transceivers. The
USB controller allows hot plug and play and isochronous peripherals to be inserted into the system with
universal driver support. The controller also implements legacy keyboard and mouse support so that legacy
software can run transparently in a non-USB-aware operating system environment.
Keyboard controller with PS2 mouse support.
Real Time Clock with 256 byte extended CMOS. In addition to the standard ISA RTC functionality, the
integrated RTC also includes the date alarm, century field, and other enhancements for compatibility with
the ACPI standard.
Notebook-class power management functionality compliant with ACPI and legacy APM requirements.
Multiple sleep states (power-on suspend, suspend-to-DRAM, and suspend-to-Disk) are supported with
hardware automatic wake-up. Additional functionality includes event monitoring, CPU clock throttling and
stop (Intel processor protocol), PCI bus clock stop control, modular power, clock and leakage control,
hardware-based and software-based event handling, general purpose I/O, chip select and external SMI.
Full System Management Bus (SMBus) interface.
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Integrated bus-mastering dual full-duplex direct-sound AC97-link-compatible sound system.
Plug and Play controller that allows complete steer ability of all PCI interrupts and internal interrupts / DMA
channels to any interrupt channel. One additional steerable interrupt channel is provided to allow plug and
play and reconfigure ability of onboard peripherals for Windows family compliance.
The VT8235CD also enhances the functionality of the standard ISA peripherals. The integrated interrupt controller
supports both edge and level triggered interrupts channel by channel. The integrated DMA controller supports type F
DMA in addition to standard ISADMA modes. Compliant with the PCI-2.2 specification, the VT8235CD supports
delayed transactions and remote power management so that slower ISA peripherals do not block the traffic of the
PCI bus. Special circuitry is built in to allow concurrent operation without causing dead lock even in a PCI-to-PCI
bridge environment. The chip also includes eight levels (double words) of line buffers from the PCI bus to the ISA
bus to further enhance overall system performance.
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CPU/Cache
CA
CD
Sideband Signals
Init/A20M#
INIR/NMI
SMI/Stop CLK
FERR/IGNNE Sleep
Boot Rom
On board
LPC I/O
North Bridge
MA/Command
MD
System Memory
DIMM Module ID
Vlink
Interface
SMB
LPC
VT8235
487 BGA
RTC
Crystal
USB 2.0 Ports 0~5
Keyboard/Mouse
Expansion
Cards
PCI
IDE Primary and Secondary
AC97 Link
APLC
GPIO, Power Control, Reset
MII Fast Ethernet Interface
Figure 1. PC System Configuration Using the VT8233
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Inter-operable with VIA Host-to-V-Link Host Controller
Combine with VT8754 (Apollo P4X333) for a complete 533 / 400 MHz FSB Pentium 4 system
Combine with VT8377 (Apollo KX400) for a complete 266 / 200 MHz FSB Athlon Socket-A system
May be used interchangeably with the VT8235CDLSout h Bridge in most board designs
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High Bandwidth 533 MB/s 8-bit V-Link Client Controller
Supports 66 MHz V-Link Client interface with peak bandwidth of 533 MB/sec
V-Link operates in 2x, 4x, and 8x modes
Full duplex commands with separate Strobe / Command
Request / Data split transaction
Configurable outstanding transaction queue for V-Link Client accesses
Auto Client Retry to eliminate V-Link Host-Client Retry cycles
Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer latency; all V-Link
transactions for both Host and Client have a consistent view of transaction data depth and buffer size to
avoid data overflow.
Highly efficient V-Link arbitration with minimum overhead; all V-Link transactions have predictable cycle
length with known Command / Data duration
Auto connect / reconnect capability and dynamic stop for minimum power consumption
Parity checking to insure correct data transfers
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Integrated Peripheral Controllers
Integrated Fast Ethernet Controller with 1 / 10 / 100 Mbit capability
Integrated USB 2.0 Controller with three root hubs and six function ports
Dual channel UltraDMA-133 / 100 / 66 / 33 master mode EIDE controller
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AC-link interface for AC-97 audio codec and modem codec
HSP modem support
Integrated DirectSound compatible digital audio controller
LPC interface for Low Pin Count interface to Super-I/O or ROM
Integrated Legacy Functions
Integrated Keyboard Controller with PS2 mouse support
Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm for
ACPI
Integrated DMA, timer, and interrupt controller
Serial IRQ for docking and non-docking applications
Fast reset and Gate A20 operation
Concurrent PCI Bus Controller
33 MHz operation
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Supports up to six PCI masters
Peer concurrency
Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same
time
Zero wait state PCI master and slave burst transfer rate
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PCI to system memory data streaming up to 132Mbyte/sec (data sent to north bridge via high speed V-Link
Interface)
PCI master snoop ahead and snoop filtering
Eight DW of CPU to PCI posted write buffers
Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting
possibilities
Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
Four lines of post write buffers from PCI masters to DRAM
Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters
Delay transaction from PCI master accessing DRAM
Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)
Symmetric arbitration between Host/PCI bus for optimized system performance
Complete steerable PCI interrupts
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PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs
Fast Ethernet Controller
High performance PCI master interface with scatter / gather and bursting capability
Standard MII interface to external PHYceiver
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1 / 10 / 100 MHz full and half duplex operation
Independent 2K byte FIFOs for receive and transmit
Flexible dynamically loadable EEPROM algorithm
Physical, Broadcast, and Multicast address filtering using hashing function
Magic packet and wake-on-address filtering
Software controllable power down
UltraDMA- 133/ 100 / 66 / 33 Master Mode EIDE Controller
Dual channel master mode hard disk controller supporting four Enhanced IDE devices
Transfer rate up to 133MB/sec to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-133
interface
Increased reliability using UltraDMA-133/100/66 transfer protocols Thirty-two levels (double words) of
prefetch and write buffers
Dual DMA engine for concurrent dual channel operation
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Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant
Full scatter gather capability
Support ATAPI compliant devices including DVD devices
Support PCI native and ATA compatibility modes
Complete software driver support
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Direct Sound Ready AC97 Digital Audio Controller
AC-Link access to 4 CODECs (AC97 + AMC97 + MC97)
Multi channel Audio
Bus Master Scatter / Gather DMA
Dedicated read and write channels supporting simultaneous stereo playback and record
Dedicated read and write channels supporting simultaneous modem receive and transmit
1 stereo DirectSound channel with source / volume control / mixer
1 shared FM / SPDIF PCM read channel
1 dedicated channel supporting multi-channel audio
32-byte line-buffers for each SGD channel
Programmable 8bit / 16bit mono / stereo PCM data format support
AC97 2.1 compliant
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System Management Bus Interface
Host interface for processor communications
Slave interface for external SMBus masters
Universal Serial Bus Controller
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USB v2.0 and Enhanced Host Controller Interface (EHCI) v1.0 compatible
USB v1.1 and Universal Host Controller Interface (UHCI) v1.1 compatible
Eighteen level (double words) data FIFO with full scatter and gather capability
Three root hubs and six function ports
Integrated physical layer transceivers with optional over-current detection status on USB inputs
Legacy keyboard and PS/2 mouse support
Sophisticated PC2001-Compatible Mobile Power Management
Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management
ACPI v1.0 Compliant
APM v1.2 Compliant
CPU clock throttling and clock stop control for complete ACPI C0 to C3 state support
PCI bus clock run, Power Management Enable (PME) control, and PCI/CPU clock generator stop control
Supports multiple system suspend types: power-on suspends with flexible CPU/PCI bus reset options,
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suspend to DRAM, and suspend to disk (soft-off), all with hardware automatic wake-up
Multiple suspend power plane controls and suspend status indicators
One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer
Normal, doze, sleep, suspend and conserve modes
Global and local device power control
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System event monitoring with two event classes
Primary and secondary interrupt differentiation for individual channels
Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid
open/close for system wake-up
32 general purpose input ports and 32 output ports
Multiple internal and external SMI sources for flexible power management models
Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field
Thermal alarm on external temperature sensing circuit
I/O pad leakage control
Plug and Play Controller
PCI interrupts steerable to any interrupt channel
Steerable interrupts for integrated peripheral controllers: USB, floppy, serial, parallel, and audio
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Microsoft Windows XPTM, Windows NTTM, Windows 2000TM, Windows 98TM and plug and play BIOS
compliant
Built-in NAND-tree pin scan test capability
0.22um, 2.5V, low power CMOS process
Single chip 27 x 27 mm, 1.0 mm ball pitch, 487 pin BGA
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1.3.4 System Frequency Synthesizer andeDDR-SDRAM
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The ICS950403 is a system clock synthesizer chip for AMD K8 based notebook systems with AMD, VIA or Ali
chipset. This provides all clocks required for such a system. The ICS950403 employs a proprietary closed loop
design, which tightly controls the percentage of spreading over process and temperature variations. Serial
programming I 2 C interface allows changing functions, stop clock programming and frequency selection.
Output Features
2 - Differential pair push-pull CPU clocks @ 3.3V
8 - PCICLK (Including 1 free running) @ 3.3 V
3 - Selectable PCICLK/HTTCLK @ 3.3V
1 - HTTCLK @ 3.3V
1 - 48MHz @ 3.3V fixed
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1 - 24_48MHz @ 3.3V
3 - REF @ 3.3V, 14.318MHz
Features/Benefits
Programmable output frequency
Programmable output divider ratios
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Programmable output rise/fall time
Programmable output skew
Programmable spread percentage for EMI control
Watchdog timer technology and RESET# output to reset system if system malfunction
Programmable watch dog safe frequency
Support I2C index read/write and block read/write operations
Uses external 14.318MHz crystal
Support Hyper Transport Technology (HTTCLK)
48-Pin 300mil SSOP
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1.3.5 PC Card Interface Controller: ENE CB1410
The ENE CB1410 is a high-performance PCI-to-PC Card controller that supports a single PC Card socket compliant
with the 1997 PC Card Standard. The ENE CB1410 provides features that make it the best choice for bridging
between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit
PC Card specification defined in PCI Local Bus Specification and defines the new 32-bit PC Card, CardBus, capable
of full 32-bit data transfers at 33 MHz. The ENE CB1410 supports both 16-bit and CardBus PC Cards, powered at 5
V or 3.3 V, as required.
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The ENE CB1410 is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI
master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or
CardBus PC Card bridging transactions. The ENE CB1410 is also compliant with the latest PCI Bus Power
Management Interface Specification and PCI Bus Power Management Interface Specification for PCI to CardBus
Bridges.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The ENE
CB1410 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for
maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level
with sustained bursting. The ENE CB1410 can also be programmed to accept fast posted writes to improve systembus utilization.
Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and
serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement
sideband functions. Many other features designed into the ENE CB1410, such as socket activity light-emitting diode
(LED) outputs, are discussed in detail throughout the design specification.
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An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption
while operating at PCI clock rates up to 33MHz. Several low-power modes enable the host power management
system to further reduce power consumption.
The CB1410 Supports the Following Features
3V operation with 5V tolerant
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144-pin LQFP or 144-ball LFBGA package for CB1410 single slot Cardbus controller
Compliant with
PCI Local Bus Specification, Revision 2.2
PCI Bus Power Management Interface Specification, Revision 1.1
PCI Mobile Design Guide, Version 1.1
Advanced Configuration and Power Interface Specification, Revision 1.0
PC99 System Design Guide
PC Card Standard 8.0
Interrupt Configuration
Support parallel PCI interrupts
Support parallel IRQ and parallel PCI interrupts
Support serialized IRQ and parallel PCI interrupts
Support serialized IRQ and PCI interrupts
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Power Management Control Logic
Support CLKRUN# protocol
Supports SUSPEND#
Support PCI PME# from D3, D2, D1 and D0
Support PCI PME# from D3 cold
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Supports D3STATE#
Power Switch Interface
Supports parallel 4 wire power switch interface.
Misc Control Logic
Support CLKRUN# protocol
Support serial EEPROM interface
Support socket activity LED
Support 5 GPIOs and GPE#
Support standard Zoomed Video Port
Support SPKOUT, CAUDIO and RIOUT#
Support PCI LOCK
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1.3.6 One-Slot PC Card Power Interface Switch: ENE CP-2211
CP-2211 is single Slot PCMCIA and CardBus power switch. It integrates control logic, low switching resistance
MOSFET, over current alarm and over temperature auto shutdown circuits. It can deliver 3.3V or 5V to PC Card
VCCOUT and 3.3V, 5V or 12V to PC Card VPPOUT. The output current is up to 1A for VCCOUT and 250mA for
VPPOUT.
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Low Switching Resistance (100mΩ for VCC Switch)
Over temperature auto shutdown
1A output current for VCCOUT
150mA output current for VPPOUT
Only 3.3V is required for chip normal operation
12V is not required for 3.3V or 5V Output
Break-Before-Make Switching
16-Pin SSOP Package
1.3.7 AC’97 Audio System: VIA VT1617/1617A
The VT1617/1617A is a high performance audio codec which complies with the AC’97 revision 2.3. It integrates
Sample Rate Converters on all channels and can be adjusted in 1Hz increments. This chip supports 96KHz sampling
rates, high-quality 96KHz S/PDIF output, stereo digital playback.
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The 20bit, ΣΔADCs VT1617/1617A implements stereo recording and white noise removal to ensure the best
quality of recording. It features 8-channel hardware-expansion for flexible 7.1-channel applications. It also contains
a hardware down-mixing feature that allows the end users enjoy 6-channel audio with 2-channel or 4-channel
speakers. The analog mixer circuitry integrates a stereo enhancement to provide a pleasing 3D surround sound effect
for stereo media. The VT1617/1617A has a built-in quality headphone amplifier and a high-accuracy PLL for cost
saving. This codec is designed with aggressive power management to achieve low power consumption; when used
with a 3.3V analog supply, the owner consumption is further reduced.
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AC’97 V2.3 Audio Codec
Fully compliant with AC’97 Revision 2.3
High Audio Quality
Support sampling rates up to 96KHz
Independent 20-bit ADC and 20-bit DAC
SNR (Signal to Noise Ratio) exceeds 95dB
Built-in 1Hz resolution VSR converter
Various Output Format
Support 8-channel outputs
Hardware down-mixed 6-channel to 2-channel or 4-channel
Center and LFE channel swapping
Alternative Line-Level outputs at surround output
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96KHz S/PDIF output
Direct CD input to S/PDIF output
Added-on Functions
Integrates headphone amplifier with mute
Dual microphones supporting Karaoke mixing
Extension Control
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4-bit 3D depth control
Support EAPD control
Supports GPIO pins control
Selectable clock sources
Driver support Magic 5.1
Convenient Design
Flexible Jack-detect design
Built-in accurate PLL for saving an external crystal
Built-in Smart 5.1.
Power
Low power consumption mode
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3.3V or 5V analog, 3.3V digital power supply
Package
48-Pin LQFP Package
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1.3.9 Memory System
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1.3.8 System Flash Memory (BIOS)
2M bit Flash memory
Flashed by 5V only
User can upgrade the system BIOS in the future just running flash program.
64MB, 128MB, 256MB, 512MB (x64) 200-Pin DDR SDRAM SODIMMs
JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)
Utilizes 333Mb/s and 400Mb/s DDR SDRAM components
64MB (8 Meg x 64 [H]); 128MB (16 Meg x 64, [H] and [HD]); 256MB (32 Meg x 64 [HD]); 512MB (64
Meg x 64 [HD])
VDD= VDDQ= +2.5V ±0.2V
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VDDSPD = +2.2V to +5.5V
2.5V I/O (SSTL_2 compatible)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-aligned with data for WRITEs
Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
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Bidirectional data strobe (DQS) transmitted/received with data—i.e.,source-synchronous data capture
Differential clock inputs (CK and CK# - can be multiple clocks, CK0/CK0#, CK1/CK1#, etc.)
Four internal device banks for concurrent operation
Selectable burst lengths: 2, 4, or 8
Auto precharge option
Auto Refresh and Self Refresh Modes
15.6μs (MT4VDDT864H, MT8VDDT1664HD), 7.8125μs (MT4VDDT1664H, MT8VDDT3264HD,
MT8VDDT6464HD) maximum average periodic refresh interval
Serial Presence Detect (SPD) with EEPROM
Fast data transfer rates PC2700, PC2100 or PC1600
Selectable READ CAS latency for maximum compatibility
Gold-plated edge contacts
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1.3.10 LAN: VT6103L 10Base-T/100Base-TX Ethernet PHY
The VT6103L is a Physical Layer device for Ethernet 10BASE-T and 100BASE-TX using category 5 Unshielded,
Type 1 Shielded, and Fiber Optic cables. This VLSI device is designed for easy implementation of 10 / 100 Mb/s
Fast Ethernet LANs. It interfaces to a MAC through an MII interface ensuring interoperability between products
from different vendors.
Product Features
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Single Chip 100Base-TX/10Base-T Physical Layer solution
Dual Speed – 100/10 Mbps
Half And Full Duplex
MII Interface to Ethernet Controller
MII Interface to Configuration & Status
Optional Repeater Interface
Auto Negotiation : 10/100, Full/Half Duplex
Meet All Applicable IEEE 802.3, 10Base-T and 100Base-Tx Standards
On Chip Wave Shaping – No External Filters Required
Adaptive Equalizer
Baseline Wander Correction
LED Outputs
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Link Status
Duplex status
Speed Status
Collision
48 Pin SSOP Package
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1.4 Other Functions
1.4.1 Hot Key Function
Keys
Feature
Combination
Fn + F1
Wireless lan on/off
Meaning
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Wireless Lan on ->off
Fn + F2
Reserve
Fn + F3
Volume down
Adjust Audio volume down
Fn + F4
Volume up
Adjust Audio volume up
Fn + F5
Display switch
LCD->CRT->LCD&CRT, TV-out will be not TV present.
TV->CRT->TV&CRT, TV-out is connected.
Fn + F6
Brightness down
Adjust LCD panel backlight darkness.
Fn + F7
Brightness up
Adjust LCD panel backlight lightness.
Fn + F8
MAX brightness toggle
Toggle LCD brightness maximum or user setting
Fn + F9
Reserved
Fn + F10
Battery Low warning beep toggle
Toggle to enable/mute the “Battery Low Warning” beep sound
Fn + F11
LCD panel toggle on/off
Toggle LCD panel on or off.
Fn + F12
System sleep
System sleep button function.
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1.4.2 Power on/off/Suspend/Resume Button
1.4.2.1 APM Mode
At APM mode, Power button is on/off system power.
1.4.2.2 ACPI Mode
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At ACPI mode, power button behavior was set by windows power management control panel. You could set
“standby” or “power off” to power button function. Continue pushing power button over 4 seconds will force
system off at ACPI mode. There is no sleep button on this machine.
1.4.3 Lid Switch
System automatically provides a Keyboard cover state through PS2 to relative application when user closes the
Keyboard cover.
1.4.4 LED Indicators
System has some status LED indicators to display system activity,.
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1.4.4.1 Three LED Indicators on Display Housing/Cover:
From left to right that indicates, AC Power/Battery Power and Battery Charger
AC Power:
This LED lights green when AC powers to the notebook, and flash (on 1 second, off 1 second) when
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Suspend to DRAM is active using AC power. The LED is off when the notebook is off or powered by
batteries.
Battery Power:
This LED lights green when Battery powers to the notebook, and flash (on 1second, off 1 second) when
Suspend to DRAM is active using Battery power. The LED is off when the notebook is off or powered by
AC power.
Battery Charge Status:
During normal operation, this LED stays off as long as the battery is charged. When the battery charge
drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second. When AC is
connected, this indicator glows green if the battery pack is fully charged or orange (amber) if the battery is
being charged. When battery charging error, it will flash orange light.
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WLAN RF Status (BTO: Wireless LAN only):
This LED indicates WLAN RF module power status. User could use Fn+F1 to enable or disable RF.
1.4.4.2 Five LED Indicators above Front Side Housing:
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From left to right that indicates CD, HDD, NUM LOCK, CAPS LOCK and SCROLL LOCK.
l FAN is controlled by Embedded Controller Winbond W83L950D. Thermal with hardware monitor to sense CPU
temperature and EC control fan on/off.
CR2032 3V 220mAh lithium battery
When AC in or system main battery inside, CMOS battery will consume no power
AC or main battery not exists, CMOS battery life is at lest 10 years
Battery was put in battery holder, can be replaced.
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1.4.7 I/O Port
One 3 pins AC power socket
One CRT monitor
One S-Video TV out (PAL/NTSC)
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Six USB 2.0 ports for all USB devices
One MODEM RJ-11 phone jack for PSTN line
One RJ-45 for LAN
Headphone out Jack
Microphone Input Jack
One Cardbus Sockets for one type II PC card extension
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2. System View and Disassembly
2.1 System View
2.1.1 Front View
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Lock
2 Ventilation Openings
1 2
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2.1.3 Right-side View
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CD/DVD driver
Line out jack
RJ-45 connector
RJ-11 connector
AC Power Indicator
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2 3
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4 Battery Power Indicator
Battery Charge Indicator
PC Card slot
2.1.4 Rear View
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10
MIC in jack
USB port *2
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9
VGA port
S-Video output connector
Ventilation Openings
USB port *4
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2 3
5
4 Power connector
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1
2.1.5 Bottom View
2
1 Wireless Card cover
2 CPU
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LCD Screen
2
Stereo set
3
Keyboard
4
Caps Lock
5
Wireless Card Indicator
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CD/DVD-Rom Indicator
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HDD Indicator
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11
Num Lock
1
2
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11
Caps Lock
Scroll Lock
Power Button
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9 8
6 5
7
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2.2 System Disassembly
The section discusses at length each major component for disassembly/reassembly and show corresponding
illustrations. Use the chart below to determine the disassembly sequence for removing components from the
notebook.
NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the
notebook is not turned on or connected to AC power.
2.2.1 Battery Pack
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2.2.2 Keyboard
Modular Components
2.2.3 CPU
2.2.4 HDD Module
2.2.5 DVD-ROM Drive
2.2.6 DDR-SDRAM
NOTEBOOK
2.2.7 Modem Card
2.2.8 LCD Assembly
LCD Assembly Components
2.2.9 Inverter Board
2.2.10 LCD Panel
2.2.11 System Board
Base Unit Components
2.2.12 Touch Pad
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2.2.1 Battery Pack
Disassembly
1. Carefully put the notebook upside down.
2. Remove the four screws, then remove the CPU cover. (Figure 2-1)
3. Put up the battery pack, then free the battery pack. (Figure 2-2)
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Figure 2-1 Remove the four screws
Figure 2-2 Remove the battery pack
Reassembly
1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you hear a
clicking sound.
2. Replace the CPU cover and secure the four screws.
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2.2.2 Keyboard
Disassembly
1. Remove the battery pack. (Refer to section 2.2.1 Disassembly)
2. Open the top cover.
3. Loosen the five latches locking the keyboard. (Figure 2-3)
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Figure 2-3 Loosen the five latches
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4. Slightly lift up the keyboard and disconnect the cable from the mother board, then separate the keyboard.
(Figure 2-4)
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Figure 2-4 Lift up the keyboard and disconnect the cable
Reassembly
1. Reconnect the keyboard cable and fit the keyboard back.
2. Replace the keyboard into place and fasten the five latches.
3. Replace the battery pack. (Refer to section 2.2.1 reassembly)
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2.2.3 CPU
Disassembly
1. Remove the battery pack. (Refer to section 2.2.1 Disassembly)
2. Disconnect the fan’s power cord from system board and remove five screws that secure the heatsink upon the
CPU, Then free the heatsink. (Figure 2-5)
3. To remove the existing CPU, lift the socket arm up to the vertical position. (Figure 2-6)
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Figure 2-5 Free the heatsink
Figure 2-6 Disconnect the cable
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Reassembly
1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins into
the holes. Place the lever back to the horizontal position and push the lever to the left.
2. Reconnect the fan’s power cord to the system board, fit the heatsink onto the top of the CPU and secure with five
screws.
3. Replace the battery pack. (See section 2.2.1 reassembly)
CPU socket stopper
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2.2.4 HDD Module
Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)
2. Remove two screws fastening the HDD module and slightly lift up HDD module. (Figure 2-7)
3. Remove four screws to separate the hard disk drive from the bracket, free the hard disk driver. (Figure 2-8)
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Figure 2-7 Remove HDD module
Figure 2-8 Free the HDD driver
Reassembly
1. Attach the bracket to hard disk drive and secure with four screws.
2. Slide the HDD module into the compartment and secure with two screws.
3. Replace the battery pack. (Refer to section 2.2.1 reassembly)
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2.2.5 CD/DVD-ROM Drive
Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)
2. Remove one screw fastening the CD/DVD-ROM drive. (Figure 2-9)
3. Insert a small rod, such as a straightened paper clip, into CD/DVD-ROM drive’s manual eject hole () and push
firmly to release the tray. Then gently pull out the CD/DVD-ROM drive by holding the tray that pops out().
(Figure 2-9)
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Figure 2-9 Remove the CD/DVDROM drive
Reassembly
1. Push the CD/DVD-ROM drive into the compartment and secure with one screw.
2. Replace the battery pack. (Refer to section 2.2.1 reassembly)
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2.2.6 DDR-SDRAM
Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)
2. Pull the retaining clips outwards () and remove the DDR-SDRAM (). (Figure 2-10)
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Figure 2-10 Remove the DDR-SDRAM
Reassembly
1. To install the DDR, match the DDR's notched part with the socket's projected part and firmly insert the DDR into
the socket at 20-degree angle. Then push down until the retaining clips lock the DDR into position.
2. Replace the battery pack. (Refer to section 2.2.1 reassembly)
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2.2.7 Modem Card
Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)
2. Remove the two screws. (Figure 2-11)
3. Disconnect the cable from the system board, Then free the modem card. (Figure 2-12)
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Figure 2-11 Remove the two screws
Figure 2-12 Disconnect the cable
Reassembly
1. Fit the modem card, Then reconnect the cable and secure with two screws.
2. Replace the battery pack. (Refer to section 2.2.1 reassembly)
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2.2.8 LCD ASSY
Disassembly
1. Remove the battery pack and keyboard. (See sections 2.2.1 and 2.2.2 Disassembly)
2. Remove two hinge covers. (Figure 2-13)
3. Carefully put the notebook upside down. Remove the two screws fastening the wireless cover. (Figure 2-14)
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Figure 2-13 Remove two hinge covers
Figure 2-14 Remove the two screws
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4. Disconnect the LCD cable from the system board and detach the antenna. (Figure 2-15)
5. Remove the four screws and put up the LCD assembly, then free the LCD assembly. (Figure 2-16)
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Figure 2-15 Disconnect the LCD cable
Reassembly
Figure 2-16 Free the LCD assembly
1. Attach the LCD assembly to the base unit and secure with four screws, then fit the antenna.
2. Reconnect the one cable to the system board, Then replace the wireless cover and secure two screws.
3. Replace the two hinge covers.
4. Replace the keyboard and battery pack. (Refer to sections 2.2.2 and 2.2.1 Reassembly)
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2.2.9 Inverter Board
Disassembly
1. Remove the battery, keyboard and LCD assembly. (Refer to section 2.2.1, 2.2.2 and 2.2.8 Disassembly)
2. Remove two screws and rubbers on the corners of the LCD panel. (Figure 2-17)
3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the process until
the cover is completely separated from the housing.
4. Remove the one screw fastening the inverter board. (Figure 2-18)
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Figure 2-17 Remove LCD cover
Figure 2-18 Remove the one screw
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5. To remove the inverter board on the lower part of the LCD housing , disconnect two cables. (Figure 2-19)
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Figure 2-19 Remove the inverter board
Reassembly
1. Reconnect the two cables. Fit the inverter board back into place and secure with one screw.
2. Replace the LCD cover and secure with two screws and rubbers.
3. Replace the LCD assembly. (Refer to section 2.2.8 Reassembly)
4. Replace the keyboard and battery pack. (Refer to sections 2.2.2 and 2.2.1 Reassembly)
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2.2.10 LCD Panel
Disassembly
1. Remove the battery, keyboard and LCD assembly. (Refer to sections 2.2.1, 2.2.2 and 2.2.8 Disassembly)
2. Remove the LCD cover. (Refer for two steps 2,3 of section 2.2.9 Disassembly)
3. Remove the eight screws fastening the LCD panel and detach the cable, Then lift it up. (Figure 2-20)
4. Remove the five screws fastening the LCD brackets. (Figure 2-21)
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Figure 2-20 Remove the eight screws
and detach the cable
Figure 2-21 Remove the five screws
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5. Disconnect the cable and free the LCD panel. (Figure 2-22)
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Figure 2-22 Free the LCD panel
Reassembly
1. Reconnect the cable, then replace the LCD brackets and secure with five screws.
2. Fit the LCD panel back into place and secure with eight screws, then reconnect the cable to the inverter board.
3. Replace the LCD cover and secure with two screws and rubbers. (Refer to section 2.2.9 Reassembly)
4. Replace the LCD assembly. (Refer to section 2.2.8 Reassembly)
5. Replace the keyboard and battery pack. (Refer to sections 2.2.2 and 2.2.1 Reassembly)
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2.2.11 System Board
Disassembly
1. Remove the battery, keyboard, CPU, hard disk drive, CD/DVD-ROM drive, DDR-SDRAM, modem card and
LCD assembly. (Refer to sections 2.2.1, 2.2.2, 2.2.3, 2.2.4, 2.2.5, 2.2.6, 2.2.7 and 2.2.8 Disassembly)
2. Remove the four screws. (Figure 2-23)
3. Remove the eleven screws and free the housing. (Figure 2-24)
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Figure 2-23 Remove the four screws
Figure 2-24 Remove the eleven screws
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4. Remove the three screws and lift up the housing’s shielding. (Figure 2-25)
5. Disconnect the speaker’s cable and the touch pad’s cable, Then remove the one screw and four hex nuts. Now
you can lift up the system board. (Figure 2-26)
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Figure 2-25 Remove the three screws
Reassembly
Figure 2-26 Free the system board
1. Replace the system board into the top cover and secure with one screw and four hex nuts.
2. Reconnect the touch pad’s cable, the speaker’s cable.
3. Replace the housing’s shielding and secure with three screws.
4. Replace the housing and secure with fifteen screws.
5. Replace the LCD assembly, modem card, DDR-SDRAM, CD/DVD-ROM, HDD, CPU, keyboard and battery
pack. (See sections 2.2.8, 2.2.6, 2.2.5, 2.2.4, 2.2.3, 2.2.2 and 2.2.1 Reassembly)
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2.2.12 Touch Pad
Disassembly
1. Remove the system board. (See section 2.2.11 Disassembly)
2. Remove the two screws and disconnect the cable, then free the touch pad. (Figure 2-27)
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Figure 2-27 Free the touch pad
Reassembly
1. Replace the touch pad and reconnect the cable.
2. Replace the touch pad shielding and secure with two screws.
3. Reassemble the notebook. (See the previous sections Reassembly)
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3. Definition & Location of Connectors / Switches
3.1 Mother Board – A(1)
J10 J12
J9
J5
PJ1 : AC Power Jack
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J2
J7
PJ2 : Battery Connector
J1 : S-Video Port
J8
J509
J2 : External VGA Connector
J3, J4, J9 : USB Port Connector
J6
J1
J5 : RJ11 & RJ45 Connector
J6 : North Bridge Fan Connector
J7 : MDC Jump Wire Connector
J8 : LCD Connector
J3
J10 : Microphone Jack
J4
J11 : CPU Fan Connector
J12 : Line Out Jack
J11
PJ1
------ To next page ------
PJ2
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3. Definition & Location of Connectors / Switches
3.1 Mother Board – A(2)
------ Continue to previous page ------
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J13 : Internal Speaker Connector
J20 SW1
J509
J14 : Primary EIDE Connector
J15 : MDC Board Connector
J16,J17 : Extend DDR SDRAM Socket
J18 : Touch-Pad Connector
J20 : RTC Battery Connector
J21
J15
J21 : Secondary IDE Connector
J22 : Mini-PCI Socket
J16
J17
J22
SW1 : H8 Reset Button
J18
J13
J14
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3. Definition & Location of Connectors / Switches
3.2 Mother Board - B
J501 : Internal Keyboard Connector
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J502 : PCMCIA Card Socket
J502
J509
SW501 : Power Button
J501
SW502 : Touch-Pad Up Button
SW503 : Touch-Pad Right Button
SW504 : Touch-Pad Left Button
SW505 : Touch-Pad Down Button
SW505
SW503
SW502
SW501
SW504
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4. Definition & Location of Major Components
4.1 Mother Board - A
U2 : VT6103L LAN Controller
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U3 : TV Encoder(VIA_VT1622)
U10
U13
U2
U26
U6 : AMD CPU Socket
U16
U20
J509
U9 : LVDS Encoder(VIA_VT1634)
U14
U3
U9
U10 : VT1617A Audio Codec
U12 : VIA_K8N800 North Bridge
U13 : G1428 Sounder Amplifier
U12
U14 : ICS950403 Clock Generator
U6
U16 : KBC (W83L950D)
U20 : VIA_VT8235CD South Bridge
U25
U25 : LPC BIOS ROM
U26 : CB1410 PCMCIA Controller
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5. Pin Descriptions of Major Components
5.1 AMD Mobile Athlon 64(ClawHammer) Processor(1)
DDR SDRAM Memory Interface Pins
Signal Name
Type
DDR SDRAM Memory Interface Pins (Continued)
Description
Signal Name
Type
Description
O-IOS
DRAM Bank Address. Two copies are provided to
accommodate the loading of unbuffered DIMMs. During
precharges, activates, reads, and writes the two copies are
inverted from each other to minimize switching noise. The
signals are inverted only when the bus is used to carry address
information.1
DRAM Reset pin for Suspend-to-RAM power management
mode. This pin is required for registered DIMMs only.
DRAM Interface Voltage Reference 1
O-IOD Differential DDR SDRAM clock to the top of DIMM 0 for
unbuffered DIMMs.1
O-IOD Differential DDR SDRAM clock to the top of DIMM 1 for
unbuffered DIMMs.1
O-IOD Differential DDR SDRAM clock to the bottom of DIMM 0 for
unbuffered DIMMs.1
O-IOD Differential DDR SDRAM clock to the bottom of DIMM 1 for
unbuffered DIMMs.1
O-IOD Differential DDR SDRAM clock to DIMM 3 for registered
DIMMs.1
O-IOD Differential DDRS DRAM clock to DIMM 2 for registered
DIMMs.1
O-IOD Differential DDR SDRAM clock to the middle of DIMM 1 for
unbuffered DIMMs, or DIMM 1 for registered DIMMs.1
O-IOD Differential DDR SDRAM clock to the middle of DIMM 0 for
unbuffered DIMMs, or DIMM 0 for registered DIMMs.1
O-IOS Clock Enables to DIMMs. Used to gate clocks for power
management functionality.1
B-IOS DRAM Data Strobes synchronous with MEMDATA and
MEMCHECK during DRAM read and writes.1
B-IOS DRAM Interface Data Bus
MEMBANKA[1:0]
MEMBANKB[1:0]
MEMCHECK[7:0]
B-IOS
DRAM Interface ECC Check Bits
L0_CLKIN_H/L[1:0]
I-HT
Link 0 Clock Input
MEMCS_L[7:0]
O-IOS
DRAM Chip Selects 1
L0_CTLIN_H/L[1:0]
I-HT
Link 0 Control Input 2
MEMRASA_L
MEMRASB_L
O-IOS
L0_CADIN_H/L[15:0]
I-HT
Link 0 Command/Address/Data Input
L0_CLKOUT_H/L[1:0]
O-HT Link 0 Clock Outputs
MEMCASA_L
MEMCASB_L
O-IOS
MEMWEA_L
MEMWEB_L
O-IOS
MEMADDA[13:0]
MEMADDB[13:0]
O-IOS
DRAM Row Address Select. MEMRASA_L and
MEMRASB_L are functionally identical. Two copies are
provided to accommodate the loading of unbuffered DIMMs.1
DRAM Column Address Select. MEMCASA_L and
MEMCASB_L are functionally identical. Two copies are
provided to accommodate the loading of unbuffered DIMMs.1
DRAM Write Enable. MEMWEA_L and MEMWEB_L are
functionally identical. Two copies are provided to accommodate
the loading of unbuffered DIMMs.1
DRAM Column/Row Address. Two copies are provided to
accommodate the loading of unbuffered DIMMs. During
precharges, activates, reads, and writes, the two copies are
inverted from each other (except A[10] which is used for
auto-precharge) to minimize switching noise. The signals are
inverted only when the bus is used to carry address
information.1
MEMCLK_H/L[7]
MEMCLK_H/L[6]
MEMCLK_H/L[5]
MEMCLK_H/L[4]
MEMCLK_H/L[3]
MEMCLK_H/L[2]
MEMCLK_H/L[1]
MEMCLK_H/L[0]
MEMCKEA
MEMCKEB
MEMDQS[17:0]
MEMDATA[63:0]
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MEMRESET_L
O-IOS
MEMVREF
VREF
MEMZP
A
Compensation Resistor tied to VSS 1
MEMZN
A
Compensation Resistor tied to 2.5 V 1
Note: For connection details and proper resistor values, see the AMD Athlon™ 64 Processor
Motherboard Design Guide, order# 24665.
HyperTransport™ Technology Pin Descriptions
Signal Name
Type Description
L0_CTLOUT_H/L[1:0]
O-HT Link 0 Control Output
L0_CADOUT_H/L[15:0]
O-HT Link 0 Command/Address/Data Outputs
L0_REF1
A
Compensation Resistor to VLDT 1
L0_REF0
A
Compensation Resistor to VSS 1
Note: 1.These pins are used in an alternating fashion to compensate R TT by internal comparison to 3/4
VLDT and 1/4 VLDTand compensate R ON by comparison to each other around 1/2 VLDT.
For proper resistor value, see theAMD Athlon™ 64 Processor Motherboard Design Guide, order#
24665.
2.The unused L0_CTLIN_H/L[1] pins must be properly terminated such that the true pin is pulled
High and thecomplement is pulled Low. Refer to the AMD Athlon™ 64 Processor Motherboard
Design Guide, order# 24665, for details.
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5.1 AMD Mobile Athlon 64(ClawHammer) Processor(2)
Miscellaneous Pin Descriptions
Signal Name
JTAG Pin Descriptions
Type Description
Type
Description
RESET_L
I-IOS System Reset
TCK
I-IOS
JTAG Clock
PWROK
I-IOS Indicates that voltages and clocks have reached specified
operation
I-IOS HyperTransport™ Technology Stop Control Input. Used for
power management and for changing HyperTransport link width
and frequency.
O-IOS Voltage ID to the regulator
TMS
I-IOS
JTAG Mode Select
TRST_L
I-IOS
JTAG Reset
TDI
I-IOS
JTAG Data Input
TDO
O-IOS
JTAG Data Output
LDTSTOP_L
VID[4:0]
THERMDA
THERMDC
THERMTRIP_L
COREFB_H/L
Signal Name
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A
Anode (+) of the thermal diode
A
Cathode (–) of the thermal diode
O-IO-O Thermal Sensor Trip output, asserted at nominal temperature of
D
125 ℃.
A
Differential feedback for VDD Power Supply
VDDIOFB_H/L
A
Differential feedback for VDDIO Power Supply
CORE_SENSE
A
VDD voltage monitor pin
VDDA
S
Filtered PLL Supply Voltage
VTT_SENSE
A
VTT voltage monitor pin
VDDIO_SENSE
A
VDDIO voltage monitor pin
VDD
S
Core power supply
VDDIO
S
DDR SDRAM I/O ring power supply
VLDT_A
VLDT_B
VTT_A
VTT_B
VSS
S
S
HyperTransport™ I/O ring power supply for side A and side B
of the package
VTT regulator voltage for side A and side B of the die
S
Ground
Clock Pin Descriptions
Signal Name
Type
Description
CLKIN_H/L
I-IOD
200-MHz PLL Reference Clock
FBCLKOUT_H/L
O-IOD Core Clock PLL 200-MHz Feedback Clock
Debug Pin Descriptions
Signal Name
DBREQ_L
DBRDY
Type
Description
I-IOS Debug Request
O-IOS Debug Ready
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5.2 VIA K8N800 North Bridge(1)
AGP Bus Interface
Signal Name
GD[31:0]
I/O
Signal Description
(see pin
list)
IO
Address / Data Bus. Address is driven with GDS assertion for
AGP-style transfers and with GFARME# assertion for PCI-style
transfers.
Command / Byte Enable. (Interpreted as GC/BE# for AGP
2x/4x and GC#/BE for 8x). For AGP cycles these pins provide
command information (different commands than for PCI) driven
by the master (graphics controller) when requests are being
enqueued using GPIPE# (2x/4x only as GPIPE# isn™t used in
8x mode). These pins provide valid byte information during
AGP write transactions and are driven by the master. The target
(this chip) drives these lines to io0000lt during the return of
AGP read data. For PCI cycles, commands are driven with
GFARME# assertion. Byte enables corresponding to supplied or
requested data are driven on following clocks.
AGP Parity. A single parity bit is provided over GD[31:0] and
GC#BE[3:0].
Dynamic Bus Inversion High / Low. AGP 8x transfer mode
only. Driven by the source to indicate whether the
corresponding data bit group (GDBIH for GD[31:16] and
GDBIL for GD[15:0]) needs to be inverted on the receiving end
(1 on GDBIx indicates that the corresponding data bit group
should be inverted). Used to limit the number of simultaneously
switching outputs to 8 for each 16-pin group.
Pipelined Request. Not used by AGP 8x. Asserted by the
master (external graphics controller) to indicate that a full-width
request is to be enqueued by the target (North Bridge). The
master enqueues one request each rising edge of GCLK while
GPIPE# is asserted. When GPIPE# is deasserted no new
requests are enqueued across the AD bus.
Note: See RxAE[1] for GPIPE# / GDBIH pin function
selection.
Bus Strobe 0. Source synchronous strobes for GD[15:0] (the
agent that is providing the data drives these signals). GDS0
provides timing for 2x data transfer mode; GDS0 and GDS0#
provide timing for 4x mode. For 8x transfer mode, GDS0 is
interpreted as GDS0F (i1Firstl. strobe) and GDS0# as GDS0S
(iSSecondl. strobe).
AC7
GC#BE[3:0]
(GCBE[3:0]# for AD11
4x mode)
AF11
AD15
GPAR
AGP Bus Interface (Continued)
Pin #
AC16
GDBIH
/ AC5
GPIPE#GDBIL
AC4
GADSTB0F(GA AE15
DSTB0 for 4x),
GADSTB0S(GA AF15
DSTB0# for 4x)
IO
IO
IO
IO
Signal Name
Pin #
GADSTB1F(GA AE7
DSTB1 for 4x),
GADSTB1S(GA AF7
DSTB1# for 4x)
I/O
Signal Description
IO
Bus Strobe 1. Source synchronous strobes for GD[31:16] (i.e.,
the agent that is providing the data drives these signals). GDS1
provides timing for 2x data transfer mode; GDS1 and GDS1#
provide timing for 4x transfer mode. For 8x transfer mode,
GDS1 is interpreted as GDS1F (iSFirstle strobe) and GDS1# as
GDS1S (iSSecondld strobe).
Frame. Assertion indicates the address phase of a PCI transfer.
Negation indicates that one more data transfer is desired by the
cycle initiator. Interpreted as active high for 8x.
Initiator Ready. (Interpreted as active low for PCI/AGP2x/4x
and high for AGP 8x). For AGP write cycles, the assertion of
this pin indicates that the master is ready to provide all
write data for the current transaction. Once this pin is asserted,
the master is not allowed to insert wait states. For AGP read
cycles, the assertion of this pin indicates that the master is ready
to transfer a subsequent block of read data. The master is never
allowed to insert a wait state during the initial block of a read
transaction. However, it may insert wait states after each block
transfers. For PCI cycles, asserted when the initiator is ready
for data transfer.
Target Ready. (Interpreted as active low for PCI/AGP2x/4x
and high for AGP 8x). For AGP cycles, indicates that the target
is ready to provide read data for the entire transaction (when
the transaction can complete within four clocks) or is ready to
transfer a (initial or subsequent) block of data when the transfer
requires more than four clocks to complete. The target is
allowed to insert wait states after each block transfer for both
read and write transactions. For PCI cycles, asserted when the
target is ready for data transfer.
Device Select (PCI transactions only). This signal is driven by
the North Bridge when a PCI initiator is attempting to access
main memory. It is an input when the chip is acting as PCI
initiator. Not used for AGP cycles. Interpreted as active high for
AGP 8x.
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GFRAME(GFR AC9
AME# for 4x)
IO
GIRDY(GIRDY AC10
# for 4x)
IO
AC14
IO
GDEVSEL(GDE AC11
VSEL# for 4x
mode)
IO
GTRDY(GTRD
Y# for 4x)
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5.2 VIA K8N800 North Bridge(2)
AGP Bus Interface (Continued)
Signal Name
AGP Bus Interface (Continued)
Pin #
I/O
Signal Description
AGP8XDT#
Y2
I
GRBF(GRBF#
for 4x)
AD6
I
AGP 8x Transfer Mode Detect. Low indicates that the external
graphics card can support 8x transfer mode
Read Buffer Full. Indicates if the master (graphics controller)
is ready to accept previously requested low priority read data.
When GRBF# is asserted, the North Bridge will not return low
priority read data to the graphics controller.
Write Buffer Full.
GWBF(GWBF# AC1
for 4x)
(see pin
GSBA[7:0]#
(GSBA[7:0] for list)
4x)
I
GSBSTBF(GSB AF1
STB for 4x),
AE1
GSBSTBS(GSBS
TB# for 4x)
AB1
GST[2:0]
AA1
AA2
I
I
O
Signal Name
Pin #
GSTOP(GSTOP AC12
# for 4x)
I/O
Signal Description
IO
Stop (PCI transactions only). Asserted by the target to request
the master to stop the current transaction. Interpreted as active
high for AGP 8x.
Request. Master (graphics controller) request for use of the
AGP bus.
Grant. Permission is given to the master (graphics controller) to
use the AGP bus.
AGP System Error.
GREQ(GREQ# Y1
I
for 4x)
GGNT(GGNT# AA3
O
for 4x)
GSERR(GSERR AC15
IO
# for 4x)
Note: The AGP interface pins can be optionally configured as additional interfaces for connecting to
external display devices. For simplification of the AGP pin description tables above and on the next
page, that multiplexing is not shown here (see isAdditional 12C InterfaceslÓo, and display pin
description tables later in this document for more information).
Note: The AGP interface pins can be optionally configured as additional interfaces for connecting to
external display devices. For simplification of the AGP pin description tables above and on the next
page, that multiplexing is not shown here (see isAdditional I2C Interfacesll and display pin description
tables later in this document for more information).
Note: Separate system interrupts are not provided for AGP. The AGP connector provides interrupts via
PCI bus INTA-B#.
Note: A separate reset is not required for the AGP bus (RESET# resets both PCI and AGP buses)
Note: Two mechanisms are provided by the AGP bus to enqueue master requests: GPIPE# (to send
addresses multiplexed on the AD lines) and the SBA port (to send addresses unmultiplexed). AGP
masters implement one or the other or select one at initialization time (they are not allowed to change
during runtime). Only one of the two will be used; the signals associated with the other will not be used.
GRBF# has an internal pullup to maintain it in the de-asserted state in case it is not implemented on the
master device. AGP 8x mode allows only SBA (GPIPE# isn™t used in 8x mode).
Note: AGP 8x signal levels are 0V and 0.8V. AGP 8x mode maintains most signals at a low level when
inactive resulting in no current flow.
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Side Band Address. Provides an additional bus to pass address
and command information from the master (graphics controller)
to the target (North Bridge). These pins are ignored until
enabled.
Side Band Strobe. Driven by the master to provide timing for
GSBA[7:0]. 8x mode uses GSBSTBF (iBFirstlr strobe) and
GSBSTBS (iBSecondl) strobe). These signals are interpreted as
GSBSTB & GSBSTB# for AGP4x.
Status (AGP only). Provides information from the arbiter to a
master to indicate what it may do. Only valid while GGNT# is
asserted.
000 Indicates that previously requested low priority read or
flush data is being returned to the master (graphics
controller).
001 Indicates that previously requested high priority read data is
being returned to the master.
010 Indicates that the master is to provide low priority write
data for a previously enqueued write command.
011 Indicates that the master is to provide high priority write
data for a previously enqueued write command.
100 Reserved. (arbiter must not issue, may be defined in the
future).
101 Reserved. (arbiter must not issue, may be defined in the
future).
110 Reserved. (arbiter must not issue, may be defined in the
future).
111 Indicates that the master (graphics controller) has been
given permission to start a bus transaction. The master may
enqueue AGP requests by asserting PIPE# or start a PCI
transaction by asserting GFRM#. ST[2:0] are always
outputs from the target (North Bridge logic) and inputs to
the master (graphics controller).
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5.2 VIA K8N800 North Bridge(3)
V-Link Interface
Signal Name
Dedicated Digital Video Port 0 (DVP0) – TMDS Interface
Pin #
I/O Signal Description
DVP0D11/ TVD11
DVP0D10/ TVD10
DVP0D9 / TVD9
DVP0D8 / TVD8
DVP0D7 / TVD7
DVP0D6 / TVD6
DVP0D5 / TVD5
DVP0D4 / TVD4
DVP0D3 / TVD3
DVP0D2 / TVD2
DVP0D1 / TVD1
DVP0D0 / TVD0
DVP0HS / TVHS
Signal Name
M1
M3
M2
L1
M4
L3
L2
K1
L4
K3
K2
J1
N4
O
O
Complement Strobe from Client to Host.
DVP0VS / TVVS
N3
O
Digital Video Port 0 Horizontal Sync. Internally pulled
down.
Digital Video Port 0 Vertical Sync. Internally pulled down.
DVP0DE / TVDE
N1
O
Digital Video Port 0 Data Enable. Internally pulled down.
DVP0DET / TVCLKR P4
I
DVP0CLK / TVCLK
O
Digital Video Port 0 Display Detect. If VGA register
3C5.12[5]=0, 3C5.1A[5] will read 1 if display is connected.
Tie to GND if not used.
Digital Video Port 0 Clock. Internally pulled down.
Pin #
I/O
Signal Description
VAD7,
VAD6,
VAD5,
VAD4,
VAD3,
VAD2,
VAD1,
VAD0
VPAR
AF25
AD24
AF20
AE19
AE24
AF24
AD21
AD20
AF19
IO
IO
IO
IO
IO
IO
IO
IO
IO
Address / Data Bus. Also used to pass strap information from
the South Bridge to the North Bridge (the actual straps are on
the indicated South Bridge pin and that information is passed to
the North Bridge at reset time via the VAD pins).
Parity.
VBE#
AE21
IO
Byte Enable.
UPCMD
AF26
I
UPSTB
AE23
I
Command from Client (South Bridge) to Host (North
Bridge).
Strobe from Client to Host.
UPSTB#
AF23
I
Digital Video Port 0 Data. Default output drive is 8 mA. 16
mA may be selected via SR3D[6]=1.
NOTE: DVP0D[6:0] are also used for power-up reset straps
for the embedded graphics controller. Check the Strap Pin
table for details.
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DNCMD
AD23
O
DNSTB
AF22
O
Command from Host (North Bridge) to Client (South
Bridge).
Strobe from Host to Client.
DNSTB#
AD22
O
Complement Strobe from Host to Client.
P3
The terminology ie3C5.nnlg above refers to the VGA iGSequencerl. registers at I/O port 3C5 index
“nn”
SMB / I 2 C Interface
Signal Name
SBPLCLK
GIRDY
SBPLDAT
GC#BE1
SBDDCCLK
GREQ
SBDDCDAT
GGNT
SPCLK[2:1]
SPDAT[2:1]
Pin #
I/O
Signal Description
/ AC10
I/O
I 2 C Serial Bus Clock for Panel (Muxed on AGP Bus Pins).
/ AF11
I/O
I 2 C Serial Bus Data for Panel (Muxed on AGP Bus Pins).
/ Y1
I/O
/ AA3
I/O
I 2 C Serial Bus Clock for CRT DDC (Muxed on AGP Bus
Pins).
I 2 C Serial Bus Data for CRT DDC (Muxed on AGP Bus
Pins).
Serial Port (SMB/I 2 C) Clocks. Clocks for serial data transfer.
SPCLK1 is typically used for I 2 C communications. SPCLK2
is typically used for CRT Display DDC communications.
Serial Port (SMB/I 2 C) Data. Data signals for serial data
transfer. SPDAT1 is typically used for I 2 C communications.
SPDAT2 is typically used for CRT Display DDC
communications.
C2, P2
C1, P1
IO
IO
CRT Interface
Pin #
I/O
Signal Description
AR
AG
AB
RSET
Signal Name
B3
A3
A2
C4
AO
AO
AO
AI
HSYNC
A1
O
Analog Red. Red output to CRT monitor.
Analog Green. Green output to CRT monitor.
Analog Blue. Blue output to CRT monitor.
CRT Output Reference Resistor. Tie to GNDRGB through an
external 90.9 ±1% resistor to
control the "RGB" RAMDAC full-scale current.
Horizontal Sync. Digital output to CRT monitor.
VSYNC
B1
O
Vertical Sync. Digital output to CRT monitor.
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5.2 VIA K8N800 North Bridge(4)
Dedicated Digital Video Port 0 (DVP0) - TV Encoder Interface
Signal Name
Pin #
I/O Signal Description
TVD11 / DVP0D11
TVD10 / DVP0D10
TVD9 / DVP0D9
TVD8 / DVP0D8
TVD7 / DVP0D7
TVD6 / DVP0D6
TVD5 / DVP0D5
TVD4 / DVP0D4
TVD3 / DVP0D3
TVD2 / DVP0D2
TVD1 / DVP0D1
TVD0 / DVP0D0
TVHS / DVP0HS
M1
M3
M2
L1
M4
L3
L2
K1
L4
K3
K2
J1
N4
O
O
TVVS / DVP0VS
N3
O
TVDE / DVP0DE
N1
O
AGP-Multiplexed Digital Video Port 1 (GDVP1) – TMDS Interface
AGP Name
Pin # I/O Signal Description
TV Encoder 0 Horizontal Sync. Internally pulled down.
GDVP1D11
GDVP1D10
GDVP1D9
GDVP1D8
GDVP1D7
GDVP1D6
GDVP1D5
GDVP1D4
GDVP1D3
GDVP1D2
GDVP1D1
GDVP1D0
GDVP1HS
Signal Name
GC#BE3
GD26
GD24
GD30
GD28
GD29
GSBA4#
GD27
GSBA5#
GSBSTBS
GSBSTBF
GSBA2#
GSBA3#
AC7 O
AE6
AF6
AE4
AF5
AF4
AF2
AD5
AD3
AE1
AF1
AD1
AD2 O
Horizontal Sync.
TV Encoder 0 Vertical Sync. Internally pulled down.
GDVP1VS
GSBA0#
AC2 O
Vertical Sync.
TV Encoder 0 Display Enable. Internally pulled down.
GDVP1DE
TV Encoder 0 Data.
To configure DVP0 as a TV Out interface port, pins
DVP0D[6:5] must be strapped high.
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Note: One TV Encoder interface is supported through either
DVP0 or GDVP1.
Data.
GSBA1#
AC3 O
Data Enable.
TV Encoder 0 Clock Return. Input from TV encoder.
Internally pulled
down.
TVCLK / DVP0CLK P3
O
TV Encoder 0 Clock Out. Output to TV encoder. Internally
pulled
down.
The above pins may be connected to an external TV Encoder chip such as a VIA VT1622A or
VT1622AM for driving a TV set.
I/O pads for the pins on this page are powered by VCCGFX (3.3V I/O).
GDVP1DET
GD31
AD4 I
GDVP1CLK
GSBA6#
AE3 O
Display Detect. If VGA register 3C5.3E[0] = 1,
3C5.1A[4] will read 1 if a display is connected.
Tie to GND if not used.
Clock.
GDVP1CLK#
GSBA7#
AF3 O
Clock Complement.
Analog Power / Ground
Reference Voltages
TVCLKR / DVP0DET P4
Signal Name
I
Pin #
I/O Signal Description
VCCATX
C22
P
GNDATX
C21
P
VCCARX
E25
P
GNDARX
E26
P
Analog Power for HT Transmit. 3.3V ±5%. Connect
through a ferrite bead for isolation of digital switching noise.
Analog Ground for HT Transmit. Connect to main ground
plane through a ferrite bead for isolation of digital switching
noise.
Analog Power for HT Receive. 3.3V ±5%. Connect through
a ferrite bead for isolation of digital switching noise.
Analog Ground for HT Receive. Connect to main ground
plane through a ferrite bead for isolation of digital switching
noise.
The GDVP1 Digital Video Port is supported through multiplexing its interface signal pins with AGP
pins. GDVP1 can be configured as either a TMDS transmitter interface port or a TV Encoder interface
port. (see the TMDS Transmitter Interface and TV Encoder Interface pin lists below for details).
Pin #
I/O Signal Description
VLVREF
Signal Name
AF21
P
AGPVREF[1:0]
AC6, P
AC13
V-Link Voltage Reference. 0.625V ±2% derived using a
resistive voltage divider (3K §Ù to
2.5V and 1K §Ù to ground). See Design Guide for details.
AGP Voltage Reference. 0.5 VCCQQ (0.75V) for AGP 2.0
(4x transfer mode) and 0.23 VCCQQ (0.35V) for AGP 3.0 (8x
transfer mode). See the Design Guide for additional
information and circuit implementation details..
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5.2 VIA K8N800 North Bridge(5)
AGP-Multiplexed Digital Video Port 1 (GDVP1) – TV Encoder
Signal Name
AGP Name Pin # I/O Signal Description
GTVD11 / GDVP1D11, GC#BE3
GTVD10 / GDVP1D10,
GD26
GTVD9 / GDVP1D9,
GD24
GTVD8 / GDVP1D8,
GD30
GTVD7 / GDVP1D7,
GD28
GTVD6 / GDVP1D6,
GD29
GTVD5 / GDVP1D5,
GSBA4#
GTVD4 / GDVP1D4,
GD27
GTVD3 / GDVP1D3,
GSBA5#
GTVD2 / GDVP1D2,
GSBSTBS
GTVD1 / GDVP1D1,
GSBSTBF
GTVD0 / GDVP1D0
GSBA2#
GTVHS / GDVP1HS
GSBA3#
AC7 O
AE6
AF6
AE4
AF5
AF4
AF2
AD5
AD3
AE1
AF1
AD1
AD2 O
Horizontal Sync. Internally pulled down.
GTVVS / GDVP1VS
GSBA0#
AC2 O
Vertical Sync. Internally pulled down.
GTVDE / GDVP1DE
GSBA1#
AC3 O
Display Enable. Internally pulled down.
Data.
Signal Name
AGP Name Pin # I/O Signal Description
GD11
GD13
GD14
GD15
GC#BE2
GD16
GD17
GD18
GD23
GD20
GD22
GADSSTB1
F
GD1
GD0
GD3
GD4
GD5
GD6
GD7
GADSTB0F
GC#BE0
GADSTB0S
GD10
GD12
AE13 O
AD12
AF12
AE12
AD11
AD10
AE10
AF10
AD8
AF9
AE9
AE7
AD18
AF18
AF17
AD17
AD16
AE16
AF16
AE15
AD15
AF15
AD13
AF13
Flat Panel Data. For 24-bit or dual 12-bit flat
panel display modes.
Two FPD interface modes, 24-bit and dual
12-bit, are supported.
Strapping pin DVP0D4 is used to select the
interface mode to the LVDS transmitter chip:
Strap High (3C5.12[4]=1): 24-bit
Strap Low (3C5.12[4]=0): Dual 12-bit
In in24-bitl] mode, only one set of control pins
is required. However, in dual 12-bit mode, the
K8N800 Version CD provides two sets of
control signals that are required for certain
LVDS transmitter chips.
In 24-bit mode, two operating modes are
supported:
3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=0
Double data rate: each rising & falling clock
edge transmits a complete 24-bit pixel
3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=1
Single data rate: each clock rising edge
transmits a complete 24-bit pixel
In dual 12-bit mode,
3C5.12[4]=0 & 3x5.88[2] = 1
Each rising and falling clock edge transmits half
(12 bits) of two 24-bit pixels
FPHS
GFRAME
AC9 O
FPVS
GDEVSEL
AC11 O
FPDE
GD19
AD9 O
FPDET
GADSTB1S
AF7 I
Flat Panel Horizontal Sync. 24-bit mode or
port 0 of dual 12-bit mode.
Flat Panel Vertical Sync. 24-bit mode or port 0
of dual 12-bit mode.
Flat Panel Data Enable. 24-bit mode or port 0
of dual 12-bit mode
Flat Panel Detect. 24-bit mode or port 0 of dual
12-bit mode
Flat Panel Clock. 24-bit mode or port 0 of dual
12-bit mode
Flat Panel Clock Complement. 24-bit mode or
port 0 of dual 12-bit
Mode.
FPD23 / FPD0D11,
FPD22 / FPD0D10,
FPD21 / FPD0D09,
FPD20 / FPD0D08,
FPD19 / FPD0D07,
FPD18 / FPD0D06,
FPD17 / FPD0D05,
FPD16 / FPD0D04,
FPD15 / FPD0D03,
FPD14 / FPD0D02,
FPD13 / FPD0D01,
FPD12 / FPD0D00,
FPD11 / FPD1D11,
FPD10 / FPD1D10,
FPD09 / FPD1D09,
FPD08 / FPD1D08,
FPD07 / FPD1D07,
FPD06 / FPD1D06,
FPD05 / FPD1D05,
FPD04 / FPD1D04,
FPD03 / FPD1D03,
FPD02 / FPD1D02,
FPD01 / FPD1D01,
FPD00 / FPD1D00
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GTVCLKR
/
GD31
AD4 I
Clock In. Input from TV encoder. Internally
GDVP1DET
pulled down.
GTVCLK
/ GSBA6#
AE3 O
Clock Out. Output to TV encoder. Internally
GDVP1CLK
pulled down.
GTVCLK#
/ GSBA7#
AF3 O
Clock Out Complement. Output to TV
GDVP1CLK#
encoder. Internally pulled down.
The above pins may be connected to an external TV Encoder chip such as a VIA VT1623 or
VT1623M for driving a TV set.
I/O pads for the pins on this page are powered by VCC15AGP (1.5V I/O).
Flat Panel Power Control (Muxed with AGP)
Signal Name
24-Bit / Dual 12-Bit Flat Panel Display Interface
AGP Name Pin # I/O Signal Description
ENAVDD
GST1
AA1 IO
Enable Panel VDD Power.
FPCLK
GD21
AF8 O
ENAVEE
GST0
AA2 IO
Enable Panel VEE Power.
GST2
AB1 IO
FPCLK#
GWBF
AC1 O
ENABLT
Enable Panel Back Light.
Note: I/O pads for all pins on this page are powered by VCC15AGP (i.e., 1.5V I/O).
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5.2 VIA K8N800 North Bridge(6)
24-Bit / Dual 12-Bit Flat Panel Display Interface (Continued)
Signal Name
FP1HS
GD9
AD14 O
FP1VS
GPAR
AC16 O
FP1DE
GSERR
AC15 O
FP1DET
GD8
AF14 I
FP1CLK
GD2
AE18 O
FP1CLK#
GSTOP
AC12 O
Flat Panel Horizontal Sync. For port 1 in dual
12-bit mode.
Flat Panel Vertical Sync. For port 1 in dual
12-bit mode.
Flat Panel Data Enable. For port 1 in dual
12-bit mode.
Flat Panel Detect. For port 1 in dual 12-bit
mode.
Flat Panel Clock. For port 1 in dual 12-bit
mode.
Flat Panel Clock Complement. For port 1 in
dual 12-bit mode.
Compensation
Signal Name
Pin #
I/O Signal Description
RPCOMP
D25
AI
RNCOMP
D26
AI
RTCOMP
Clock, Reset, Power Control, General Purpose I/O, Interrupts and Test
AGP Name Pin # I/O Signal Description
C26
AI
VLPCOMP
AD19 AI
AGPNCOMP
W1
AI
AGPPCOMP
V1
AI
Signal Name
GCLK
Pin #
I/O Signal Description
A11
I
AGP Clock. 66 MHz clock for AGP logic.
DCLKI
D7
I
Dot Clock (Pixel Clock) In. For spread spectrum.
DCLKO
A7
O
Dot Clock (Pixel Clock) Out. For spread spectrum.
RESET#
AD25 I
PWROK
AE26
SUSST#
AD26 I
TESTIN
AC26 I
BISTIN
D3
DEBUG
AC17 I
XIN
C6
I
Reset. Input from the South Bridge chip. 3.3V tolerant input.
When asserted, this signal resets the chip and sets all register
bits to the default value. The rising edge of this signal is used
to sample all power-up strap options In addition, HTRST# is
driven active to reset the K8 CPU.
Power OK. Driven by South Bridge PWROK output from the
power supply PWRGOOD input to the South Bridge.
Suspend Status. For implementation of the
Suspend-to-DRAM feature. Connect to an external pull-up to
disable.
Test In. This pin is used for testing and must be left
unconnected or tied high (4.7K §Ù to 2.5V) on all board
designs.
Built-In-Self-Test In. Reserved for test. Connect to GND for
normal operation.
Debug. Reserved for test. Connect to ground for normal
operation.
Reference Frequency In. 14.31818 MHz.
INTA#
E7
O
PCI Interrupt Output A. Connect to the South Bridge.
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Host CPU P-Channel Compensation. Connect 50 §Ù 1%
resistor to GND.
Host CPU N-Channel Compensation. Connect 50 §Ù 1%
resistor to VCCHT.
Host CPU Compensation. Connect 100 §Ù 1% resistor to
VCCHT.
V-Link P-Channel Compensation. Connect 360 §Ù 1%
resistor to ground.
AGP N-Channel Compensation. Connect 60.4 §Ù 1%
resistor to VCCAGP.
AGP P-Channel Compensation. Connect 60.4 §Ù 1%
resistor to GND.
I
I
GPOUT
D2
O
General Purpose Output.
GPO0
N2
O
General Purpose Output.
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5.2 VIA K8N800 North Bridge(7)
Integrated Graphics Power and Ground
Pin #
I/O Signal Description
VCCDAC
Signal Name
B2
P
GNDDAC
C3, D4 P
VCCRGB
A4
P
GNDRGB
B4
P
VCCPLL1
D5
P
GNDPLL1
C5
P
VCCPLL2
A5
P
GNDPLL2
B5
P
VCCPLL3
A6
P
GNDPLL3
B6
P
DAC Voltage. 3.3V ±5% connected via ferrite bead for
isolation of digital switching noise.
DAC Ground. Connect to main ground plane.
Power for CRT RGB Outputs. 3.3V ±5% connected via
ferrite bead for isolation of digital switching noise
Connection point for RGB Load Resistors. Connect to main
ground plane via ferrite bead for isolation of digital switching
noise.
Power for Graphics Controller PLL1 (“E-Clock”). 1.5V
±5% connected via ferrite bead for isolation of digital
switching noise.
Ground for Graphics Controller PLL1 (“E-Clock”).
Connect to main ground plane via ferrite bead for isolation of
digital switching noise.
Power for Graphics Controller PLL2 (“D-Clock”). 1.5V
±5% connected via ferrite bead for isolation of digital
switching noise.
Ground for Graphics Controller PLL2 (“D-Clock”).
Connect to main ground plane via ferrite bead for isolation of
digital switching noise.
Power for Graphics Controller PLL3 (“LCD Clock”). 1.5V
±5% connected via ferrite bead for isolation of digital
switching noise.
Ground for Graphics Controller PLL3 (“LCD Clock”).
Connect to main ground plane via ferrite bead for isolation of
digital switching noise.
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8399 N/B Maintenance
5.3 VIA VT8235CD South Bridge(1)
V-Link Interface
Signal Name
Pin #
I/O
VD[7:0]
(see pin IO
list)
CPU Interface
Signal Name Pin # I/O
Signal Description
VBE#
G24
IO
Data Bus. These pins are also used to send strap information to
the chipset north
bridge. At power up, VD7 reflects the state of a strap on
SDCS3#, VD[6:4] reflect
the state of straps on pins SDA[2:0], and VD[3:0] reflect the
state of straps on pins
Strap_VD3-0. The specific interpretation of these straps is north
bridge chip design
dependent.
Parity. If the VPAR function is implemented in a compatible
manner on the north
bridge, this pin should be connected to the north bridge VPAR
pin (P4X333,
P4X400, P4X800, KT400). If VPAR is not implemented in the
north bridge chip or
is incompatible with the 8235CE (4x V-Link north bridges)
connect this pin to an
8.2K pullup to 2.5V (Pro266, Pro266T, KT266, KT266A,
KT333, P4X266, PN266,
KN266, KM266, P4M266, P4N266). See app note AN222 for
details.
Byte Enable.
VCLK
L22
I
V-Link Clock.
UPCMD
K23
O
Command from Client-to-Host.
DNCMD
K25
I
Command from Host-to-Client.
UPSTB
J26
O
Strobe from Client-to-Host.
VPAR
F24
IO
A20M#
U26
OD
Signal Description
A20 Mask. Connect to A20 mask input of the CPU to control
address bit-20 generation.
Logical combination of the A20GATE input (from internal or
external keyboard controller)
and Port 92 bit-1 (Fast_A20).
Numerical Coprocessor Error. This signal is tied to the
coprocessor error signal on the
CPU. Internally generates interrupt 13 if active. Output voltage
swing is programmable tot
1.5V or 2.5V by Device 17 Function 0 Rx67[2].
Ignore Numeric Error. This pin is connected to the CPU
iPignore errorlr pin.
Initialization. The VT8235 Version CE asserts INIT# if it
detects a shut-down special
cycle on the PCI bus or if a soft reset is initiated by the register
CPU Interrupt. INTR is driven by the VT8235 Version CE to
signal the CPU that an
interrupt request is pending and needs service.
Non-Maskable Interrupt. NMI is used to force a
non-maskable interrupt to the CPU. The
VT8235 Version CE generates an NMI when PCI bus SERR# is
asserted.
Sleep. Used to put the CPU to sleep.
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UPSTB#
J24
O
Complement Strobe from Client-to-Host.
DNSTB
K26
I
Strobe from Host-to-Client.
DNSTB#
H24
I
Complement Strobe from Host-to-Client.
FERR#
U24
I
IGNNE#
T24
OD
INIT#
R26
OD
INTR
T25
OD
NMI
T26
OD
SLP#
V26
OD
U25
OD
System Management Interrupt. SMI# is asserted by the
VT8235 Version CE to the CPU
in response to different Power-Management events.
R24
OD
Stop Clock. STPCLK# is asserted by the VT8235 Version CE
STPCLK#
to the CPU to throttle the
processor clock.
Note: Connect each of the above signals to 150 §Ù pullup resistors to VCC_CMOS (see Design Guide).
SMI#
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8399 N/B Maintenance
5.3 VIA VT8235CD South Bridge(2)
Advanced Programmable Interrupt Controller (APIC) Interface
Signal Name Pin # I/O
Signal Description
APICD1
T23
O
Internal APIC Data 1. Function 0 Rx58[6] = 1
APICD0
R25
O
Internal APIC Data 0. Function 0 Rx58[6] = 1
APICCLK
U23
I
APIC Clock.
PCI Bus Interface
Signal Name Pin # I/O
AD[31:0]
(see
IO
pinlist)
CBE[3:0]#
M3, L4, IO
C1, E2
OD
GHI# / GPI22/ R22
GPO22
OD
DPSLP#
/ P21
GPI23/ GPO23
CPUMISS
/ Y1
GPI17
AGPBZ# / GPI6 AD10
OD
I
I
Address / Data Bus. Multiplexed address and data. The address
is driven with FRAME#assertion and data is driven or received
in following cycles.
Command / Byte Enable. The command is driven with
FRAME# assertion. Byteenables corresponding to supplied or
requested data are driven on following clocks.
Device Select. The VT8235 Version CE asserts this signal to
claim PCI transactions
through positive or subtractive decoding. As an input,
DEVSEL# indicates the response
to a VT8235 Version CE-initiated transaction and is also
sampled when decoding whether
to subtractively decode the cycle.
Frame. Assertion indicates the address phase of a PCI transfer.
Negation indicates that
one more data transfer is desired by the cycle initiator.
Initiator Ready. Asserted when the initiator is ready for data
transfer.
Target Ready. Asserted when the target is ready for data
transfer.
Stop. Asserted by the target to request the master to stop the
current transaction.
System Error. SERR# can be pulsed active by any PCI device
that detects a system error
condition. Upon sampling SERR# active, the VT8235 Version
CE can be programmed to
generate an NMI to the CPU.
Parity Error. PERR#, sustained tri-state, is only for the
reporting of data parity errors
during all PCI transactions except for a Special Cycle.
Parity. A single parity bit is provided over AD[31:0] and
C/BE[3:0]#.
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DEVSEL#
H2
IO
FRAME#
J1
IO
IRDY#
J2
IO
TRDY#
H1
IO
STOP#
K4
IO
SERR#
C2
I
PERR#
C3
_
PAR
F4
IO
CPU Speed Control Interface
Signal Name Pin # I/O
Signal Description
VRDSLP
/ AB9
GPI29/ GPO29
Signal Description
Voltage Regulator Deep Sleep. Connected to the CPU voltage
regulator. High selectsthe proper voltage for deep sleep mode.
This pin performs the VRDPSLP function if
Function 0 RxE5[3] = 0.
CPU Speed Select. Connected to the CPU voltage regulator,
used to select high speed (L) or low speed (H). This pin
performs the GHI# function if Function 0 RxE5[3] = 0.
CPU Deep Sleep. This pin performs the DPSLP# function if
Device 17 Function 0RxE5[3]=0.
CPU Missing. Used to detect the physical presence of the CPU
chip in its socket. High
indicates no CPU present. Connect to the CPUMISS pin of the
CPU socket. The state of
this pin may be read in the SMBus 2 registers. This pin may be
used as CPUMISS and
GPI17 at the same time.
AGP Busy. Low indicates that an AGP master cycle is in
progress (CPU speed transitions
will be postponed if this input is asserted low). Connected to the
AGP Bus AGPBZ# pin.
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5.3 VIA VT8235CD South Bridge(3)
PCI Bus Interface (Continued)
Signal Name Pin # I/O
Signal Description
INTA#
INTB#
INTC#
INTD#
INTE# / GPI12, /
GPO12,
INTF# / GPI13, /
GPO13,
INTG# / GPI14, /
GPO14,
INTH# / GPI15, /
GPO15
A4
B4
B5
C4
D4
REQ5# / GPI7,
REQ4#,
REQ3#,
REQ2#,
REQ1#,
REQ0#
GNT5# / GPO7,
GNT4#,
GNT3#,
GNT2#,
GNT1#,
GNT0#
PCIRST#
R3
P3
D5
C5
B6
A5
R2
R4
E5
C6
D6
A6
R1
O
PCICLK
R23
I
PCKRUN#
AB7
IO
I
E4
A3
B3
I
O
LAN Controller - Media Independent Interface (MII)
Signal Name Pin # I/O PU Signal Description
PCI Interrupt Request. The INTA# through INTD# pins are
typically connected to thePCI bus INTA#-INTD# pins per the
table below. INTE-H# are enabled by setting Device17,
Function 0 Rx5B[1] = 1. BIOS settings must match the physical
connection method.
INTA# INTB# INTC# INTD#
PCI Slot 1 INTA# NTB# INTC# INTD#
PCI Slot 2 INTB# INTC# INTD# INTE#
PCI Slot 3 INTC# INTD# INTE# INTF#
PCI Slot 4 INTD# INTE# INTF# INTG#
PCI Slot 5 INTE# INTF# INTG# INTH#
PCI Slot 6 INTF# INTG# INTH# INTA#
MCOL
B11
I
PD MII Collision Detect. From the external PHY.
MCRS
A11
I
PCI Request. These signals connect to the VT8235 Version CE
from each PCI slot (oreach PCI master) to request the PCI bus.
To use pin R3 as REQ5#, Function 0 RxE4 mustbe set to 1
otherwise this pin will function as General Purpose Input 7.
PD MII Carrier Sense. Asserted by the external PHY when
the media is
active.
PD MII Management Data Clock. Sent to the external PHY
as a timing
reference for MDIO
PD MII Management Data I/O. Read from the MDI bit or
written to the
MDO bit.
PD MII Receive Clock. 2.5 or 25 MHz clock recovered by the
PHY.
PD MII Receive Data. Parallel receive data lines driven by the
external
PHY synchronous with MRXCLK.
PD MII Receive Data Valid.
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PCI Grant. These signals are driven by the VT8235 Version
CE to grant PCI access to aspecific PCI master. To use pin R2
as GNT5#, Function 0 RxE4 must be set to 1otherwise this pin
will function as General Purpose Output 7.
MDCK
A7
O
MDIO
B7
IO
MRXCLK
C9
I
MRXD[3-0]
C7, A8, I
B8, C8
MRXDV
D8
I
MRXERR
D10
I
RAMVCC
PD MII Receive Error. Asserted by the PHY when it detects a
data
decoding error.
C10
I
PD MII Transmit Clock. Always active 2.5 or 25 MHz clock
supplied by
the PHY.
A9, B9, O
PD MII Transmit Data. Parallel transmit data lines
B10,
synchronized to
A10
MTXCLK.
C11
O
PD MII Transmit Enable. Signals that transmit is active from
the MII
port to the PHY.
D9, E9, Power
MII Interface Power. 3.3V ±5%.
E10,
E11
D12,
MII Suspend Power. 2.5V ±5%.
Power
E12
Power For Internal LAN RAM. 2.5V ±5%.
E7
Power
RAMGND
E6
Power
MTXCLK
MTXD[3-0]
PCI Reset. This signal is used to reset devices attached to the
PCI bus.
PCI Clock. This signal provides timing for all transactions on
the PCI Bus.
PCI Bus Clock Run. This signal indicates whether the PCI
clock is or will be stopped
(high) or running (low). The VT8235 Version CE drives this
signal low when the PCI
clock is running (default on reset) and releases it when it stops
the PCI clock. External
devices may assert this signal low to request that the PCI clock
be restarted or prevent it
from stopping. Connect this pin to ground using a 100 §Ù
resistor if the function is not
used. Refer to the ihPCI Mobile Design Guidelo and applicable
VIA North Bridge Design
Guide (KT400A, CLE266, or P4X400) for more details.
MTXENA
MIIVCC
MIIVCC25
Ground For Internal LAN RAM.
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5.3 VIA VT8235CD South Bridge(4)
Serial EEPROM Interface
Signal Name Pin # I/O PU Signal Description
Universal Serial Bus 2.0 Interface
Signal Name Pin # I/O Signal Description
EECS#
D11
O
Serial EEPROM Chip Select.
USBP0+
EECK
C12
O
Serial EEPROM Clock.
USBP0Œ
EEDO
B12
I
Serial EEPROM Data Output. Connect to EEPROM Data
Out pin.
Serial EEPROM Data Input. Connect to EEPROM Data
In pin.
USBP1+
USBP1Œ
USBP2+
EEDI
A12
O
E20
IO
USB 2.0 Port 0 Data +
D20
IO
USB 2.0 Port 0 Data Œ
A20
IO
USB 2.0 Port 1 Data +
B20
IO
USB 2.0 Port 1 Data Œ
E18
IO
USB 2.0 Port 2 Data +
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Low Pin Count (LPC) Interface
Signal Name Pin # I/O PU Signal Description
USBP2Œ
D18
IO
USB 2.0 Port 2 Data Œ
USBP3+
A18
IO
USB 2.0 Port 3 Data +
USBP3Œ
B18
IO
USB 2.0 Port 3 Data Œ
USBP4+
D16
IO
USB 2.0 Port 4 Data +
USBP4Œ
E16
IO
USB 2.0 Port 4 Data Œ
USBP5+
A16
IO
USB 2.0 Port 5 Data +
LFRM#
AF6
IO
LPC Frame.
LREQ#
AE6
IO
LPC DMA / Bus Master Request.
USBP5Œ
B16
IO
AD7,
IO
PU LPC Address / Data.
AE7,
AF7,
AD8
Note: Connect the LPC interface LPCRST# (LPC Reset) signal to PCIRST#
USB 2.0 Port 5 Data Œ
USBCLK
E23
I
USB 2.0 Clock. 48MHz clock input for the USB interface
USBOC0#
C26
I
USB 2.0 Port 0 Over Current Detect. Port 0 is disabled if low.
USBOC1#
D24
I
USB 2.0 Port 1 Over Current Detect. Port 1 is disabled if low.
USBOC2#
B26
I
USB 2.0 Port 2 Over Current Detect. Port 2 is disabled if low.
USBOC3#
C25
I
USB 2.0 Port 3 Over Current Detect. Port 3 is disabled if low.
USB 2.0 Port 4 Over Current Detect. Port 4 is disabled if low.
LAD[3-0]
System Management Bus (SMB) Interface (I 2 C Bus)
Signal Name Pin # I/O Signal Description
USBOC4#
B24
I
USBOC5#
A24
I
USB 2.0 Port 5 Over Current Detect. Port 5 is disabled if low.
USBVCC
(see pin
list)
(see pin
list)
C24
Pow
er
Pow
er
Pow
er
Pow
er
Pow
er
USB 2.0 Port Differential Output Interface Logic Voltage. 3.3V
SMBCK1
AC4
IO
SMB / I 2 C Channel 1 Clock.
SMBCK2 /
GPI27 / GPO27
SMBDT1
AC3
IO
SMB / I 2 C Channel 2 Clock. Rx95[2] = 0
AB2
IO
SMB / I 2 C Channel 1 Data.
SMBDT2 /
GPI26 / GPO26
SMBALRT#
AD1
IO
SMB / I 2 C Channel 2 Data. Rx95[2] = 0
VCCUPLL
AB1
I
SMB Alert. (enabled by System Management Bus I/O space
Rx08[3] =
1) When the chip is enabled to allow it, assertion generates an IRQ
or
SMI interrupt or a power management resume event. Connect to a
10K
ohm pullup to VSUS33 if not used.
GNDUPLL
USBGND
VSUSUSB
A23,
B23
C23,
D23
USB 2.0 Port Differential Output Interface Logic Ground.
USB 2.0 Suspend Power. 2.5V ±5%.
USB 2.0 PLL Analog Voltage. 2.5V ±5%.
USB 2.0 PLL Analog Ground.
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8399 N/B Maintenance
5.3 VIA VT8235CD South Bridge(5)
UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface
Signal Name Pin # I/O Signal Description
PDRDY
/PDDMARDY
/PDSTROBE
SDRDY
/SDDMARDY
/SDSTROBE
Y22
AF17
I
I
PDIOR#
/PHDMARDY
/PHSTROBE
W26
O
SDIOR#
/SHDMARDY
/SHSTROBE
AF23
O
PDIOW#
/PSTOP
Y25
O
SDIOW#
/SSTOP
AE23
O
PDDRQ
Y23
I
SDDRQ
AD17
I
EIDE Mode: Primary I/O Channel Ready. Device ready
indicator UltraDMA Mode: Primary Device DMA Ready.
Output flow control. The device mayassert DDMARDY to pause
output transfers Primary Device Strobe. Input data strobe (both
edges). The device may stop DSTROBE to pause input data
transfers
EIDE Mode: Secondary I/O Channel Ready. Device ready
indicator UltraDMA Mode: Secondary Device DMA Ready.
Output flow control. The devicemay assert DDMARDY to pause
output transfers Secondary Device Strobe. Input data strobe (both
edges). The device may stop DSTROBE to pause input data
transfers
EIDE Mode: Primary Device I/O Read. Device read strobe
UltraDMA Mode: Primary Host DMA Ready. Primary channel
input flow control. Thehost may assert HDMARDY to pause input
transfers Primary Host Strobe. Output data strobe (both edges).
The host may stop HSTROBE to pause output data transfers
EIDE Mode: Secondary Device I/O Read. Device read strobe
UltraDMA Mode: Secondary Host DMA Ready. Input flow
control. The host mayassert HDMARDY to pause input transfers
Host Strobe B. Output strobe (both edges). The host may stop
HSTROBE to pause output data transfers
EIDE Mode: Primary Device I/O Write. Device write strobe
UltraDMA Mode: Primary Stop. Stop transfer: Asserted by the
host prior to initiation of
an UltraDMA burst; negated by the host before data is transferred in
an UltraDMA burst. Assertion of STOP by the host during or after
data transfer in UltraDMA mode signals the termination of the
burst.
EIDE Mode: Secondary Device I/O Write. Device write strobe
UltraDMA Mode: Secondary Stop. Stop transfer: Asserted by the
host prior to initiation of an UltraDMA burst; negated by the host
before data is transferred in an UltraDMA burst. Assertion of STOP
by the host during or after data transfer in UltraDMA mode signals
the termination of the burst.
Primary Device DMA Request. Primary channel DMA request
UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface (Continued)
Signal Name Pin # I/O Signal Description
PDDACK#
Y24
O
Primary Device DMA Acknowledge. Primary channel DMA
acknowledge
Secondary Device DMA Acknowledge. Secondary channel DMA
acknowledge
Primary Channel Interrupt Request.
SDDACK#
AD23
O
IRQ14
AD24
I
IRQ15
AE26
I
Secondary Channel Interrupt Request.
PDCS1#
V22
O
PDCS3#
V23
O
SDCS1# / strap
AF25
O
SDCS3# / strap
AF26
O
Primary Master Chip Select. This signal corresponds to CS1FX#
on the primary IDE connector.
Primary Slave Chip Select. This signal corresponds to CS3FX# on
the primary IDE connector.
Secondary Master Chip Select. This signal corresponds to
CS17X# on the secondary IDE connector. Strap low (resistor to
ground) to enable serial EEPROM interface via the MII bus (this
disables the EExx pins). This pin has an internal pullup to default to
serial EEPROM interface via the EExx pins.
Secondary Slave Chip Select. This signal corresponds to CS37X#
on the secondary IDE connector. Strap information is
communicated to the north bridge via VD[7].
Primary Disk Address. PDA[2:0] are used to indicate which byte
in either the ATA command block or control block is being
accessed.
Secondary Disk Address. SDA[2:0] are used to indicate which
byte in either the ATA command block or control block is being
accessed. Strap information is communicated to the north bridge via
VD[6:4].
Primary Disk Data.
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Secondary Device DMA Request. Secondary channel DMA
request
W24,
V25,
W23
SDA[2-0] / strap AE24,
AC22,
AF24
PDA[2-0]
PDD[15-0]
SDD[15-0]
O
O
(see pin IO
list)
(see pin IO
list)
Secondary Disk Data.
Serial IRQ
Signal Name Pin # I/O Signal Description
SERIRQ
AD9
I
Serial IRQ. This pin has an internal pull-up resistor.
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5.3 VIA VT8235CD South Bridge(6)
AC97 Audio / Modem Interface
Signal Name Pin # I/O Signal Description
Internal Keyboard Controller
Signal Name Pin # I/O PU Signal Description
MSCK / IRQ1
ACRST#
T3
O
AC97 Reset.
ACBTCK
T1
I
AC97 Bit Clock.
ACSYNC
T2
O
AC97 Sync.
ACSDO
U2
O
AC97 Serial Data Out.
ACSDIN0
(VSUS33)ƒ
ACSDIN1
(VSUS33)ƒ
ACSDIN2 /
GPIO20 / PCS0#
ACSDIN3 /
GPIO21 / PCS1#
/ SLPBTN#
U3
I
AC97 Serial Data In 0.
V2
I
AC97 Serial Data In 1.
U1
I
AC97 Serial Data In 2. RxE4[6]=0,E5[1]=0, PMIO Rx4C[20]=1
V3
I
AC97 Serial Data In 3. RxE4[6]=0,E5[2]=0, PMIO Rx4C[21]=1
AC5
I
PWROK#
AF1
O
PCIRST#
R1
O
OSC
AB8
I
RTCX1
AE4
I
Power Good. Connected to the Power Good signal on the
Power Supply. Internal logic
powered by VBAT.
Power OK. Internal logic powered by VSUS33.
RTCX2
AF3
O
TEST
AE9
I
PCI Reset. Active low reset signal for the PCI bus. The
VT8235 Version CE will assert
this pin during power-up or from the control register.
Oscillator. 14.31818 MHz clock signal used by the internal
Timer.
RTC Crystal Input: 32.768 KHz crystal or oscillator
input. This input is used for the
internal RTC and power-well power management logic and
is powered by VBAT.
RTC Crystal Output: 32.768 KHz crystal output. Internal
logic powered by VBAT.
Test.
AF9
O
Test Pin Output. Output pin for test mode.
(see pin
list)
–
No Connect. Do not connect.
TPO
NC
IO / I
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Resets, Clocks, and Power Status
Signal Name Pin #
I/O
Signal Description
PWRGD
PU MultiFunction Pin (Internal mouse controller enabled by
Rx51[1])
Rx51[2]=1 Mouse Clock. From internal mouse controller.
Rx51[2]=0 Interrupt Request 1. Interrupt input 1.
MSDT / IRQ12
W2
IO / I PU MultiFunction Pin (Internal mouse controller enabled by
Rx51[1])
Rx51[2]=1 Mouse Data. From internal mouse controller.
Rx51[2]=0 Interrupt Request 12. Interrupt input 12.
KBCK / KA20G
W3
IO / I PU MultiFunction Pin (Internal keyboard controller enabled
by
Rx51[0])
Rx51[0]=1 Keyboard Clock. From internal keyboard
controller
Rx51[0]=0 Gate A20. Input from external keyboard
controller.
KBDT / KBRC
V1
IO / I PU MultiFunction Pin (Internal keyboard controller enabled
by
Rx51[0])
Rx51[0]=1 Keyboard Data. From internal keyboard
controller.
Rx51[0]=0 Keyboard Reset. From external keyboard
controller
(KBC) for CPURST# generation
KBCS# / strap
Keyboard Chip Select (Rx51[0]=0). To external keyboard
AF10
O
controller chip. Strap high to enable LPC BIOS ROM.
Note: KBCK, KBDT, MSCK, and MSDT are powered by the VSUS33 suspend voltage plane.
W1
Speaker
Signal Name
SPKR / strap
Pin #
AF8
I/O PU Signal Description
O
Speaker. Strap low to enable (high to disable) CPU
frequency
strapping.
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5.3 VIA VT8235CD South Bridge(7)
General Purpose Inputs
Signal Name Pin #
I/O
Signal Description
GPI0 (VBAT)
AE2
I
General Purpose Input 0. Status on PMIO Rx20[0]
GPI1 (VSUS33)
AC2
I
General Purpose Input 1. Status on PMIO Rx20[1]
GPI2 / EXTSMI# AA1
(VSUS33)
GPI3 / RING#
Y2
(VSUS33)
GPI4 / LID#
AC1
(VSUS33)
GPI5 /
V4
BATLOW#
(VSUS33)
GPI6 / AGPBZ# AD10
I
General Purpose Input 2. Status on PMIO Rx20[4]
I
General Purpose Input 3. Status on PMIO Rx20[8]
I
General Purpose Input 4. Status on PMIO Rx20[11]
I
General Purpose Input 5. Status on PMIO Rx20[12]
General Purpose Inputs (Continued)
Signal Name Pin #
I/O
Signal Description
GPI26 / GPO26 /
SMBDT2
(VSUS33)
GPI27 / GPO27 /
SMBCK2
(VSUS33)
GPI28 / GPO28
AD1
I
General Purpose Input 26. Rx95[2] = 1, 95[3] = 0
AC3
I
General Purpose Input 27. Rx95[2] = 1, 95[3] = 0
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General Purpose Input 6. Status on PMIO Rx20[5]
GPI7 / REQ5#
R3
I
General Purpose Input 7. RxE4[2] = 0
GPI12 / GPO12 /
INTE#
GPI13 / GPO13 /
INTF#
GPI14 / GPO14 /
INTG#
GPI15 / GPO15 /
INTH#
GPI16 /
INTRUDER#
(VBAT)
GPI17 /
CPUMISS
GPI18 / THRM#
/ AOLGPI
GPI20 / GPO20 /
ACSDIN2 /
PCS0#
GPI21 / GPO21 /
ACSDIN3 /
PCS1# /
SLPBTN#
GPI22 / GPO22 /
GHI#
GPI23 / GPO23 /
DPSLP#
D4
I
General Purpose Input 12. RxE4[4] = 0, 5B[1]=0
E4
I
General Purpose Input 13. RxE4[4] = 0, 5B[1]=0
A3
I
General Purpose Input 14. RxE4[4] = 0, 5B[1]=0
B3
I
General Purpose Input 15. RxE4[4] = 0, 5B[1]=0
AE1
I
General Purpose Input 16. Status on PMIO Rx20[6]
Y1
I
General Purpose Input 17. Status on PMIO Rx20[5]
Y4
I
General Purpose Input 18. Rx8C[3] = 0
U1
I
General Purpose Input 20. RxE4[6]=1, E5[1]=0,
PMIO 4C[20] = 1
V3
I
General Purpose Input 21. RxE4[6]=1, E5[2]=0
PMIO 4C[21] = 1
R22
I
P21
I
General Purpose Input 22. RxE5[3] = 1, PMIO 4C[22] =
1
General Purpose Input 23. RxE5[3] = 1, PMIO 4C[23] =
1
General Purpose Input 28. RxE5[3] = 1, PMIO 4C[28] =
1
GPI29 / GPO29 / AB9
General Purpose Input 29. RxE5[3] = 1, PMIO 4C[29] =
I
VRDSLP
1
Note: Register references above are Device 17 Function 0 unless indicated otherwise.
Note: Default pin function is underlined in the signal name column above.
Note: Input pin status for the above GPI pins 31-0 is also available on PMIO Rx4B-48[31-0]
Note: See also Power Management I/O register Rx50 for input pin change status for GPI16-19 and
24-27
Note: See also Power Management I/O register Rx52 for SCI/SMI select for GPI16-19 and 24-27
Note: See also Power Management I/O register Rx4C. General purpose input pins 20-31 are shared
with OD (open drain) general
AC8
I
Programmable Chip Selects
Signal Name Pin #
I/O
PCS0# / GPIO20
/ ACSDIN2
PCS1# / GPIO21
/ ACSDIN3 /
SLPBTN#
Signal Description
U1
O
Programmable Chip Select 0. RxE4[6]=1, E5[1]=1
V3
O
Programmable Chip Select 1. RxE4[6]=1, E5[2]=1
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8399 N/B Maintenance
5.3 VIA VT8235CD South Bridge(8)
General Purpose Outputs
Signal Name Pin #
I/O
Signal Description
General Purpose Outputs (Continued)
Signal Name Pin #
I/O
Signal Description
GPO0 (VSUS33)
AA3
O
General Purpose Output 0.
GPO1 / SUSA#
(VSUS33)
GPO2 / SUSB#
(VSUS33)
GPO3 /
SUSST1#
(VSUS33)
GPO4 / SUSCLK
(VSUS33)
GPO5 /
CPUSTP#
GPO6 / PCISTP#
AA2
O
General Purpose Output 1. Rx94[2] = 1
AD3
O
General Purpose Output 2. Rx94[3] = 1
Y3
O
General Purpose Output 3. Rx94[4] = 1
AB3
O
General Purpose Output 4. Rx95[1] = 1
AC7
O
General Purpose Output 5. RxE4[0] = 1
AD6
O
General Purpose Output 6. RxE4[1] = 1
Power Management and Event Detection
Signal Name Pin #
I/O
Signal Description
GPO7 / GNT5#
R2
O
General Purpose Output 7. RxE4[2] = 0
PWRBTN#
AD2
I
GPO12 / GPI12 /
INTE#
GPO13 / GPI13 /
INTF#
GPO14 / GPI14 /
INTG#
GPO15 / GPI15 /
INTH#
GPO20 / GPI20 /
ACSDIN2 /
PCS0#
GPO21 / GPI21 /
ACSDIN3 /
PCS1#
/SLPBTN#
GPO22 / GPI22 /
GHI#
GPO23 / GPI23 /
DPSLP#
GPO26 / GPI26 /
SMBDT2
(VSUS33ƒ)
GPO27 / GPI27 /
SMBCK2
(VSUS33ƒ)
D4
O
General Purpose Output 12. RxE4[4]=1, 5B[1]=0
E4
O
General Purpose Output 13. RxE4[4]=1, 5B[1]=0
V3
I
A3
O
General Purpose Output 14. RxE4[4]=1, 5B[1]=0
B3
O
General Purpose Output 15. RxE4[4]=1, 5B[1]=0
SLPBTN# /
GPIO21/
ACSDIN3 /
PCS1#
RSMRST#
AD4
I
U1
OD
General Purpose Output 20. RxE4[6]=1, E5[1]=0
V3
OD
General Purpose Output 21. RxE4[6]=1, E5[2]=0
EXTSMI# /
GPI2
AA1
IOD
R22
OD
General Purpose Output 22. RxE5[3]=1, PMIO 4C[22]=1
PME#
W4
I
P21
OD
General Purpose Output 23. RxE5[3]=1, PMIO 4C[23]=1
SMBALRT#
AB1
I
AD1
OD
General Purpose Output 26. Rx95[2] = 1, 95[3] = 1
AC3
OD
General Purpose Output 27. Rx95[2] = 1, 95[3] = 1
GPO28 / GPI28
AC8
OD
General Purpose Output 28. RxE5[3] = 1, PMIO 4C[28]=1
GPO29 / GPI29 / AB9
General Purpose Output 29. RxE5[3] = 1, PMIO 4C[29]=1
OD
VRDSLP
Note: The output state for each of the above general purpose outputs is selectable via Power
Management I/O registers Rx4C-48
Note: Default pin functions are underlined in the table above.
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Power Button. Used by the Power Management subsystem
to monitor an external
system on/off button or switch. Internal logic powered
by VSUS33.
Sleep Button. Used by the Power Management subsystem
to monitor an external sleepbutton or switch. RxE4[6] = 1,
80[6] = 1, E5[2] = 0 and PMIO Rx4C[21] = 1
Resume Reset. Resets the internal logic connected to the
VSUS33 power plane and
also resets portions of the internal RTC logic. Internal logic
powered by VBAT.
External System Management Interrupt. When enabled
to allow it, a falling edge on
this input causes an SMI# to be generated to the CPU to
enter SMI mode. (10K PU to
VSUS33 if not used) (3.3V only)
Power Management Event. (10K PU to VSUS33 if not
used)
SMB Alert. When programmed to allow it (SMB I/O
Rx8[3]=1), assertion generates
an IRQ, SMI, or power management event. (10K PU to
VSUS33 if not used)
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8399 N/B Maintenance
5.3 VIA VT8235CD South Bridge(9)
Power Management and Event Detection (Continued)
Signal Name Pin #
I/O
Signal Description
Power Management and Event Detection (Continued)
Signal Name Pin #
I/O
Signal Description
LID# / GPI4
AC1
I
SUSST1# /
GPO3
INTRUDER# /
GPI16
THRM# / GPI18/
AOLGPI
AE1
I
Y4
I
RING# / GPI3
Y2
I
BATLOW# /
GPI5
CPUSTP# /
GPO5
V4
I
AC7
O
PCISTP# /
GPO6
AD6
O
SUSA# / GPO1
AA2
SUSB# / GPO2
SUSC#
AD3
AF2
O
O
O
Notebook Computer Display Lid Open / Closed
Monitor. Used by the Power Management subsystem to
monitor the opening and closing of the display lid of
notebook computers. Can be used to detect either
low-to-high or high-to-low transitions to generate an SMI#.
(10K PU to VSUS33 if not used)
Intrusion Indicator. The value of this bit may be read at
PMIO Rx20[6]
Thermal Alarm Monitor. Rx8C[3] = 1. Rising or falling
edges (selectable by PMIORx2C[6]) may be detected to set
status at PMIO Rx20[10]. Setting of this status bit
may then be used to generate an SCI or SMI. THRM# may
also be used to enable duty cycle control of stop-clock
(STPCLK#) to automatically limit maximum temperature
(see Device 17 Function 0 Rx8C[7-4]).
Ring Indicator. May be connected to external modem
circuitry to allow the system to be re-activated by a
received phone call. (10K PU to VSUS33 if not used)
Battery Low Indicator. (10K PU to VSUS33 if not used)
(3.3V only)
CPU Clock Stop (RxE4[0] = 0). Signals the system clock
generator to disable the CPU clock outputs. Not connected
if not used.
PCI Clock Stop (RxE4[1] = 0). Signals the system clock
generator to disable the PCI clock outputs. Not connected if
not used.
Suspend Plane A Control (Rx94[2]=0). Asserted during
power management POS, STR, and STD suspend states.
Used to control the primary power plane. (10K PU to
VSUS33 if not used)
Suspend Plane B Control (Rx94[3]=0). Asserted during
power management STR and STD suspend states. Used to
control the secondary power plane. (10K PU to VSUS33
if not used)
Suspend Plane C Control. Asserted during power
management STD suspend state.
Used to control the tertiary power plane. Also connected to
ATX power-on circuitry. (10K PU to VSUS33 if not used)
Y3
O
Suspend Status 1 (Rx94[4] = 0). Typically connected to
the North Bridge to provide information on host clock
status. Asserted when the system may stop the host clock,
such as Stop Clock or during POS, STR, or STD suspend
states. Connect 10K PU to VSUS33.
Suspend Clock. 32.768 KHz output clock for use by the
North Bridge (e.g., KT400A, CLE266, or P4X400) for
DRAM refresh purposes. Stopped during Suspend-to-Disk
and Soft-Off modes. Connect 10K PU to VSUS33.
CPU Missing. Used to detect the physical presence of the
CPU chip in its socket.
High indicates no CPU present. Connect to the CPUMISS
pin of the CPU socket. The state of this pin may be read in
the SMBus 2 registers. This pin may be used as CPUMISS
and GPI17 at the same time.
Alert On LAN. The state of this pin may be read in the
SMBus 2 registers. This pinmay be used as AOLGPI,
GPI18 and THRM# all at the same time.
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SUSCLK
AB3
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CPUMISS /
GPI17
Y1
I
AOLGPI /
GPI18/ THRM#
Y4
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Strap Pins for VT8235 Version CE Configuration
Signal Name Pin # Function
Description
Strap_AUTO
SPKR
KBCS#
SDCS1#
Note
L: Enable Auto Reboot
H: Disable Auto Reboot
(Default)
L: Enable CPU Frequency
AF8
CPU
Frequency Strapping
Strapping H: Disable CPU Frequency
Strapping (Default)
AF10
Internal L: Disable internal KBC
Keyboard H: Enable internal KBC
(Default)
Controller
L: Enable. Use external
AF25 Eliminate
External
EEPROM (Default)
LAN
H: Disable. Do not use
EEPROM
external EEPROM
AE10
Auto
Reboot
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8399 N/B Maintenance
5.3 VIA VT8235CD South Bridge(10)
Power and Ground
Signal Name Pin #
I/O
Signal Description
T4, U4
P
Suspend Power. 3.3V ±5%. Always available unless the
mechanical switch of the power supply is turned off. If the
ihsoft-offlÉD state is not implemented, then this pin can be
connected to VCC33. Signals powered by or referenced to
this plane are: PWRGD, RSMRST#, PWRBTN#,
SMBCK1/2, SMBDT1/2, GPO0, SUSA# / GPO1, SUSB# /
GPO2, SUSC#, SUSST1# / GPO3, SUSCLK / GPO4,
GPI1, GPI2 / EXTSMI#, GPI3 / RING#, GPI4 / LID, GPI5
/ BATLOW#, GPI6 / PME#, SMBALRT#
Suspend Power. 2.5V ±5%.
VSUSUSB
C24
P
USB Suspend Power. 2.5V ±5%.
VBAT
AF4
P
VLVREF
H22
P
VLCOMP
J22
AI
RTC Battery. Battery input for internal RTC (RTCX1,
RTCX2)
V-Link Voltage Reference. 0.9V ±5% for 4x transfers and
0.625V ±5% for 8x transfers.
V-Link Compensation.
(see pin
list)
D9,
E9-11
P
V-Link Compensation Circuit Voltage. 2.5V ±5%
P
D12.
E12
E7
P
LAN MII Power. 3.3V ±5%.Power for LAN Media
Independent Interface (interface to external PHY). Connect
to VCC33 through a ferrite bead.
LAN MII Suspend Power. 2.5V ±5%.
P
LANGND
E6
P
USBVCC
(see pin
list)
P
USBGND
P
PLLVCC
(see pin
list)
A23,
B23
C23,
D23
T22
P
PLLGND
U22
P
VSUS33
VSUS25
VCCVK
MIIVCC
MIIVCC25
LANVCC
VCCUPLL
GNDUPLL
AA4,
AB4-6
P
P
P
Power and Ground（
（Continued）
）
Signal Name Pin #
I/O
Signal Description
VCC33
VCC
(see pin
list)
(see pin
list)
P
I/O Power. 3.3V ±5%
P
Core Power. 2.5V ±5%. This supply is turned on
only when the mechanical switch on the power
supply is turned on and the PWRON signal is
conditioned high.
Ground. Connect to primary motherboard ground plane.
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LAN Power. 2.5V ±5%. Power for LAN. Connect to VCC
through a ferrite bead.
LAN Ground. Connect to GND through a ferrite bead.
USB 2.0 Differential Output Power. 3.3V ±5%. Power
for USB differential outputs (USBP0+, P0Œ, P1+, P1Œ,
P2+, P2Œ, P3+, P3Œ, P4+, P4Œ, P5+, P5Œ). Connect to
VSUS33 through a ferrite bead.
USB 2.0 Differential Output Ground. Connect to GND
through a ferrite bead.
USB 2.0 PLL Analog Voltage. 2.5V ±5%. Connect to
VCC through a ferrite bead.
USB 2.0 PLL Analog Ground. Connect to GND through a
ferrite bead.
PLL Analog Power. 2.5V ±5%. Connect to VCC through
a ferrite bead.
PLL Analog Ground. Connect to GND through a ferrite
bead.
GND
(see pin
list)
P
Strap Pins for North Bridge Configuration
Signal Name Pin # Function
Description
Note
SDCS3#
SDCS3# signal state is reflected on Check the
AF26 NB
Configuratio signal pinVD[7] during power up NorthBridge DS
n
for North Bridgeconfiguration.
fordetails
SDA2
SDA2 signal state is reflected on Check the
AE24 NB
Configuratio signal pinVD[6] during power up NorthBridge DS
n
for North Bridgeconfiguration.
fordetails
SDA1
SDA1 signal state is reflected on Check the
AC22 NB
Configuratio signal pinVD[5] during power up NorthBridge DS
n
for North Bridgeconfiguration.
fordetails
SDA0
SDA0 signal states is reflected on Check the
AF24 NB
Configuratio signal pinsVD[4] during power up NorthBridge DS
n
for North Bridgeconfiguration.
fordetails
Strap_VD3 signal state is reflected Check the
Strap_VD3
AC6 NB
Configuratio on signal pinVD[3] during power NorthBridge DS
up for North Bridgeconfiguration. fordetails
n
Strap_VD2
Strap_VD2 signal state is reflected Check the
AD5 NB
Configuratio on signal pinVD[2] during power NorthBridge DS
n
up for North Bridgeconfiguration. fordetails
Strap_VD1
Strap_VD1 signal state is reflected Check the North
AE5 NB
Configuratio on signal pin, VD[1] during power Bridge DS for details
n
up for North Bridge configuration.
Strap_VD0
Strap_VD0 signal state is reflected Check the
AF5 NB
Configuratio on signalpin, VD[0] during power NorthBridge DS
n
up for North Bridgeconfiguration. fordetails
Note: Internal Pullups are present on pins KBCK, KBDT, MSCK, MSDT, SERIRQ, LAD[3:0]
Internal Pulldowns are present on all LAN pins
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8399 N/B Maintenance
6. System Block Diagram
J16&J17
DIMM-SLOT
J502
Card Bus
Socket
J22
Mini PCI
Card Socket
U26
PCMCIA
Controller
CBI1410
U6
AMD
CLAWHAMMER
CRT
RGB
Host
Bus
U9
LVDS
Encoder
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U12
LCD
North Bridge
K8N800
U3
TV
Encoder
V-link
TV
Internal
MIC
MIC
Jack
Amplifier
G1428
PCI BUS
U2
LAN PHY
VT6103L
HDD
MII
U20
AC Link
South Bridge
U10
Audio
Codec
VT1617A
Internal Speaker
U13
HP Jack
VT8235
MDC
RJ11
LPC BUS
CD-ROM
USB2.0 X6
ISA BUS
U25
U16
Internal KB
FWH
BIOS
KBC
W83L950D
Touch Pad
FAN
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8399 N/B Maintenance
7. Maintenance Diagnostics
7.1 Introduction
Each time the computer is turned on, the system BIOS runs a series of internal checks on the hardware. This poweron self test (post) allows the computer to detect problems as early as the power-on stage. Error messages of post can
alert you to the problems of your computer.If an error is detected during these tests, you will see an error message
displayed on the screen. If the error occurs before the display is initialized, then the screen cannot display the error
message. Error codes or system beeps are used to identify a post error that occurs when the screen is not available.
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The value for the diagnostic port is written at the beginning of the test. Therefore, if the test failed, the user can
determine where the problem occurred by reading the last value written to the port by the debug card plug at MINI
PCI slot.
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7.2 Diagnostic Tool for Mini PCI Slot
The Mini PCI DOG killer card is a single-step debug tool which utilizes Mini PCI interface (Type III A) and is able
to hold a PCI bus cycle so that address, data and control bus states on PCI bus can be inspected. Especially, the tool
can help an engineer trace address/data bus for BIOS read cycles as soon as power on and debug open or short circuit
problems easily. Usually, this sort of problem will make a PC motherboard fail to boot.
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P/N:411906900001
Description: PWA-MPDOG;MINI PCI DOGKELLER CARD
Note: Order it from MIC/TSSC
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7.3 Error Codes-1
Following is a list of error codes in sequent display on the debug board.
POST (HEX)
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
DESCRIPTION
Some Type Of Long Reset
Turn off FASTA20 for POST
Signal Power On Reset
Initialize the Chipset
Search For ISA Bus VGA Adapter
Reset Counter/Timer 1
user register configure through CMOS
Size Memory
Dispatch To RAM Test
checksum the ROM
Reset PIC's
Initialize Video Adapter(s)
Initialize Video (6845 Regs)
Initialize Color Adapter
Initialize Monochrome Adapter
Test 8237A Page Registers
Test Keyboard
Test Keyboard Controller
Check If CMOS Ram Valid
Test Battery Fail & CMOS X-SUM
Test the DMA controllers
Initialize 8237A Controller
Initialize Int Vectors
POST (HEX)
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
DESCRIPTION
RAM Quick Sizing
Protected mode entered safely
RAM test completed
Protected mode exit successful
Setup Shadow
Going To Initialize Video
Search For Monochrome Adapter
Search For Color Adapter
Signon messages displayed
special init of keyboard ctrl
Test If Keyboard Present
Test Keyboard Interrupt
Test Keyboard Command Byte
TEST, Blank and count all RAM
Protected mode entered safely (2).
RAM test complete
Protected mode exit successful
Update OUTPUT port
Setup Cache Controller
Test If 18.2Hz Periodic Working
test for RTC ticking
initialize the hardware vectors
Search and Init the Mouse
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8399 N/B Maintenance
7.3 Error Codes-2
Following is a list of error codes in sequent display on the debug board.
POST (HEX)
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
DESCRIPTION
Update NUMLOCK status
special init of COMM and LPT ports
Configure the COMM and LPT ports
Initialize the floppies
Initialize the hard disk
Initialize option ROMs
OEM's init of power management
Update NUMLOCK status
Test For Coprocessor Installed
OEM functions before boot
Dispatch To Op. Sys. Boot
Jump Into Bootstrap Code
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8399 N/B Maintenance
8. Trouble Shooting
8.1 Base Work Condition
8.9 Hard Disk Driver Test Error
8.2 No Power
8.10 CD-ROM Driver Test Error
8.8 USB Port Test Error
8.16 TV Encoder Test Error
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8.4 No Display
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8.13 Modem Test Error
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Error
8.14 Mini PCI Test Error
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8.6 Memory Test Error
8.15 CardBus & Reader Test Error
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8399 N/B Maintenance
8.1 Base Work Condition(1)
System Voltage Check
P23
Power In
PJ1
PF1,PL1
P23
PD5
PWR_VDDIN
PL5,PR1
PR4
PU1
PR3
PQ1
PWRIN1
ADINP
PL20
PL18
PD14
PU19
P24
BATT
DVMAIN
PR76
PQ14
PQ15
+KBC_VREF
PU15
PL14,PU14
PL13,PR73
P26
JO7
+3V_P
JO8,JO9
P20
+3VS
L33
R296
Q28,U21
L65
Discharge
PL15,PR74
PU16,PU17
P26
JO10
+5V_P
JO11,JO12
P20
+5VS
U17
U35
R408,Q41
JS3,PL12,PR49,PU11
PR51,PU10,PU12,PL7
P21
+2.5V_P
JO526
JO527,JO528
PL11,PR53
PU13,PJL1
PL9,PL10,PQ4
PQ7,PL3,PL4
PU5,PU6,PU7
P20
+VDD3
P19
L60
+KBC_VDDA
P20
R435
JS5
Q15,Q16
+SVDD3
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P23
PD3
P20
Q12
U19
PD6
P23
PF2
PL19
PQ23
PQ24
PQ25
P20
F5
P10
D17
Q36
Q31
P16
+3VS_LAN
+VCC_RTC
P16
L32
+3VS_LAN_PLL
P20
+3V (To Next Page)
P8
+3VS_USB
P20
+2.5VS
P20
+5V
P6
R168
+NB_VCCSUS
P18
L47
+AVDDAD
P18
L52
+5V_AMP
P20
+2.5VS_DDR (To Next Page)
P21
+1.25V_DDR_P
JO5,JO6
P20
+1.25VTT
P25
+VCC_CORE
96
8399 N/B Maintenance
8.1 Base Work Condition(2)
System Voltage Check
P20
+2.5VS_DDR
PL2,PU3
PU2
PU4
U18
P22
+1.2V_P
P22
JO1,JO2
JO3,JO4
P20
+1.2VLDTA
P20
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+1.5V_P
+1.5V
P20
+2.5V
L27
L29
R235,C237,R261
P2
+1.25VSREF_MEM
R184,C150,C159
P2
+1.25VSREF_CLAW
L99
L42
L46
L44
P20
+3V
U27
P14
+VCCA
P14
L35
P11
TV_VDDA1
P11
TV_VDDA2
P11
TV_VDD
P12
L502
L503
L504
L2
L3
P6
+1.5V_VCCAGP
P6
+1.5V_NB
P6
+1.5V_VCCVL
P6
+1.5VPLL1
P6
+1.5VPLL2
LVDSVCC
P12
DVDD
P12
I2CVCC
P12
PLLVCC
+VPPA
U7
P3
+2.5VDDA
L30
L7
L24
L4
P11
+3V_TV
P6
+NB_AVDD2
P6
+NB_AVDD1
P6
+3.3VDACVDD
97
8399 N/B Maintenance
8.1 Base Work Condition(3)
System Clock Check
+3V
+3VS
+3V
+3V
+3V
L58
120Z/100M
R329
10K
C267
10U
C262
10U
C245
0.1U
C265
0.1U
C271
0.1U
C240
0.1U
P5
P7
U12
North Bridge
K8N800
GUICLK
R234
22
66M_AGP
R244
33
FS1
48
U14
11
P14
R246
PCI_CARD_CLK
C257
22P
70
P19
27
R262
CLK_KBC
25
SMB_CLK0
32
ICS_PD#
R254
0
1
FS0
R230
22
14M_SB_IOSC
R243
22
SB_VCLK
28
R258
22
USB_CLK
R265
33
PCI_SB_CLK
R238
22
14M_SB_APICCLK
FS2
P8
South
Bridge
C252
22P
C283
22P
P4
J16&J17
SMBCLK_DDR
22
SO_DIMM
SLOT
P18
2
AUDIO_14M
3
FS1
FS0
1
0
1
1
CPU
HTT
PCI
200.40
66.80
33.40
C241
27P
CLK_LPC33
C281
22P
U10
Audio
Codec
4
14
14.318MHZ
P10
U20
SMBDATA_DDR
R240
P9
SUSA#
21
X3
0111
D11
RLS4148
8
45
R310
10K
Q35
2N7002
13
22
R251
10K
Q37
2N7002
SMB_DATA0
ICS950403
21
U16
KBC
Controller
FS2
R324
10K
R257
10K
U26
PCMCIA
Controller
FS3
R346
10K
26
23
Clock
Generator
C242
22P
C255
22P
R344
10K
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2,9…
31
C246
27P
R264
22
L59
120Z/100M
FS3
R248
27
MINI_PCI_CLK
R253
22
LPC_48M
C270
22P
22
37
R245
15
CPUCLK+
R255
0
MINI_LPC_CLK
C259
22P
C103
3900P
5,10..
CPUCK+
R132
169
36
R247
15
CPUCLK-
C107
3900P
CPUCK-
25
P15
121
J22
Mini-PCI
Connector
P2
U6
CPU
98
8399 N/B Maintenance
8.1 Base Work Condition(4)
System Reset Check
1
+2.5V
JO501
POWERBTN#
P20
SW501
U22D
74HCT08_V
P17
CPU_PWROK_2.5V
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P2
ALL_PWROK_2.5V
U6
+SVDD3
2
1
P19
P20 U38
RESET
GND
MN
VCC
3
4
IMP811
C389
1U
SW1
1
3
2
4
5
+1.2VPG
U16
KBC
Controller
18
KBC_PWR_ON
Power
Module
P20
CPU_RESET#
U12
North
Bridge
NB_PCIRST#
P3
P18
U10
Audio
Codec
CPU_PCIRST#
+2.5V
R355
0
CPU
P7
U22A
KBC_RESET#
ALL_PWROK_2.5V
convert to
25
R407
1K
11
U22C
74HCT08_V
PWROK_SB
P16
25
AC97_RST#
W83L950D
P8
22
KBC_SUSB
Q26
8
KBC_RSMRST
Q20
7
KBC_SB_PWRBTN
Q21
SUSB#
P9
U20
RSMRST#
P14
20,66
CARD_PCIRST#
South
Bridge
SB_PWRBTN#
J15
Modem
Connector
U26
PCMCIA
Controller
110
+3V
U8A
74HCT08_V
PCI_RST#
64
LPC_RST#
P15
P8
J22
3
26
MINI_PCIRST#
MINI-PCI
Slot
+3V
U8C
74HCT08_V
8
NB_PCIRST#
To U12
P11
U3
TV
Encoder
19
P8
P13
IDE_PCIRST#
TV_PCIRST#
IDERST#
convert to
2,5
J14&J21
Primary&Secondary
EIDE Connector
99
8399 N/B Maintenance
*1: No power definition
Base on ACPI Spec. We define the no power as while we press the power button, the system can’t leave S5 status
or none the PG signal send out from power supply.
Judge condition:
Check whether there are any voltage feedback control to turn off the power.
Check whether no CPU power will cause system can’t leave S5 status.
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If there are not any diagram match these condition, we should stop analyzing the schematic in power supply sending
out the PG signal. If yes, we should add the effected analysis into no power chapter.
Base on the digital IC three basic working conditions: working power, reset, Clock. We define the no display as
while system leave S5 status but can’t get into S0 status.
Judge condition:
Check which power will cause no display.
Check which reset signal will cause no display.
Check which Clock signal will cause no display
Base on these three conditions to analyze the schematic and edit the no display chapter.
Keyword:
S5: Soft Off
S0: Working
For detail please refer the ACPI specification
100
8399 N/B Maintenance
8.2 No Power(1)
When power button is pressed ,nothing happens ,power indicator does not light up.
No power
AC Power
Is the
Notebook connected
to power (Either AC adaptor
or battery)?
Yes
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No
Connect AC
Adaptor or battery
Where
From Power Source
Problem(First use
AC to power it)
Please try another known good battery
or AC adapter.
Power
OK?
NO
Board-level
Trouble shooting
Check following parts and signals:
Parts:
Signals:
Yes
Please replace the
faulty AC adaptor
or Battery.
PJ1
PF1
PL1
PL5
PU1
PD3
PD5
PD6
PWR_VDDIN
DVMAIN
ADEN#
I_LIMIT
LEARNING
ADINP
BATT
Battery
Check following parts and signals:
Parts:
Signals:
PJ2
PF3
PL16
PL17
PQ15
PR75
PD6
PR76
PQ14
PR92
PR94
PR97
RP44
PU20
PR108
PR109
PR85
PR88
BATT1
PWR_VDDIN
DVMAIN
ADEN#
BAT_V
BAT_T
BAT_C
BAT_D
KBC_+3VS
KBC_CPUCORE
101
8399 N/B Maintenance
8.2 No Power(2)
When power button is pressed ,nothing happens ,power indicator does not light up.
PD5
BAV70LT1
1
2
3
PWR_VDDIN
8
7
6
5
G
PD2
BZV55C24V
PC39
0.1U
PC38
0.1U
PJO3﹐PJO4
SPARKGAP_6
PC40
1000P
1
2
3
PD3
SBM1040
3
DVMAIN
D
PC150
1000P
PR4
470K
PC152
0.01U
PR6
4.7K
PC2
1000P
PR5
4.7K
PC149
0.1U
PC148
0.01U
PR75
100K
3
2
1
PR3
100K
PC151
1000P
PR82
226K
S
3
2
1
2
ADINP
To chapter 8.2.2
PU1
AO7004
PR1
0.01
PL1
120Z/100M
S
PF1
7A/24VDC
PJ1
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PL5
120Z/100M
P23
PD6
BAV70LT1
1
G
PQ15
AO4407
P23 PU9
I_LIMIT
PC44
1U
P19
U16
KBC
Controller
14
ADEN#
23
LEARNING
PR31
10
RS+
VCC
RS-
GND1
OUT
3
8
7
6
5
76
5
6
D
4
2
GND0 1
PC41
0.1U
MAX4073FEUT-T
PQ1
2N7002
PR76
33K
PQ14
2N7002
PQ17
DTC144WK
PR2
1M
BATT
102
8399 N/B Maintenance
8.2 No Power(3)
When power button is pressed ,nothing happens ,power indicator does not light up.
PD6
BAV70LT1
BATT1
PWR_VDDIN
4
PL17
120Z/100M
6
PJ2
5
Battery Connector
4
PR86
100K
DVMAIN
PR76
33K
PQ14
2N7002
PC125
0.1U
ADEN#
14
PR88
4.99K
PR92
0
PR91
20K
3
2
1
BATT1
PR85
VCC
7 OUT2
6
RS25 RS2+
P19
RP44
33*4
D14
BAV70LT1
BAT_VOLT
78
BAT_T
BAT_TEMP
77
PR94
0
BAT_D
BAT_DATA
3
PR97
0
BAT_C
BAT_CLK
2
0.01
C301
0.1U
U16
KBC
Controller
C302
0.1U
BATT
PC124
0.01U
P23 PU20
8
+SVDD3
PC130
0.1U
BAT_V
+SVDD3
PC146
0.1U
PR87
499K
PC126
0.1U
+SVDD3
3
2
1
8
7
6
5
BATT1
PL16
120Z/100M
PC129
0.1U
P23
PR75
100K
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PF3
TR/SFT-10A
7
PQ15
AO4407
OUT1
1
PR109
10
RS1- 2
3
RS1+
GND 4
I_CHG
KBC_+3VS
75
KBC_CPUCORE
74
C306
0.1U
PC147
1U
MAX4377
PR108
10
I_DISCHG
PC145
1U
C307
0.1U
103
8399 N/B Maintenance
8.3 Battery Can not Be Charged(1)
When the battery is installed but the battery status indicate LED display abnormal.
Battery can not Charge
Is the
notebook connected
to power (AC adaptor)?
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No
Board-level
Trouble shooting
Connect
AC adaptor.
Check following parts and signals:
Yes
Replace
Mother board
1. Make sure that the battery is good.
2. Make sure that the battery is installed properly.
Battery charge
OK?
Yes
Please replace the
faulty Battery.
Parts
PF2
PL19
PQ21
PD16
PQ23
PL20
PL18
PD14
PD17
PQ24
PQ25
PC144
Signal
PU19
PR95
PC133
PC141
PC143
PR102
PR101
PR100
PQ20
PQ22
U16
ADINP
CHANGING
BATT
21N+
I_CTRL
CHARGING
BATT_SELL
No
104
8399 N/B Maintenance
8.3 Battery Can not Be Charged(2)
When the battery is installed but the battery status indicate LED display abnormal.
PF2
TR/3216FF-3A
PC134
0.01U
PQ23
AO4407
PL19
DEAD_120Z/100M
PC142
10U
3
2
1
8
7
6
5
S
ADINP
From chapter 8.2.1
PL20
33UH
PL18
3.0UH
PR105
4.7K
PC139
1000P
G
PR106
4.7K
PQ21
MMBT2222A
PD17
SSA34
PR103
100K
BATT
D
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PC136
0.01U
PD14
SSA34
PC137
10U
PC140
0.1U
PC127
1000P
PC131
10U
PC143
0.1U
PR102
20K
2IN+
PD16
BAS32L
PQ24
DTA144WK
PR101
13.7K
PC128
0.01U
PU19
P24 TL594C
CHARGING
From U16
PQ25
2N7002
PC144
0.1U
2IN+
9
10
11
12
13
14
15
16
PR95
10K
PC133
0.1U
10
I_CTRL
79
CHARGING
13
BATT_SELL
E1
C1
GND
E2
RT
C2
CT
VCC
OUTPUTCTRL DTC
FEEDBACK
REF
2IN1IN2IN+
1IN+
KBC
Controller
PR104
23.7K
PR89
4.7
8
7
6
5
4
3
2
1
PC138
0.1U
PC141
0.01U
PC135
1U
PR93
100K
PC132
1000P
PR90
10K
PR96
6.19K
PR98
124K
PR99
2.49K
PJS501
SHORT-SMT3
P19
U16
PR100
249K
PQ22
2N7002
PR84
0
PQ20
2N7002
105
8399 N/B Maintenance
8.4 No Display(1)
There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.
No Display
Monitor
or LCD module
OK?
No
Yes
Make sure that CPU module,
DIMM memory are installed
Properly.
Display
OK?
Yes
No
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Replace monitor
or LCD.
Replace
Motherboard
Correct it.
1.Try another known good CPU
module, DIMM module and BIOS.
2.Remove all of I/O device (FDD,
HDD, CD-ROM…….) from
motherboard except LCD or monitor.
Display
OK?
No
Yes
Board-level
Troubleshooting
Using debug card,depending
on the error codes to make
sure which parts maybe faulty
Using circuit diagram ,check
the faulty parts
1. Replace faulty part.
2. Connect the I/O device to the
M/B one at a time to find out
which part is causing the problem.
106
8399 N/B Maintenance
8.4 No Display(2)
There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.
DVDD
53,70,79,95
LVDSVCC
30,40,48
12CVCC
+2.5V
10,16
R197
4.7K
RP13
0*4
67
LV_A[0..2]
LV_TST1
R141
4.7K
LV_PD#
R142
4.7K
LV_INTR
R144
4.7K
LV_RES1
R188
10K
LVDS_VREF
R190
10K
87
LVDS_CLKIN+
RP7~RP12
22*4
R182
R179
22
NB_FPCLK-
75
LVDS_HSYNC
R199
22
NB_FPHS
74
LVDS_VSYNC
R198
22
NB_FPVS
76
LVDS_DE
R193
22
NB_FPDE
72
22
U9
44
TXOUT2+
45
TXOUT2-
7
46
TXOUT1+
11
47
TXOUT1-
13
49
TXOUT0+
12
50
TXOUT0-
14
4.7K
LV_DUAL
12
41
6
TXCLK+
RP3
1K*4
20
61
4.7K
LV_EDGE
23
18
DVMAIN
U12
Q2
AO3400
C44
0.1U
R32
470K
+1.5V
R102
0
ENAVDD
+1.5V
+3V
+3V
D1
BAW56
R433
10K
25
R124
0
1
ENPBLT
Q3
DTC144TKA
3
2
L25
R434
10K
ENPBLT_NB
+SVDD3
ENBL_KBC
RP53
10K
R432
0
120Z/100M
P19
BATT_DEAD#
15
BLADJ
11
U16
KBC
Controller
C315
0.1U
29,30
C19
0.1U
North
Bridge
PWR_VDDIN
Q1
DTC144TKA
J8
17,19,21
C424
0.1U
C43
0.1U
P12
26
L6
120Z/100M
C22
1000P
C21
0.1U
8
TXCLK-
22
R143
C42
1000P
LCD Connector
R140
1,2
5
21
78
P7
+3V
63~65
18
LV_I2SEL
NB_FPCLK+
LVDS_CLKIN-
+3V
4.7K
22
88
42
R415
NB_FPD[00..23]
P12
LVDS
Encoder
+1.5V
LVDS_D[0..23]
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68
PLLVCC
1~8,81~86…
P10
LCD_ID[0..2]
RP1
10K*4
P9
P8
U20
South
Bridge
107
8399 N/B Maintenance
8.5 External Monitor No Display(1)
There is no display or picture abnormal on CRT monitor, but LCD can normally display.
External Monitor No Display
1. Confirm monitor is good and check
the cable are connected properly.
2. Try another known good monitor.
Display
OK?
Yes
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Board-level
Trouble shooting
Yes
Re-soldering.
No
Check following parts and signals:
Replace faulty monitor.
Replace
Mother board
No
Check if J2
are cold solder?
Parts:
U12
U20
J2
Q5
Q6
R420
R423
L15
U39
U40
L18
R421
R422
L16
L17
L12
L13
L14
CP1
CP2
C1
Signals:
RP2
C410
C411
C412
R12
R13
R68
R69
CRT_DDDA
CRT_DDCK
CRT_HSYNC
CRT_VSYNC
CRT_TED
CRT_GREEN
CRT_BLUE
CRT_IN#
108
8399 N/B Maintenance
8.5 External Monitor No Display(2)
There is no display or picture abnormal on CRT monitor, but LCD can normally display.
+3V
R68
2.2K
CRT_DDDA
CRT_DDCK
P7
R69
2.2K
Q5
2N7002
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Q6
2N7002
R420
33
L15
120Z/100M
12
R423
33
L18
120Z/100M
15
P11
+5V
J2
U39
74HCT1G126
CRT_HSYNC
North
Bridge
U40
74HCT1G126
CRT_VSYNC
CRT_RED
CRT_GREEN
CRT_BLUE
RP2
75*4
R421
51
L17
120Z/100M
13
R422
51
L16
120Z/100M
14
C410
22P
C411
22P
CP2
22P*4
L12
120Z/100M
1
L13
120Z/100M
2
L14
120Z/100M
3
C412
22P
External VGA Connector
U12
+3V
CP1
22P*4
+3V
R13
10K
P9
U20
South
Bridge
CRT_IN#
R12
1K
5
C1
100P
6,7,8,10
109
8399 N/B Maintenance
8.6 Memory Test Error(1)
Either on board or extend SDRAM is failure or system hangs up.
Memory Test Error
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1.If your system installed with expansion
SO-DIMM module then check them for
proper installation.
2.Make sure that your SO-DIMM sockets
are OK.
3.Then try another known good SO-DIMM
modules.
Test
OK?
No
Yes
If your system host bus clock
running at 100MHZ then make
sure that SO-DIMM module
meet require of DDR 333.
Yes
Board-level
Troubleshooting
Replace the faulty
SDRAM module.
Replace
Motherboard
No
Replace the faulty
SDRAM module.
Check following parts and signals
Parts:
Signals:
U6
U20
U14
J16
J17
Q35
Q37
R324
R346
R329
R344
RP19
..
.
RP33
+3V
+1.25VTT
+2.5VS_DDR
+1.25VSREF_MEM
CPU_MD[0..63]
CPU_DQS[0..7]
CPU_DQM[0..7]
MEMADD_A/B[0..13]
DDR_BAA/B[0,1]
DDR_RASA/B[0,1]
DDR_WEA/B[0,1]
CPU_CS[0..3]#
CPU_CKEA/B
CPU_CS[0..3]#
DDRCLK[0,1,4..7]
DDRCLK[0,1,4..7]#
SMBCLK_DDR
SMBDATA_DDR
110
8399 N/B Maintenance
8.6 Memory Test Error(2)
Either on board or extend SDRAM is failure or system hangs up.
+1.25VTT
RP[31﹐
﹐33﹐
﹐34﹐
﹐36﹐
﹐
37﹐
﹐39﹐
﹐40﹐
﹐42]
68*8
+2.5VS_DDR
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CPU_MD[0..63]
RP19~RP30
10*8
RP14~RP18
47*8
RP[32﹐
﹐35﹐
﹐38﹐
﹐41]
68*4
RP43
47*4
R259,R260
47
+1.25VSREF_MEM
CPU_DQS[0..7]
P2
P4
CPU_DQM[0..7]
MEMADD_A/B[0..13]
U6
DDR_BAA/B[0,1]
J16
&
J17
DDR_CASA/B#
CPU
DDR_RASA/B#
DDR_WEA/B#
CLAWHAMMER
CPU_CS[0..3]#
DIMM0 &DIMM1
CPU_CKEA/B
DDR_CLK[0,1,4..7]
DDR_CLK[0,1,4..7]#
+3VS
R324
10K
P9
SMBCLK1
U20
South Bridge
VT8235
P5
U14
CLK GEN
ICS950403
SMBDATA1
+3V
R346
10K
+3V
Q35
2N7002
R329
10K
R344
10K
Q37
2N7002
26
SMB_DATA0
SMBDATA_DDR
25
SMB_CLK0
SMBCLK_DDR
111
8399 N/B Maintenance
8.7 Keyboard/Touch Pad Test Error(1)
Error message of keyboard or touch-pad failure is shown or any key does not work.
Keyboard or Touch-Pad
Test Error
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Check
U16, J501,J18
for cold solder?
Is K/B or
T/P cable connected to
notebook
properly?
No
Yes
Correct it.
Board-level
Troubleshooting
No
Parts
Replace
Motherboard
No
Re-soldering
Check following parts and signals:
Try another known good Keyboard
or Touch-pad.
Test
Ok?
Yes
Yes
Replace the faulty
Keyboard or
Touch-Pad
U16
U20
U14
J501
J18
Q17
Q27
R262
SW502
SW505
SW503
SW504
Signals
L67
L69
R292
RP51
C341
C303
C304
X4
+KBC_VDDA
KBD_CS0
+VDD3
KI0..KI7
KO0..KO15
KBC_EXTSMI#
KBC_WAKE_UP#
CLK_KBC
T_DATA
T_CLK
XIN
XOUT
112
8399 N/B Maintenance
8.7 Keyboard/Touch Pad Test Error(2)
Error message of keyboard or touch-pad failure is shown or any key does not work.
+3V
RP51
4.7K
+KBC_VREF
+KBC_VDDA
25
KBD_CS0
From U20 South Bridge
71
C303
0.1U
C304
0.1U
55~62
KI0..KI7
39~54
KO0..KO15
J501
17~24
P19
1~16
JO530
U16
KBD_CS0
To J501 Keyboard Connector
P8
P9
+VDD3
26
SW502
KI3
W83L950D
KO0
JO531
SW505
U20
KI4
South
Bridge
EXTSMI#
KBC_EXTSMI#
Q17
DTC144TKA
WAKE_UP#
KBC_WAKE_UP#
Q27
DTC144TKA
KO0
+5V
5
R429
0
1
C341
0.1U
P13
37
J18
T_DATA
L67
120Z/100M
2
6
T_CLK
L69
120Z/100M
3
SW504
4
XIN
SW_LEFT
29
XOUT
P5
U14
CLK GEN
ICS950403
R262
22
CLK_KBC
R292
70
1M
SW503
X4
SW_RIGHT
Touch Pad Connector
9
28
21
P19
Keyboard Connector
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72
5
6
C329
22P
8MHZ
C328
22P
113
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8.8 USB Port Test Error(1)
An error occurs when a USB I/O device is installed.
USB Test Error
Check if the USB device is installed
properly. (Including charge board.)
Test
OK?
Yes
No
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Correct it
Replace
Mother board
Check following parts and signals:
Parts:
Replace another known good USB
device.
Re-test
OK?
No
Yes
Replace the
faulty part
Board-level
Trouble shooting
U20
J3
J4
J9
F2
F3
F4
L20
L21
L22
L23
L97
L98
C32
C33
C384
R10
R27
R212
Signals:
+5VS
USBP4+
USBP0+
USBP4-
USBP0-
USBP5+
USBP1+
USBP5-
USBP1-
USB_OC#[0..5]
USBP2+
USBP2USBP3+
USBP3-
114
8399 N/B Maintenance
8.8 USB Port Test Error(2)
An error occurs when a USB I/O device is installed.
+5VS
F2
A1,B1
MINISMDC110
C36
1U
R11
10K
C380
0.1U
+ C32
330U
R10
10K
P17
USB_OC#0
USB_OC#1
R9
560K
C4
1000P
B2
A2
USBP0USBP1-
L22
90Z/100M
USBP1+
USBP0+
2
3
3
2
1
4
4
1
+5VS
P8
F3
J3
R4
560K
L23
90Z/100M
A3
B3
A1,B1
MINISMDC110
C34
1U
R28
10K
C383
0.1U
+ C33
330U
USB2.0
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C10
1000P
R27
10K
P17
USB_OC#2
USB_OC#3
U20
R29
560K
C37
1000P
R26
560K
B2
A2
USBP2USBP3-
L20
90Z/100M
USBP3+
USBP2+
+5VS
2
3
3
2
1
4
4
1
F4
L21
90Z/100M
A3
B3
L101
600Z/100M
MINISMDC110
J4
C84
1U
R195
10K
C101
0.1U
+ C384
330U
USB2.0
South
Bridge
C39
1000P
A1,B1
R212
10K
P17
USB_OC#4
USB_OC#5
C385
1000P
C386
1000P
J9
R353
560K
L97
90Z/100M
2
3
3
2
1
4
4
1
L98
90Z/100M
A3
B3
USB2.0
B2
A2
USBP4USBP5-
USBP5+
USBP4+
R224
560K
115
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8.9 Hard Disk Driver Test Error(1)
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.
Hard Driver Test
Error
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Board-level
Troubleshooting
1.Check the BIOS setup
2.Replace another good hard driver try again
Check following parts and signals:
Re-boot
OK?
Yes
Replace the faulty parts.
No
Check the system driver for proper installation.
Re - Test
OK?
Yes
End
Replace
Motherboard
Parts:
Signals:
U20
J14
PR61
PR62
RP59
RP58
R325
R320
R327
R331
Q32
U8
HDD_PDD[0..15]
HDD_PDCS[1,3]#
HDD_PDA[0,2]
HDD_PDDACK#
HDD_IRQ14
HDD_PDIOW#
HDD_PDDREQ
HDD_PIORDY
HDD_PDA1
HDD_PDIOR#
IDERST#
No
116
8399 N/B Maintenance
8.9 Hard Disk Driver Test Error(2)
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.
+5V
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+3V
R320
4.7K
HDD_PDCS[1,3]#
37,38
IDE_PDA[0,2]
HDD_PDA[0,2]
35,36
IDE_PDDACK#
HDD_PDDACK#
30
IDE_IRQ14
HDD_IRQ14
32
IDE_PDIOW#
HDD_PDIOW#
24
IDE_PDDREQ
HDD_PDDREQ
22
HDD_PIORDY
28
HDD_PDA1
34
HDD_PDIOR#
26
U20
RP59
0*8
R226
10K
South Bridge
IDE_PIORDY
VT8235
IDE_PDA1
RP58
0*4
IDE_PDIOR#
+3V
+3V
P13
J14
HDD Connector
3~18
IDE_PDCS[1,3]#
P9
C254
0.1U
HDD_PDD[0..15]
IDE_PDD[0..15]
P8
C251
0.1U
+3V
R325
10K
PR61,PR62
0*8
41,42
+5V
+3V
R297
22
R327
10K
PCI_RST#
U8A
74HCT08_V
R331
10K
IDE_PCIRST#
2
IDERST#
Q32
DTC144TKA
27
R229
470
117
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8.10 CD-ROM Driver Test Error(1)
CD-ROM driver can’t run normally,maybe an error message is shown when reading data from CD-ROM.
CD-ROM Driver
Test Error
Check the CD-ROM driver for proper
installation.
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Board-level
Troubleshooting
Check following parts and signals:
Test
OK?
Yes
No
Try another known good compact disk.
Re - Test
OK?
Yes
Correct it
Replace
Motherboard
Replace
the faulty parts.
Parts:
Signals:
U20
J21
PR63
PR68
RP69
RP70
R384
R398
R327
R331
Q32
U8
CD_SDD[0..15]
CD_SDCS[1,3]#
CD_SDA[0..2]
CD_SDDACK#
CD_SDIOW#
CD_SDDREQ
CD_SIORDY
CD_IRQ15
CD_SDIOR#
PCI_RST#
No
118
8399 N/B Maintenance
8.10 CD-ROM Driver Test Error(2)
CD-ROM driver can’t run normally,maybe an error message is shown when reading data from CD-ROM.
+5V
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38~42
+3V
C314
0.1U
+3V
R364
2.7K
IDE_SDD[0..15]
IDE_SDCS[1,3]#
P9
R398
4.7K
PR63,PR68
0*8
RP70
0*8
SDA2
IDE_SDA[0..2]
P8
R384
10K
C313
0.1U
CD_SDD[0..15]
6~21
CD_SDCS[1,3]#
35,36
P13
CD_SDA[0..2]
31,33,34
IDE_SDDACK#
CD_SDDACK#
28
IDE_SDIOW#
CD_SDIOW#
25
IDE_SDDREQ
CD_SDDREQ
22
R385
10K
South Bridge
RP69
0*4
27
CD_IRQ15
29
IDE_SDIOR#
CD_SDIOR#
24
+3V
+3V
+5V
Connector
CD_SIORDY
IDE_IRQ15
IDE_SIORDY
VT8235
CD-ROM
U20
J21
+3V
R327
10K
R297
22
PCI_RST#
U8A
74HCT08_V
R331
10K
IDE_PCIRST#
IDERST#
5
Q32
DTC144TKA
119
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8.11 Audio Failure(1)
There is trouble with the sound from speaker or completely no sound.
Audio Failure
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1. Check if speaker cables are connected
properly.
2. Make sure all the drivers are installed
properly.
Board-level
Troubleshooting
Check following parts and signals:
Parts:
Test
OK?
Yes
Correct it.
No
Try another known good speaker,
CD-ROM.
Re-test
OK?
Yes
Replace
Motherboard
Replace the
faulty parts.
U10
U14
U26
U13
J13
J21
L45
L47
L48
L43
R200
R191
R194
R213
L62
R172
R173
C148
R403
U11
L52
R205
Q13
C235
J12
L39
L41
L50
L51
L53
..
.
L56
Signals:
+AVDDAD
VREF_OUT
MIC1
MIC2
CDROM_LEFT
CDROM_RIGHT
CDROM_ROMM
AUDIO_14M
AC97_SYNC
AC97_SDIN
AC97_SDOUT
AC97_RST#
AC97_BITCLK
SB_SPKR
CARDSPK#
AOUT_L
AOUT_R
AC_GPI3
TP534
+5V_AMP
SHUTDOWN
SPKR_ROUT+
SPKR_ROUTSPKR_LOUT+
SPKR_LOUTHP_SENSE
No
120
8399 N/B Maintenance
8.11 Audio Failure(2)--Audio In
There is trouble with the sound from speaker or completely no sound
+AVDDAD
P5
L47
120Z/100M
+5V
25,38
2
AUDIO_14M
R240
45
22
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C199
10U
C189
0.1U
C190
0.1U
26,42
L45
120Z/100M
+3VS
C186
0.1U
1,9
C182
0.1U
C185
0.1U
P18
4,7
10
1K
L43
600Z/100M
P18 J10
Microphone
Jack
L48
600Z/100M
R191
R194
R213
0
1K
1K
R178
47K
C201
270P
L62
120Z/100M
D6/H2.2
Second EIDE Connector
C144
1U
18
2
CDROM_RIGHT
R172
330
C142
1U
20
R177
100K
3
CDROM_COMM
AC97_RST#
R300
22
22
R333
C134
2200P
R176
100K
C133
2200P
C143
AC97_BITCLK
VT8235
+AVDDAD
35
36
40
1U
P9
U20
South
Bridge
Audio Codec
+3V
PCBEEP
C148
1U
R403
100K
U11
AHC1G86DBV
1
4
R202
10K
330
J21
11
C188
0.1U
R173
P10
22
C162
270P
CDROM_LEFT
22
R305
22
1
R304
AC97_SDIN
AC97_SDOUT
6
21
C141
1U
MIC2
U10
22
5
12
+
P13
C135
1U
MIC1
R214
47K
MIC501
P18 Internal
Microphone
28
VREF_OUT
SB_GPO0
To next page
AC97_SYNC
R192
8
R200
U14
CLK
Generator
ICS950403
2
R436
10K
SB_SPKR
CARDSPK#
3
R393
10K
R206
10K
P14
62
U26
PCMCIA
Controller
AOUT_L
To next page
AOUT_R
To next page
AC_GPI3
To next page
19
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8.11 Audio Failure(3)--Audio Out
There is trouble with the sound from speaker or completely no sound
TP534
14
+
C229
0.1U
120Z/100M
1
16
SPKR_ROUT-
L54
120Z/100M
2
4
SPKR_LOUT+
L55
120Z/100M
3
9
SPKR_LOUT-
L56
120Z/100M
4
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7,18,19
C235
100U
C419
0.1U
L53
C212
0.1U
From front page U10
U13
C236
+VDD3
C227
SHUTDOWN
R205
0
100U
100U
Audio
AMP
R216
100K
SB_GPO0
P18 J12
L50
600Z/100M
R218
1K
C224
100P
R217
1K
C223
100P
L41
120Z/100M
L39
600Z/100M
JACK-5P-R/A-W9.1
22
15,17
HP_SENSE
R222
+5V_AMP
R223
47K
100K
C214
0.1U
C230
0.1U
1U
8
R219
100K
2
R221
100K
3
5
C228
1U
C231
1U
10
6
C233
1U
C232
1U
11
20
C211
1U
23
C210
1U
C234
C208
1U
L51
600Z/100M
Q13
DTC144TKA
From front page U20
Internal
Speaker Connector
R215
4.7K
AC_GPI3
C213
0.1U
P18
J13
P18
+
+5V
L52
120Z/100M
SPKR_ROUT+
+
+5V_AMP
21
AOUT_L
From front page U10
AOUT_R
From front page U10
TPA0212_GND
122
8399 N/B Maintenance
8.12 LAN Test Error(1)
An error occurs when a LAN device is installed.
LAN Test Error
1.Check if the driver is installed properly.
2.Check if the notebook connect with the
LAN properly.
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Board-level
Troubleshooting
Yes
Test
OK?
No
Check if BIOS setup is ok.
Correct it.
Replace
Motherboard
Re-test
OK?
Yes
Correct it.
Check following parts and signals:
Parts:
U2
U4
U20
J5
L26
L28
X1
R36
R51
R37
R52
R34
R87
R92
R93
R283
R284
RP52
RP6
R59
R54
R53
R74
R413
R46
..
.
R49
C85
C87
C74
Signals:
+3VS
+3VS_LAN_PLL
+3VS_LAN
TXD+
TXDRXIN+
RXINPJTX+
PJTXPJRX+
PJRXLAN_DATAIO
LAN_DCLK
LAN_MTXC
LAN_MRXC
LAN_MTXD[0..3]
LAN_MRXD[0..3]
LAN_MTXE
LAN_COL
LAN_CRS
LAN_MRXDV
LAN_MRXER
LAN_XI
LAN_XO
No
123
8399 N/B Maintenance
8.12 LAN Test Error(2)
An error occurs when a LAN device is installed.
U4
P16 LF_H41S
+3VS
1,7,18
+3VS_LAN_PLL
+3VS_LAN
R34
0
7
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32
+3VS_LAN
R51
R37
R52
10K
23
ANE
10K
SPEED
21
10K
DUPLEX
22
10K
TEST#
20
TX-
L31
120nH
25,36,41
R36
TX+
C50
0.1U
R78
49.9
P16
35
U2
34
RX-
C75
0.1U
R77
49.9
L26
90Z/100M
TXD+
TXD-
1
4
2
3
LAN PHY
27
R92
P10
22
R93
22
MTXC
R284
22
MRXC
R283
22
RP52
22*4
RP6
22*4
U20
43
LAN_DATAIO
26
RXIN-
1
4
2
3
44
LAN_DCLK
LAN_MTXC
R62
22
LAN_MRXC
R71
22
LAN_MTXD[0..3]
VT6103L
L28
90Z/100M
RXIN+
R66
49.9
9
PJTX+
1
9
PJTX-
2
16
PJRX+
3
14
PJRX-
6
P16
J5
RX+
CMT
6
8
TD+
RXC
10
PJ4
4,5
15
PJ7
7,8
TDR48
75
+3VS_LAN
R87
1.5K
11
1
3
R49
75
R47
75
R46
75
RJ45-8P
/RJ11-4P
RD+
C74
1000P
R76
600Z/100M
RD-
R61
49.9
4
C54
0.1U
11~14
South
Bridge
LAN_MRXD[0..3]
R59
22
VT8235
LAN_COL
R54
22
15
LAN_CRS
R53
22
16
LAN_MRXDV
R74
22
3
LAN_MRXER
R413
22
5
45~48
LAN_MTXE
10
40
39
LAN_XI
R91
300
LAN_XO
C85
22P
X1
25MHZ
C87
22P
124
8399 N/B Maintenance
8.13 Modem Test Error(1)
An error occurs when run the modem
Modem Test Error
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1.Check if the driver is installed properly.
2.Check if the notebook connect with the
phone LAN properly.
Board-level
Troubleshooting
Check following parts and signals:
Test
OK?
Yes
No
Replace a known good modem
Re-test
OK?
Yes
Correct it.
Parts:
Replace
Motherboard
Correct it.
J15
J7
U10
U20
J5
R342
L19
L105
R5
R867
R305
R300
R304
Signals:
R341
R336
R334
C187
C2
C3
C666
C667
JS1
JS506
+5V
+3VS
+3V
MONO_OUT
AC97_SDOUT
AC97_RST#
AC97_SYNC
MDC_SDIN
AC97_BITCLK
TIP_1
TIP
RING_1
RING
No
125
8399 N/B Maintenance
8.13 Modem Test Error(2)
An error occurs when run the modem
21
+3V
R342
37
P16
C187
Audio Codec
1U
C167
1U
1
MONO_OUT
J15
Modem Daughter
Board Connector
C353
1U
P18
23
AC97_SDOUT
R305
22
25
AC97_RST#
R300
22
22
AC97_SYNC
R304
22
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17
+3VS
U10
16
4.7K
10,18
+5V
24
R341
22
26
R336
22
30
R334
22
P9
U20
South Bridge
MDC_SDIN
VT8235
AC97_BITCLK
TIP
L19
400UH
5
3
2
P16 3
1
4
C3
1000P
1
JS1
2
R5
0
C2
1000P
RING
TIP_1
A1
TIP
A2
RING
A3
RING_1
A4
P16
J5
TIP_1
J7
L105
400UH
4
1
3
2
GND1
GND2
C666
1000P
JS506
R867
0
C667
1000P
RING_1
RJ45-8P
/RJ11-4P
126
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8.14 Mini PCI Test Error(1)
An error message is shown after Mini PCI device is installed or the Mini PCI device does’t work.
Mini PCI Test Error
1.Please check if the Mini PCI device is
installed properly.
2.Confirm Mini PCI device driver is
installed ok.
Test
OK?
Yes
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Board-level
Troubleshooting
Correct it
No
Please try another known good Mini PCI device.
Re-test
OK?
No
Yes
Please change the
faulty part then end.
Please replace
Motherboard
Check following parts and signals:
Parts:
Signals
U20
U14
J22
Q10
U8
R248
R255
R297
R348
R267
R127
R128
R300
R305
R268
R476
R478
PCI_AD[0..31]
PCI_C/BE# [0..3]
MINIPCI_PD
PCI_INTC#
PCI_GNT2#
SERIRQ
LDRQ0#
AC97_SYNC
PCI_PERR#
PCI_REQ1#
CLKRUN#
PCI_SERR
PCI_INTD#
PCI_IRDY#
AC97_SDOUT
AC97_RST#
AC97_BITCLK
MDC_SDIN
LAD[0..3]
PCI_PAR
PCI_TRDY#
PCI_FRAME#
PCI_STOP#
PCI_DEVSEL#
MINI_PCIRST#
MINI_PCI_CLK
MINI_LPC_CLK
127
8399 N/B Maintenance
8.14 Mini PCI Test Error(2)
An error message is shown after Mini PCI device is installed or the Mini PCI device does’t work.
+5V
R339
330
D508
Q10
DTC144TKA
+3V
+5V
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123, 97
C89
0.1U
RP54
4.7K
PCI_AD[0..31]
PCI_AD21
R120
P10
30
PCI_GNT2#
SERIRQ
LDRQ0#
U20
R348,R267
PCI_PERR#
CLKRUN#
0
MINI_PCI_SERIRQ
MINI_LPC_LDRQ#
86,73,59,45
PCI_C/BE#[0..3]
South Bridge
PCI_INTD#
PCI_IRDY#
AC97_SDOUT
AC97_BITCLK
AC97_RST#
MDC_SDIN
LAD[0..3]
PCI_PAR
PCI_TRDY#
PCI_FRAME#
PCI_STOP#
R127,R128
R305,R300
22
R476,R269
R268,R478
0
21,112
29,65
67,71,103
PCI_SERR#
20,61
105~107,110
MINI_LPC_AD[0..3]
J22
MINI-PCI Connector
AC97_SYNC
PCI_REQ1#
P15
17
PCI_INTC#
P9
48
13,98
MINIPCI_PD
P8
100
93,16,22,36
56,64
66,68,72
PCI_DEVSEL#
U8
P5
U14
CLK GEN
ICS950403
14
31
R253
22
LPC_48M
R297
22
R248
R255
MINI_PCIRST#
26
27
MINI_PCI_CLK
25
0
MINI_LPC_CLK
121
128
8399 N/B Maintenance
8.15 CardBus & Reader Test Error(1)
An error occurs when a PC card device is installed.
PC Card Slot Failure
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1. Check if the PCMCIA CARD device is
installed properly.
2. Confirm PCMCIA card driver is installed ok.
Board-level
Troubleshooting
Check following parts and signals:
Test
OK?
Yes
No
Try another known good PCMCIA card device.
Re-test
OK?
No
Yes
Parts:
Signals
U20
U26
U14
J502
U27
R396
R397
RP48
RP54
RP55
R297
U8
R246
R382
R391
+VCCA
+VPPA
CCLKRUN#
CAD[0..31]
CCBE#[0..3]
CCLK
CIRDY#
CTRDY#
CSTOP#
CDEVSEL#
CFRAME#
CPAR
CPERR#
CSERR#
Correct it
Change the faulty
part then end.
Replace
Motherboard
CGNT#
CINT#
CREQ#
CBLOCK#
CRST#
R2_D2
R2_D14
R2_A18
CVS[1,2]
CCD#[1,2]
CARD_PCIRST#
PCI_CARD_CLK
129
8399 N/B Maintenance
8.15 CardBus & Reader Test Error(2)
An error occurs when a PC card device is installed.
+3V
R396
10K
R397
10K
PCI_LOCK#
67
70
14,18,30..
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C361
0.1U
P8
P9 P10
C360
0.1U
C366
0.1U
C367
0.1U
+VCCA
90,126
RP55
2.2K
RP54
4.7K
U26
PCI_DEVSEL#
PCI_FRAME#
South
Bridge
PCI_IRDY#
PCI_TRDY#
PCI_PERR# PCI_STOP#
PCI_SERR# PCI_PAR
28,29
31~36
1
PCI_REQ0#
PCI_GNT0#
2,60
PCI_INTB#
17,51
C365
0.1U
R401
10K
136
CCLKRUN#
76,77,79..
CAD[0..31]
88,99..
CCBE#[0..3]
108~110
CCLK
105,107,111
CSTOP#
101,104,133
CPAR
106,132,123
103,119
C372
0.1U
+VCCA
P14
R394
10K
33
J502
2,3,4..
P14
C368
0.1U
U20
RP48
4.7K*8
R382
47K
18,52
+VCCA
PCMCIA
Controller
CCBE#0
7,12..
CIRDY#
CTRDY#
19,20,53
CDEVSEL#
CFRAME#
49,50,54
CPERR#
CSERR#
13,14,59
CGNT#
CINT#
CREQ#
CBLOCK#
CRST#
143,84,100
R2_D2
R2_D14
131,117
CVS[1,2]
43,57
75,137
CCD#[1,2]
36,67
15,16,60
CRST#
Card Bus Socket
+3V
+VCCA
+VCCA
+VPPA
48,58
32,40,47
R2_A18
PCI_AD[0..31]
R387
PCI_AD20
100
13
PCI_C/BE#[0..3]
CLKRUN#
69
SERIRQ
65
+3V
R297
73,74
U8
74HCT08_V
22
CARD_PCIRST#
20,66
1,2
VCCEN#[0,1]
71,72
VPPEN[0,1]
16
R391
10K
+3V
14,15
P14
+3V
5,6
+5V
C367
0.1U
P5
U14
CLK GEN
ICS950403
13
R246
27
PCI_CARD_CLK
21
11,12,13
3,4
C369 C371
0.1U 0.1U
C373
0.1U
U27
CP2211
7
+VCCA
10
+VPPA
C364
0.1U
C374
0.1U
130
8399 N/B Maintenance
8.16 TV Encoder Test Error(1)
An error occurs when using the computer as TV.
TV Fail
1. Check if the TV device is installed
properly.
2. Confirm TV driver is installed ok.
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Board-level
Troubleshooting
Test
OK?
Yes
No
Check if BIOS setup is ok.
Parts:
Correct it.
Replace
Motherboard
Re-test
OK?
No
Check following parts and signals:
Yes
Correct it.
U3
U12
U20
J1
C52
R119
R381
X6
C395
C396
R297
U8
L9
L10
L11
L1
R55
R79
R112
R113
R94
R89
RP4
C46
C47
C48
C64
C66
C5
C6
C7
Signals
TV_VDD
TV_DS
TV_VDDA1
I2C_DATA
TV_VDDA2
I2C_CLK
TV_LUMA
TV_CRMA
TV_COMP
TV_PCIRST#
TVD[0..15]
TVHS
TVVS
TVCLK
TVCLK1
131
8399 N/B Maintenance
8.16 TV Encoder Test Error(2)
An error occurs when using the computer as TV.
1
+3V_TV
26,40,57
TV_VDD
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TV_VDDA1
64,1
TV_VDDA2
P7
3
18,32,48,59
14
TV_LUMA
L9
2.7UH
4
12
TV_CRMA
L11
2.7UH
6
10
TV_COMP
L10
2.7UH
7
5,9,13
C52
0.1U
6
P11
RP4
75*4
C46
270P
C48
270P
C47
270P
L1
JP_BEAD_DFS
C6
270P
C7
270P
C5
270P
GND1
P11
GND2
TVD[0..11]
U12
TVHS
TVVS
U3
J1
22
R60
0
TVCLK
25
R72
0
TVCLKI
27
TV_DS
29
R121
0
I2C_DATA
R119
0
21
R39
0
I2C_CLK
R381
0
20
R82
10K
TV Encoder
7
TV_RSET
R55
4.64K
54
TV_TE
R79
10K
46
TVD12
R112
10K
47
TVD13
R113
10K
50
TVD14
R94
10K
51
TVD15
R89
10K
61
TV_BCO
C64
10P
60
TV_VSO
C66
10P
S-Video
North
Bridge
23
2
X6
14.318MHZ
3
+3V_TV
P8
U20
South
Bridge
U8C
PCI_RST#
R297
22
TV_PCIRST#
19
C395
27P
C396
27P
132
8399 N/B Maintenance
9. Spare Part List(1)
Part Number Description
Location(S)
Part Number Description
221679920001 CARTON;NON-BRAND,8640C
242600000439 LABEL;25*6,HI-TEMP,COMMON
221679950001 PARTITION;IN CARTON,8640C
242600000452 LABEL;BLANK,7MM*7MM,PRC
221679950002 CARD BOARD;TOP/BTM,PALLET,8640C
242600000452 LABEL;BLANK,7MM*7MM,PRC
221679950003 CARD BOARD;FRAME,PALLET,8640C
221679950004 PARTITION;PALLET,8640C
222600020049 PE BAG;50*70MM,W/SEAL,COMMON
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242664800013 LABEL;CAUTION,INVERT BD,PITCHING
242668300028 LABEL;32*7MM,POLYESTER FILM,HOPE
242669600005 LABEL;LOT NUMBER,RACE
222600020310 PE BAG;70X100MM,W/SEAL,COMMON
242670800113 BFM-WORLD MARK;WINXP,7521N
222670820003 PE BAG;L560*W345,7521N
242679900005 LABEL;BAR CODE,(25*10MM)*12pcs,8
222671330003 PE BAG;LCD BRACKET,STINGRAY
Location(S)
242684100001 LABEL;AGENCY-GLOBAL,8399
222678500002 PE BUBBLE BAG;BATTERY,280*170,MS
242684100002 LABEL;BATT 11.1V/4AH,LI,PANA,839
224670830002 PALLET;1250*1080*130,7521N
245600010007 FLOW CARD;M/B,WHITE
225600000054 TAPE;INSULATING,POLYESTER FILM,1
271002000301 RES;0 ,1/10W,5% ,0805,SMT
R431
225600000061 TAPE;ADHENSIVE,DOUBLE-FACE,W20,U
271002100301 RES;10 ,1/10W,5% ,0805,SMT
PR17,PR28
225682900001 CONDUCTIVE TAPE;DC,M/B,8599
271002331301 RES;330 ,1/10W,5% ,0805,SMT
FR3,FR4,R14,R15
271002472301 RES;4.7K ,1/10W,5% ,0805,SMT
PR5,PR6
271035012711 RES;.012,1W,1%,2010,LR2010,IRC,S
PR73
227675400003 EPE PAD;K/B,8355
227682900001 END CAP;R,8599
227682900002 END CAP;L,8599
242600000001 LABEL;PAL,20*5MM,COMMON
271044060301 RES;.006 ,1.5W,5% ,2512,SMT
271045107101 RES;.01 ,1W ,1% ,2512,SMT
PR1,PR85
271045127102 RES;.012,1W,1%,2512,SMT
PR74
271046068101 RES;.006 ,1.5W ,1% ,2512,SMT;PWR
RM4
242600000145 LABEL;10*10,BLANK,COMMON
271061000002 RES;0 ,1/16W,0402,SMT
R102,R105,R119,R121,R129,R134
242600000232 LABEL;6*6MM,GAL,BLANK,COMMON
271061101103 RES;100 ,1/16W,1% ,0402,SMT
R120,R181,R184,R235,R24,R261,R
242600000378 LABEL;27*7MM,HI-TEMP 260'C
271061102105 RES;1K ,1/16W,1% ,0402,SMT
R12,R166,R217,R218
242600000385 LABEL;27*10,LAN ID BAR CODE
271061102303 RES;1K ,1/16W,5% ,0402,SMT
R1,R194,R200,R213,R288,R296,R3
242600000433 LABEL;BLANK,11*5MM,COMMON
271061103102 RES;10K ,1/16W,1% ,0402,SMT
R10,R11,R195,R212,R27,R28
242600000088 LABEL;BAR CODE,125*65,COMMON
242600000145 LABEL;10*10,BLANK,COMMON
133
8399 N/B Maintenance
9. Spare Part List(2)
Part Number Description
Location(S)
Part Number Description
Location(S)
271061103501 RES;10K ,1/16W,5% ,0402,SMT
R112,R113,R117,R13,R145,R146,R
271061604011 RES;60.4 ,1/16W,1% ,0402,SMT
R81,R90
271061104501 RES;100K ,1/16W,5% ,0402,SMT
R176,R177,R216,R219,R221,R222
271061619211 RES;6.19K,1/16W,1% ,0402,SMT
R287
271061105501 RES;1M ,1/16W,5% ,0402,SMT
R292
271061649212 RES;6.49K,1/16W,1% ,0402,SMT
R70
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R345
271061681501 RES;680 ,1/16W,5% ,0402,SMT
R131,R135,R138,R139,R148,R150
R183,R186,R207,R208,R209,R210
271061753101 RES;75,1/16W,1%,0402,SMT
R46,R47,R48,R49
R87
271061821101 RES;820 ,1/16W,1% ,0402,SMT
R114,R118
R289
271061822501 RES;8.2K ,1/16W,5% ,0402,SMT
R290,R411
R127,R128,R179,R182,R192,R193
271061900101 RES;90.9,1/16W,1%.0402,SMT
R14
R68,R69
271071000002 RES;0 ,1/16W,5% ,0603,SMT
L36,L37,L57,PR10,PR12,PR13,PR
R91
271071000002 RES;0 ,1/16W,5% ,0603,SMT
R42,X38
R170,R448
271071100302 RES;10 ,1/16W,5% ,0603,SMT
PR108,PR109,PR18,PR31,PR34,P
R241,R244,R265,R420,R423
271071101301 RES;100 ,1/16W,5% ,0603,SMT
R11,R12,R13,R17,R18,R35,R36
R154,R172,R173,R225,R227,R228
271071102102 RES;1K ,1/16W,1% ,0603,SMT
PR37,PR52
R165,R315,R350,R445
271071102302 RES;1K ,1/16W,5% ,0603,SMT
R11
R450
271071103101 RES;10K ,1/16W,1% ,0603,SMT
PR16,PR62,PR90,PR95
R55
271071103302 RES;10K ,1/16W,5% ,0603,SMT
PR22,R376,R433
R259,R260
271071103302 RES;10K ,1/16W,5% ,0603,SMT
R1,R37,R38
R229,R323
271071104101 RES;100K ,1/16W,1% ,0603,SMT
R2,R3
R108,R109,R110,R111,R130,R137
271071104302 RES;100K ,1/16W,5% ,0603,SMT
R7
R178,R214,R223,R382,R386
271071104302 RES;100K ,1/16W,5% ,0603,SMT
PR103,PR3,PR57,PR72,PR75,PR9
271061474501 RES;470K ,1/16W,5% ,0402,SMT
R123,R211,R32
271071104701 RES;100K ,1/16W,.1%,0603,SMT
PR86
271061499012 RES;49.9 ,1/16W,1% ,0402,SMT
R101,R107,R61,R66,R77,R78
271071105301 RES;1M ,1/16W,5% ,0603,SMT
PR2,PR49,PR56,R303
271061512102 RES;5.1K ,1/16W,1% ,0402,SMT
R67
271071105301 RES;1M ,1/16W,5% ,0603,SMT
R16,R39
271061562501 RES;5.6K ,1/16W,5% ,0402,SMT
R328,R356
271071107311 RES;107K ,1/16W,1% ,0603,SMT
PR21,PR69
271061564101 RES;560K ,1/16W,1% ,0402,SMT
R224,R26,R29,R353,R4,R9
271071111101 RES;110 ,1/16W,1% ,0603,SMT
R156
271061106501 RES;10M ,1/16W,5% ,0402,SMT
271061121501 RES;120 ,1/16W,5% ,0402,SMT
271061152501 RES;1.5K ,1/16W,5% ,0402,SMT
271061203102 RES;20K ,1/16W,1% ,0402,SMT
271061220501 RES;22 ,1/16W,5% ,0402,SMT
271061222501 RES;2.2K ,1/16W,5% ,0402,SMT
271061300131 RES;300 ,1/16W,5% ,0402,SMT
271061302101 RES;3K ,1/16W,1% ,0402,SMT
271061330501 RES;33 ,1/16W,5% ,0402,SMT
271061331304 RES;330 ,1/16W,5% ,0402,SMT
271061361101 RES;360 ,1/16W,1% ,0402,SMT
271061401101 RES;402,1/16W,1%.0402,SMT
271061464112 RES;4.64K ,1/16W,1% ,0402,SMT
271061470501 RES;47 ,1/16W,5% ,0402,SMT
271061471501 RES;470 ,1/16W,5% ,0402,SMT
271061472501 RES;4.7K ,1/16W,5% ,0402,SMT
271061473501 RES;47K ,1/16W,5% ,0402,SMT
134
8399 N/B Maintenance
9. Spare Part List(3)
Part Number Description
Location(S)
Part Number Description
Location(S)
271071124311 RES;124K ,1/16W,1% ,0603,SMT
PR98
271071348111 RES;3.48K,1/16W,1% ,0603,SMT
PR29
271071131101 RES;130 ,1/16W,1% ,0603,SMT
R14A
271071348812 RES;34.8 ,1/16W,1%,0603,SMT
R174,R180
271071137271 RES;13.7K,1/16W,.1%,0603,SMT
PR101
271071402111 RES;4.02K,1/16W,1% ,0603,SMT
PR50
271071143112 RES;14K,1/16W,1%,0603,SMT
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PR15
271071432111 RES;4.32K,1/16W,1% ,0603,SMT
R10
R245,R247
271071432211 RES;43.2K,1/16W,1% ,0603,SMT
R1
R132
271071442113 RES;44.2 ,1/16W,1% ,0603,SMT
R100,R30
PR60
271071472302 RES;4.7K ,1/16W,5% ,0603,SMT
PR105,PR106
R12
271071473101 RES;47K ,1/16W,1% ,0603,SMT
PR11
PR61,PR68,PR9,PR91
271071474301 RES;470K ,1/16W,5% ,0603,SMT
PR4
PR102
271071478301 RES;4.7 ,1/16W,5% ,0603,SMT
PR89
PR66,PR67
271071499111 RES;4.99K,1/16W,1% ,0603,SMT
PR32,PR88
R168
271071499311 RES;499K ,1/16W,1% ,0603,SMT
PR87
R41
271071499811 RES;49.9 ,1/16W,1% ,0603,SMT
R19,R25
PR82
271071510301 RES;51 ,1/16W,5% ,0603,SMT
R421,R422
PR48,PR65,PR70
271071563101 RES;56K ,1/16W,1% ,0603,SMT
R6
PR104
271071619111 RES;6.19K,1/16W,1% ,0603,SMT
PR96
PR99
271071634211 RES;63.4K,1/16W,1% ,0603,SMT
PR59
PR100
271071753301 RES;75K ,1/16W,5% ,0603,SMT
R8
R246,R248
271071806812 RES;80.6 ,1/16W,1% ,0603,SMT
R151
R366,R367,R372,R373,R374,R375
271071822301 RES;8.2K ,1/16W,5% ,0603,SMT
R256,R388
271071301311 RES;301K ,1/16W,1% ,0603,SMT
R13,R3
271071866111 RES;8.66K,1/16W,1% ,0603,SMT
PR51
271071302101 RES;3K ,1/16W,1% ,0603,SMT
PR30,PR33
271071887111 RES;8.87K,1/16W,1% ,0603,SMT
R133
271071330302 RES;33 ,1/16W,5% ,0603,SMT
R157,R169
271071909101 RES;9.09K,1/16W,1% ,0603,SMT
PR8
271071333301 RES;33K ,1/16W,5% ,0603,SMT
R2
271072383011 RES;383 ,1/10W,1% ,0603,SMT
R319,R352
271071333301 RES;33K ,1/16W,5% ,0603,SMT
PR76
271072474101 RES;470K ,1/10W,1% ,0603,SMT
R4,R5,R9
271071151103 RES;15 ,1/16W,1% ,0603,SMT
271071169011 RES;169 ,1/16W,1% ,0603,SMT
271071202102 RES;2K ,1/16W,1% ,0603,SMT
271071202301 RES;2K ,1/16W,5% ,0603,SMT
271071203101 RES;20K ,1/16W,1% ,0603,SMT
271071203701 RES;20K ,1/16W,.1%,0603,SMT
271071204101 RES;200K ,1/16W,1% ,0603,SMT
271071220101 RES;22 ,1/16W,1% ,0603,SMT
271071224301 RES;220K ,1/16W,5% ,0603,SMT
271071226311 RES;226K ,1/16W,1% ,0603,SMT
271071228301 RES;2.2 ,1/16W,5% ,0603,SMT
271071243211 RES;24.3K,1/16W,1% ,0603,SMT
271071249111 RES;2.49K,1/16W,1% ,0603,SMT
271071249311 RES;249K ,1/16W,1% ,0603,SMT
271071270301 RES;27 ,1/16W,5% ,0603,SMT
271071272301 RES;2.7K ,1/16W,5% ,0603,SMT
135
8399 N/B Maintenance
9. Spare Part List(4)
Part Number Description
Location(S)
Part Number Description
Location(S)
271571000301 RP;0*8 ,16P ,1/16W,5% ,1606,SM
RP59,RP61,RP62,RP63,RP68,RP7
272002225701 CAP;2.2U ,CR,16V ,+80-20%,0805,Y
C420
271571100301 RP;10*8 ,16P ,1/16W,5% ,1606,SM
RP19,RP21,RP22,RP24,RP25,RP2
272005104401 CAP;.1U ,CR,50V,10%,0805,X7R,IN
PC19,PC34
271571470301 RP;47*8 ,16P ,1/16W,5% ,1606,SM
RP14,RP15,RP16,RP17,RP18
272005104404 CAP;.1U,CR,50V,10%,0805,SMT
PC111,PC80,PC93
271571680302 RP; 68*8 ,16P,1/16W,5% ,1606,SM
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RP31,RP33,RP34,RP36,RP37,RP3
272005104705 CAP ;1U CR 50V +80-20% 0805 Y5V
C17,C18
PR107
272011106407 CAP;10U,10V,+/-10%,1206,X5R,SMT,
PC10,PC110,PC13,PC3,PC6,PC68
RP13,RP58,RP69
272011106701 CAP;10U ,10V,+80-20%,1206,Y5V,S
PC103,PC70
RP10,RP11,RP12,RP52,RP6,RP7,R
272011475401 CAP;4.7U ,10%,10V ,1206,X7R,SMT
C41
RP43
272012105401 CAP;1U ,CR,16V ,10%,1206,X7R,S
C14A,C14B
RP72,RP73
272012106701 CAP;10U ,16V ,+80-20%,1206,Y5U,
PC48
RP20,RP23,RP26,RP29
272021226701 CAP;22U ,10V,+80-20%,1210,Y5V,S
PC97
RP3
272023106002 CAP;10U,25V,M,1210,T2.8MM,X5R,SM
PC131,PC137,PC142
RP1,RP45,RP57
272023106501 CAP;10U ,25V ,20%,1210,Y5U,SMT
PC11
RP46,RP49,RP50
272023106502 CAP;10U,25V,M,1210,T2.5MM,X5R,SM
PC24,PC30,PC43,PC49,PC5,PC51
RP44
272023475401 CAP;4.7U ,25V ,10%,1210,X5R,SMT
C1
RP32,RP35,RP38,RP41
272030102301 CAP;100P,3KV,5%,1808,NPO,SMT,PWR
C20
RP2,RP4
272030102405 CAP;1000P,CR,3KV,10%,1808,X7R,TU
C2,C3,C666,C667,C74
RP47,RP53,RP56,RP60,RP66,RP6
272071105403 CAP;1U ,10V ,10%,0603,X5R,SMT
C10,C4
RP55
272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5
C311,C375
RP48,RP51,RP54,RP64,RP65,RP7
272071225401 CAP;2.2U ,CR,6.3V ,10%,0603,X5R,
C282,C336
PC145,PC147,PC44
272071332401 CAP;.33U ,10V ,10%,0603,X7R,SMT
C2
272001106702 CAP;10U,6.3V,+- 20%,0805,X5R,SMT
C115,C125,C126,C127,C128,C132
272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM
C12,C17,C6
272001106703 CAP;10U,10V,+80-20%,0805,Y5V,SMT
C100,C105,C12,C120,C158,C164,C
272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM
C339,PC138
272001475403 CAP;4.7U,10V,10%,0805,X5R,SMT
C122,C140,C202,C204,C243,C260
272072104702 CAP;.1U ,16V,+80-20%,0603,Y5V,S
PC20,PC22,PC28,PC31,PC47,PC6
272001475701 CAP;4.7U ,CR,10V ,+80-20%,0805,Y
C342,C351,C421,C96
272072224402 CAP;.22U ,16V ,10%,0603,X7R,SMT
C108,C131,C136,C15,C156,C16,C2
272002105701 CAP;1U ,CR,16V ,-20+80%,0805,Y5
PC135,PC23,PC33
272072224701 CAP;.22U ,16V ,+80-20%,0603,Y5V,
C116,C117,C402,C403,C404,C405
271586026101 RES;.02 ,2W,1%,2512,SMT
271591000701 RP;0*4,8P,1/16W,.1%,0804,SMT
271591220301 RP;22*4,8P,1/16W,5%,0804,SMT
271591470301 RP;47*4,8P,1/16W,5%,0804,SMT
271591471301 RP;470*4,8P,1/16W,5%,0804,SMT
271611100301 RP;10*4 ,8P ,1/16W,5% ,0612,SMT
271611102301 RP;1K*4 ,8P ,1/16W,5% ,0612,SMT
271611103301 RP;10K*4 ,8P ,1/16W,5% ,0612,SMT
271611153301 RP;15K*4 ,8P ,1/16W,5% ,0612,SMT
271611330301 RP;33*4 ,8P ,1/16W,5% ,0612,SMT
271611680301 RP;68*4 ,8P ,1/16W,5% ,0612,SMT
271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT
271621103302 RP;10K*8 ,10P,1/32W,5% ,1206,SMT
271621222301 RP;2.2K*8,10P,1/16W,5% ,1206,SMT
271621472302 RP;4.7K*8,10P,1/32W,5% ,1206,SMT
272001105403 CAP;1U ,10%,10V ,0805,X7R,SMT
136
8399 N/B Maintenance
9. Spare Part List(5)
Part Number Description
Location(S)
Part Number Description
Location(S)
272072473402 CAP;.047U,16V ,10%,0603,X7R,SMT
C266
272075471409 CAP; 0.0047U CR 50V 10% 0603 X7
C19
272072683404 CAP;.068U ,16V ,10%,0603,X7R,SMT
C16
272075472701 CAP;4700P,50V ,+ -20%,0603,X7R,S
PC37
272073180401 CAP;18P ,CR,25V ,10%,0603,NPO,S
C355,C356
272075822401 CAP;8200P,CR,50V,10%,X7R,0603,SM
PC106
272073223401 CAP;.022U,CR,25V ,10%,0603,X7R,S
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C9
272102100401 CAP;10P ,50V ,+-10%,0402,NPO,SM
C321,C64,C66
C103,C107
272102104401 CAP;.1U ,CR,10V,10%,0402,X5R,SM
C102,C104,C106,C124,C13,C130,C
C15A
272102105701 CAP;1U ,CR,6.3V ,80-20%,0402,Y
C110,C111,C118,C121,C135,C141
PC105,PC109,PC75,PC92
272102224701 CAP;.22U ,10V ,+80-20%,0402,Y5V,
C137,C225,C264,C278
PC1,PC123,PC127,PC132,PC139,P
272102334701 CAP;.33U ,CR,10V ,+80-20%,0402,Y
C139
PC108
272105059401 CAP;5P
C283
PC21,PC36,PC84
272105101401 CAP;100P ,50V ,5%,0402,COG,SMT
C1,C223,C224
C11,C13,C3,C8
272105101402 CAP;100P ,50V ,+ -10%,0402,NPO,S
C114,C129,C206,C261
PC102,PC116,PC117,PC128,PC14
272105102408 CAP;1000P,CR,50V,10%,0402,X7R,SM
C10,C138,C180,C22,C250,C37,C38
PC90
272105102501 CAP;1000P,50V ,+/-20%,0402,X7R,S
C123
C15,C16,C35,C37,C39
272105103402 CAP;.01U ,CR,25V ,10%,0402,X7R,S
C150,C152
PC119,PC124,PC134,PC136,PC14
272105103702 CAP;.01U ,50V,+80-20%,0402,SMT
C112,C119,C154,C175,C179,C25,C
C28,C30,C31,C32,C33,C34
272105104701 CAP;.1U ,16V,+80-20%,0402,SMT
C101,C109,C113,C155,C169,C173
C344,C425,PC107,PC113,PC118,P
272105220402 CAP;22P ,50V ,+ -10%,0402,NPO,S
C242,C249,C252,C255,C257,C259
PC104,PC98
272105221403 CAP;220P ,CR,50V ,10%,0402,X7R,S
C406
C85,C87
272105222501 CAP;2200P,50V ,+/-20%,0402,X7R,S
C99
C5
272105270303 CAP;27P ,50V ,5%,0402,COG,SMT
C241,C246,C395,C396
272075222701 CAP;2200P,50V ,+/-20%,0603,X7R,S
C133,C134
272105271403 CAP;270P ,50V,+-10%,0402,X7R,SMT
C162,C172,C174,C201,C357,C378
272075223702 CAP; 0.22U CR 50V +80-20% 0603
C29,C40,C41
272105332402 CAP;3300P,50V,10%,0402,SMT
C80
272075330401 CAP;33P ,CR,50V ,10%,0603,X7R,S
PC32
272431227402 CAP;220U,2V,-35/+10%,H1.9,S,SP-C
PC35,PC64
272075470401 CAP;47P ,50V ,10%,0603,COG,SMT
PC100,PC101
272431227503 CAP;150U ,POLY,6.3V,20%,7243,SMT
PC7,PC77,PC9
272075471401 CAP;470P ,50V,10%,0603,X7R,SMT
C36
272602107501 EC;100U,16V,M,6.3*5.5,-55+85'C,S
C227,C235,C236
272073392401 CAP;3900P,50V,10%,0603,X7R,SMT
272073472301 CAP;4700P,CR,50V ,5% ,0603,X7R,S
272075102402 CAP;1000P,CR,50V,10%,0603,X7R,IN
272075102403 CAP;1000P,CR,50V,10%,0603,X7R,SM
272075102501 CAP;1000P,CR,50V ,20%,0603,X7R,S
272075102701 CAP;1000P,50V ,+/-20%,0603,X7R,S
272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S
272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S
272075103403 CAP;.01U ,50V,10%,0603,X7R,SMT
272075103408 CAP ;0.1U CR 50V 10% 0603 X7R S
272075103702 CAP;.01U ,50V,+80-20%,0603,Y5V,S
272075103706 CAP; 0.1U CR 50V +80-20% 0603 Y
272075104701 CAP;.1U ,50V,+80-20%,0603,Y5V,S
272075181301 CAP;180P ,50V ,5% ,0603,NPO,SMT
272075220301 CAP;22P ,50V ,5% ,0603,COG,SMT
272075222401 CAP;2200P,50V ,10%,0603,X7R,SMT
,50V,+-10%,0402,SMT
137
8399 N/B Maintenance
9. Spare Part List(6)
Part Number Description
Location(S)
Part Number Description
Location(S)
272625220401 CP;22P*4 ,8P,50V ,10%,1206,NPO,S
CP1,CP2
282674112602 IC;SN74AHCT1G126DCK,NON-INVERTIN
272990100301 CAP;10P,3000V,+- 5%,NPO,SMT
C19
282674244004 IC;74HCT244D,OCT TRI-ST BUF,SOIC
U23,U24
273000130001 FERRITE CHIP;120OHM/100MHZ,1608,
L52
283467540001 IC;EEPROM,M24C02-WMN6T,2K,SO8,SM
IC6
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273000130006 FERRITE CHIP;600OHM/100MHZ,.2A,1
L100,L101,L43,L48,L50,L501,L5
283467540002 IC;EEPROM,M93C46-WMN6T,64*16 BIT
273000130019 FERRITE CHIP;120OHM/100MHZ,1608,
L10,L11,L12,L13,L14,L15,L16,L1
283480404001 IC;FLASH,256K*8-70,PLCC32,A29002
273000130038 FERRITE CHIP;600OHM/100MHZ,1608,
L38,L39,L40,L49,L57,R124
284500781001 IC;G781,TEMPERATURE MTR,SO8
U5
273000130062 INDUCTOR;120nH,10%,0603,SMT
L31
284501617005 IC;VT1617A,AUDIO CODEC,TQFP,48P
U10
273000150002 FERRIET CHIP;120OHM/100MHZ,2012,
L2,L24,L27,L29,L3,L30,L32,L33,
284501622003 IC;VT1622AM,TV ENCODER,PQFP,64P,
U3
273000150013 FERRITE CHIP;120OHM/100MHZ,2012,
L58,PL1,PL10,PL11,PL12,PL14,P
284506103009 IC;VT6103L,LAN-PHY,LQFP,48P,SMT
U2
273000150313 CHOKE COIL;90OHM/100MHZ,20%,2012
L20,L21,L22,L23,L26,L28,L97,L9
284508235007 IC;VT8235,0340CD,SOUTH BRIDGE,BG
U20
273000500092 CHOKE COIL;2.2UH ,20%,16A,3.5MM
PL7
284508800006 IC;VIA K8N800CE,N.B.,BGA578,SMT
U12
273000500115 CHOKE COIL;400uH MIN,120mΩ MAX;
L105,L19
284516310001 IC;VT1631,LVDS TRANSMITTER,TQFP,
U9
273000990018 INDUCTOR;10uH,CDRH125,SUMIDA,SMT
PL13,PL15
284583950002 IC;W83L950D-Ver.C,LPC_KBC,LQFP,8
273000990021 INDUCTOR;33uH,CDRH124,SUMIDA,SMT
PL20
284595040301 IC;ICS950403,TIMING CTL HUB FOR
U14
273000990127 INDUCTOR;IHLP5050CE-01-0.68uH,VI
PL3,PL4
286101428001 IC;G1428,AMPLIFIER,TSSOP,24P,SMT
U13
273000990186 INDUCTOR;3.0UH,30%,CDRH6D28,H2.8
PL18
286104073001 IC;MAX4073F,I-SENSE AMP,SOT23,6P
PU9
273001050028 XSFORMER;10/100 BASE,LF-H41S,SMT
U4
286300338001 IC;SC338,FET CTRL,SC,MSOP-10
PU3
T1
286300594001 IC;TL594C,PWM CONTROL,SO,16P
PU19
X3,X6
286301410002 IC;CB1410Q_B0,PCI/CARDBUS,LQFP,1
U26
274013276103 XTAL;32.768KHZ,20PPM,12.5PF,CM20
X5
286301414001 IC;MM1414,PROTECTION,TSOP-20A,PR
IC7
281101015001 IC;MP1015EM-Z,CCFL CTRL,TSSOP20,
U1
286301470001 IC;SC1470,PWM CTRL,TSSOP,14P,SMT
PU11
282574186002 IC;74AHCT1G86,SINGLE,XOR,SOT23,S
U11
286302211006 IC;CP2211,POWER DISTRI SW,REV.C1
U27
282607408001 IC;74HCT08PW,2-INPUT AND GATE,TS
U22,U8
286302996001 IC;G2996,DDR,GMT,SOP8FD,SMT
PU13
286303107001 IC;AMS3107C,3.3V,1%,VOL REGULATO
U19
286303728002 IC;LTC3728LX,PWM CTRL,LTC,5X5 QF
PU14
273001050127 XFMR;CI8.5,30T/2150T,300mH,SMT,o
274011431414 XTAL;14.318MHZ,32PF,50PPM,8*4.5,
282607408002 IC;SN74HCT08PW,2-INPUT AND GATE,
282674112601 IC;74HCT1G126GW,NON-INVERTING BU
U39,U40
U15
138
8399 N/B Maintenance
9. Spare Part List(7)
Part Number Description
Location(S)
Part Number Description
Location(S)
286304377001 IC; MAX4377F,I-SENSEAMP ,MSOP8,S
PU20
288200420001 TRANS;AOB420,30V/110A,.010OHM,N-
PQ4,PQ7
286306207001 IC;ISL6207CB,PWM DRIVER,SO8,SMT
PU5,PU7
288200717001 DIODE;RB717F,SCHOTTKY,40V,SOT323
SD2
286306559002 IC;ISL6559,MULTI-PHASE PWM CTL,S
PU6
288202222001 TRANS;MMBT2222AL,NPN,TO236AB
PQ21
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286308800007 IC;AME8800DEFT,VOL REG.,SOT89,3P
U17
288202237002 TRANS;MUN2237T1,NPN,SOT-23,SMT,O
PQ17,Q26,Q31
286308804002 IC;AME8804AEEY,ADJ,0.3A,LDO,SOT2
U7
288202240001 TRANS;MUN2240T1,NPN,SOT-23,ON
Q1,Q10,Q13,Q16,Q17,Q22,Q23,Q2
286329513001 IC;AMS2951CS-3.3,3.3V,150MA VLOT
U28
288203400001 TRANS;AO3400,N-MOSFET,SOT-23
Q2
U38
288203403001 TRANS;AO3403,P-MOSFET,SOT-23,ALP
Q11,Q9
IC5
288203413001 TRANS;AO3413,P-MOSFET,SOT-23
Q15,Q36
PD11
288204403008 TRANS;AO4403,P-MOSFET,46mOHM (VG
U21,U35
288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80
D12,PD16
288204407001 TRANS;AO4407,P-MOS,.01OHM,SO8,SM
PQ15,PQ23,PU1
288100034004 DIODE;SSA34,40V,3A,SMA
PD14,PD17,PD7,PD8
288204409001 TRANS;AO4409,P-MOSFET,SO-8P,MSL,
Q10,Q14
288100054002 DIODE;BAT54C,SCHOTTKY DIODE,SOT2
D17
288204410010 TRANS;AO4410,N-MOSFET,ID=18A,0.0
PU10
288100056003 DIODE;BAW56,70V,215mA,SOT-23
D1
288204422001 TRANS;AO4422,24mOHM,N-MOSFET,SOI
PU12,PU17,PU2,PU4,U18
288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM
ZD3,ZD4
288204832001 TRANS;SI4832DY,N-MOSFET,.028OHM,
PU16
288100056017 DIODE;BAW56LT1,70V,215MA,SOT-23,
PD12
288204912001 TRANS;AO4912,24mOHM ,SMT
PU15
288100701002 DIODE;BAV70LT1,70V,225MW,SOT-23
D14,PD5,PD6
288221371002 TRANS;MUN2137T1,PNP,SMT,ON
PQ24
288101040006 DIODE;SBM1040,10A,SCHOTTKY,POWER
PD3
288227002001 TRANS;2N7002LT1,N-CHANNEL FET,SO
Q18,Q19,Q21,Q29,Q35,Q37,Q5,Q6
288104148001 DIODE;RLS4148,200MA,500MW,MELF,S
D11
288227002006 TRANS;2N7002LT1,N-CHANNEL FET,ES
PQ1,PQ10,PQ11,PQ12,PQ13,PQ1
288105524003 DIODE;BZV55-C24,ZENER,5%,SOD-80,
PD2
291000000203 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM
J2
D3
291000000708 CON;BATTERY,7P,FM,2.5MM,BTG-07AR
CON1
288111544001 DIODE; 1SR-154-400 400V 1.0A
D4
291000013016 CON;HDR,MA,15P*2,1MM,H4.25,ST,SM
J8
288200144003 TRANS;DTC144TKA,N-MOSFET,SOT-23
Q8
291000020204 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM
288200144008 TRANS;DTA144EKA,PNP,SMT
Q8
291000020222 CON;HDR,MA,2P*1,1.25MM,H4.2,ST,S
J11,J20,J6
288200301001 TRANS;FDV301N,N-CHANNEL,SOT23
Q20
291000020415 CON;HDR,MA,4P*1,1.25MM,ST,SMT,38
J13,J7
288200416001 TRANS;AOB416,30V/110A,.0065OHM,N
PQ2,PQ5
291000143011 CON;FPC/FFC,15P*2,.8MM,BD/BD,ST,
J15
286369229301 IC;G692L293T,RESET CIRCUIT,2.93V
286387506001 IC;S-875061EUP VOLT DETECTOR S
288100014010 DIODE;SS14,40V,1A,SMA,VISHAY
288110355001 DIODE;1SS355,80V,100mA,SOD-23,SM
139
8399 N/B Maintenance
9. Spare Part List(8)
Part Number Description
Location(S)
Part Number Description
Location(S)
291000150606 CON;FPC/FFC,6P,0.5MM,R/A,SMT
J18
312278206161 EC;820U ,2.5V,+-20%,8X12.5,OS-CO
PC25,PC29,PC53,PC58
291000152614 CON;FPC/FFC,26P,1MM,H=2.0,R/A,SM
J501
314100250502 XTAL;25MHZ,30PPM,20PF,49S,11.5*3
X1
291000611255 MINIPCI SOCKET;124P,0.8MM,H=9.2,
J22
314149800402 XTAL;8MHZ,30PPM,HC-49/S,6B080002
X4
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291000616807 CON;PCMCIA CARD,68P,929100000140
J502
316678100001 PCB;PWA-INVERTER BD (DA-1A10-A);
R0C
291000617542 IC SOCKET;AMD K8 BGA-PGA754-SKT,
U6
316684100001 PCB;PWA-8399-M BD
R02
291000622010 DIMM SOCKET; DDR,200P,REVERSE TY
J16
316684500001 PCB;PWA-Tarzan/BATT ,PR AND GA
291000622011 DIMM SOCKET; DDR,200P,H=9.2mm,SM
J17
323768410001 DDR SODIMM MODULE;256MB,PC3200,7
291000810818 CON;PHONE JACK,12P,R/A,RJ45,RJ11
J5
324180786803 IC;CPU,AMD-Athlon 64 3200+,OPGA,
D501,D502,D503,D504,D505,D50
331000000303 CON HOLDER;PCMCIA,331000000071,A
D510
331000007038 CON;BAT,7P,2.5mm,OCT,tBTD-007001
PJ2
F2,F3,F4
331000008091 CON;USB,MA,ST,4P*2,SMT,1-1470748
J3,J4,J9
PF1
331000050004 CON;CD-ROM,50P,0.8MM,H-10.4,R/A,
J21
PF2
331030044021 CON;HDR,FM,22P*2,2.0MM,SMT,C1783
J14
PF3
331678100001 CONNECTOR;7 PIN,1.25mm,SMT,ACES,
J1
F1
331720015071 CON;D,FM,15P,2.29,R/A,SUYIN
J2
F5
331840005013 CON;STEREO JACK,5P,R/A,28MF60-07
J10
297030100015 SW;TOGGLE,SPST,5V/1mA,4P,SMT,TAI
SW506
331840005014 CON;STEREO JACK,5P,R/A,28MF60-05
J12
297040105010 SW;PUSH BUTTOM,5P,SPST,12V/50MA,
SW1,SW501,SW502,SW503,SW50
331870007010 CON;MINI DIN,7P,R/A,W/GROUND,030
J1
310111103013 THERMISTOR;10K,1%,RA,DISK,103AT-
RT2
331910002006 CON;POWER JACK,2P,20VDC,5A,DIP
PJ1
310111103025 THERMISTOR;10K,1%,RA,DISK,103AT-
332110020097 WIRE;#20,UL1007,74MM,BLACK,YIYI;
CN6
310111103031 THERMISTOR;10K,1%,150MM,BN35-3H1
332110020175 WIRE;#20,UL1007,L=103MM,RED, PWR
CN10
294011200016 LED;GREEN,H0.8,0603,CL-190G,SMT
294011200200 LED;GREEN/RED,H0.8,W1.9,19-22SRV
295000010008 FUSE;1.1A,POLY SWITCH,1812,SMT
295000010016 FUSE;NORMAL,6.5A/32VDC,3216,SMT
295000010102 FUSE;FAST,3A,32V,1206,SMT,CERAMI
295000010116 FUSE;FAST, 10A, 86VDC, 6125,SMT
295000010154 FUSE;FAST,1.25A,63V,1206,SMT,043
295000100004 FUSE;FAST,1A,63V,1206,THIN FILM
312272263511 EC;22U,25V,20%,RA,8*10.5,105 ℃,O
PC112,PC115,PC27,PC52,PC54,P
332110020176 WIRE;#20,UL1007,70.5MM,BLACK,YIY
VL-VL
312273361501 EC;330U ,6.3V ,RA,M,6.3*7,+105C
C32,C33,C384
332110026097 WIRE;#26,UL1007,55MM,BLACK,PRC
CN8
312276806151 EC;680U ,6.3V,20%,D10,105'C,OS-C
PC114
332110026155 WIRE;26#,UL1061,L=115MM,YELLOW,
CN9
312278206151 EC;820U ,4V,+-20%,100*10.5,SP.OS
PC82,PC94
332810000212 PWR CORD;125V/7A,2P,BLACK, AMERI
140
8399 N/B Maintenance
9. Spare Part List(9)
Part Number Description
Location(S)
Part Number Description
333020000008 SHRINK TUBE;600V,125 ℃,Φ2.5mm,L
340684100004 HEATSINK ASSY;CPU,K8 HAMMER,MPT,
333025000004 SHRINK TUBE;300V,125,I.D=2.5,T=0
340684100005 HEATSINK ASSY;CPU,K8 HAMMER,AVC,
333050000120 SHRINK TUBE;600V,105'C,D0.8*9MM,
340684100006 HAETSINK ASSY;SYSTEM,M/B,MPT,839
335152000044 CFM-BAT;FUSE THERMAL 98'C
335152000085 FUSE; 128 DC-7A/50V 139 ℃only UC
335152000094 FUSE;LR4-900,POLY SWITCH
335152000100 FUSE; THERMAL,SF91E-1/94 ℃,10A/2
338536010006 BATTERY;LI,3.6V/2.0AH,18650,PANA
339115000046 MICROPHONE;-62dB+-2dB,D6.0*H2.7,
340682900001 HOUSING ASSY;LCD,8599
340682900002 COVER ASSY;LCD,8599
340682900003 HINGE;R,8599
340682900004 HINGE;L,8599
340682900005 HINGE;R,SZS,8599
340682900006 HINGE;L,SZS,8599
340682900009 BRACKET ASSY;TOUCH-PAD,8599
340682900010 SPEAKER ASSY; 28*4.3,2W,FENG-CHI
340682900011 SPEAKER ASSY; 28*4.3,2W,VECO,859
340682900015 HOUSING ASSY;BOTTOM,8599
340682900017 COVER ASSY;CPU,8599
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Location(S)
340684100007 HAETSINK ASSY;SYSTEM,M/B,AVC,839
F2
341675300008 STANDOFF;CPU,8080
MTG501,MTG502
341682900003 BRACKET;LCD,R,8599
341682900004 BRACKET;LCD,L,8599
342502900001 CONTACT PLATE;W4L27T0.15,7068
MIC501
342503200003 CONTACT PLATE;W4L18T0.15,7521/GR
342503400005 CONTACT PLATE;W5L24T0.13,7170LI,
342503400005 CONTACT PLATE;W5L24T0.13,7170LI,
342673100024 CONTACT PLATE;W5L62T0.13 ,1/3T,8
342682900009 BRACKET;ROM,8599
342682900010 CONTACT PLATE;W5L28T0.15MM,BATTE
344503100304 DUMMY;D18L65,BATT ASSY,7521C
344672300025 DUMMY CARD;PCMCIA,MANGUSTA
344682900012 COVER;HINGE,8599
344682900016 COVER;BATTERY,8599
344682900017 HOUSING;BATTERY,8599
345668900016 SPONGE;BIOS BATT,M722
340682900018 COVER ASSY;MINIPCI,8599
345675400023 RUBBER;DOWN LCD,8355
340682900021 SHIELDING ASSY;HDD,8599
345682900005 SPONGE;DUAL DDR,M/B,8599
340682900022 DVD+RW BEZEL ASSY;SDW-041,8599
345682900006 SPONGE;SPSPEND SWITCH,M/B,8599
340684100001 COVER ASSY;TOP,8399
345682900009 SPONGE;HINGE COVER,8599
340684100003 SHIELDING ASSY;BOTTOM,8399
346502800004 INSULATOR;BATT ASSY,BATT+,BATT-,
141
8399 N/B Maintenance
9. Spare Part List(10)
Part Number Description
Location(S)
Part Number Description
346503100001 INSULATOR;BATT ASSY,THERMAL FUSE
347110020025 GASKET;1,10,020,025
346503100005 INSULATOR;5,BATTERY ASSY,7521Li
347110035035 GASKET;1,10,035,035
346503200202 INSULATOR;BATT ASSY,ONE ROUND,BL
347110040012 GASKET;1,10,040,012
346503400503 INSULATOR;BATT ASSY,W7L13,8175
346673420003 MYLAR;15*10*0.8,8640P
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347110080025 GASKET;1,10,080,025
361200001018 CLEANNER;YC-336,LIQUID,STENCIL/P
346677300001 INSULATOR;FIBER,UL94V-0,D=17.5mm
361200003047 SOLDER PASTE;NO CLEAN,RMA,CK3000
346678600005 INSULATOR;FIBER,UL94V-0,64X15,T=
361400003005 ADHESIVE;HEAT,TRANSFER,HTA-48(W)
346682900007 NYLON;BATTERY PULL,8599
361400003021 SOLDER CREAM;NOCLEAN,P4020870980
346682900009 AL-FOIL;T/P BRACKET,8599
346682900010 AL-FOIL;T/P SWITCH,MB,8599
346682900013 SPONGE;M/B,8599
361400003030 ADHESIVE;ABS+PC PACK,G485,CEMIDA
370102010205 SPC-SCREW;M2L2(t0.3),N/W/WLK
370102010256 SPC-SCREW;M2L2.5,K-HD(t0.5) NLK,
346682900014 INSULATOR;AL-FOIL,INVERTER,8599
370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK
346684100002 INSULATOR;CARD BUS,8399
370102611001 SPC-SCREW;M2.6L10,NIB,K-HD,NY
346684100003 INSULATOR;SOUTH BRIDGE,8399
346684100004 TUBE;M/B,FOR ANTENNA,8399
370103010405 SPC-SCREW;M3L4,NIW,K-HD,T0.3
370103010414 SPC-SCREW;M3L4,KHD,NIW/NLK,D5.3,
346684400002 INSULATOR;RIBRE,63*15*0.25MM,BAT
370103010604 SPC-SCREW;M3L6,NIB,K-HD,t0.8,NYL
347104030012 GASKET;1,04,030,012
371102010310 SCREW;M2L3,K-HD(+),D3.8,t=0.75,N
347104030030 GASKET;1,04,030,030
347104045125 GASKET;1,04,045,125
347105020090 GASKET;1,05,020,090
Location(S)
371102010310 SCREW;M2L3,K-HD(+),D3.8,t=0.75,N
371102010610 SCREW;M2L6,K-HD(+),t0.75,NIB
371102610308 SCREW;M2.6L3,D3.5,t=0.5,K-HD,NIW
347105060030 GASKET;1,05,060,030
371102610406 SCREW;M2.6L4,K-HEAD(+),NIB
347105060060 GASKET;1,05,060,060
371102610607 SCREW;M2.6L6,K-HEAD(+),NIB
347108010012 GASKET;1,08,010,012
373101712351 T-SCREW;B,M1.7,L2.35,K-HD,2,NIB
347108080090 GASKET;1,08,080,090
377102650901 S-STANDOFF;M2.6DP3.5H9L1.1,NIW
347108150024 GASKET;1,08,150,024
377102651002 S-STANDOFF;M2.6DP5H12.5L4,NIW,NY
MTG3,MTG4
142
8399 N/B Maintenance
9. Spare Part List(11)
Part Number Description
Location(S)
Part Number Description
377244010002 STANDOFF;#4-40DP3.5H5L5.5,NIW
441684400006 CONTACT PLATE ASSY;PTC,S-TUBE,BL
411678100001 PWA;PWA-INVERTER BD,DA-1A10-A,PW
441684400010 CONTACT PLATE ASSY;W5L45T0.13,FU
411678100002 PWA;PWA-INVERTER BD,SMT,DA-1A10-
441684430003 BATT ASSY;11.1V,4.0Ah,LI,CASE CL
411684110001 PWA;PWA-8399-MAX,MOTHER BD
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Location(S)
441684430004 BATT ASSY;11.1V,4.0Ah,LI,CORE PA
411684110002 PWA;PWA-8399-MAX,MOTHER BD,T/U
442678800002 CFM Medion AC ADPT ASSY;19V,4.74
411684110003 PWA;PWA-8399-MAX,MOTHER BD,SMT
442680900051 TOUCHPAD MODULE;SYNAPTICS,TM42PU
411684430001 PWA;PWA-BATT,PCB BD,LI,4.0Ah,BL4
451682900001 HDD ME KIT;8599
411684430002 PWA;PWA-BATT,PCB BD,SMT,4.0Ah,BL
451682900002 LCD ME KIT;15",XGA,SAMSUNG,8599
412681400001 PCB ASSY;WIRELESS LAN CARD,MINI
451682900005 ROM ME KIT;8599
412684100001 CFM-Medion; PCB ASSY;FAX MODEM 5
451684110002 HOUSING KIT;8399 ID1
412684110001 FAX MODEM KIT;Creatix,8399-MAX I
451684110004 LABEL KIT;N-B,8399
413000020433 LCD;LTN150XB- L03,15",XGA,SAMSUN
461677400001 PACKING KIT;DA-1A05-A;PWR
416268411001 LT PF;15",XGA,SAMSUNG,8399-MAX I
461682900002 PACKING KIT;COMPACT,N-B,8599
421675400012 WIRE ASSY;BIOS,BATTERY,8355
481684100002 F/W ASSY;KBD CTRL,8399
U16
481684110001 F/W ASSY;SYS/VGA BIOS,8399-MAX
U25
421682900001 WIRE ASSY;LTN150XB-L03,8599
421682900011 WIRE ASSY;LTN150XB-L03,GREATLAND
523405320072 HDD DRIVE,40GB,2.5",IC25N040ATMR
421684100003 WIRE ASSY,MDC-MODEM,4-4PIN,8399
523430061910 DVD+RW DRIVE;SDW-041,QSI
421684100005 WIRE ASSY;ANTENNA,WHA-YU,8399
523468290001 DVD+RW ASSY;SDW-041,8599
421684110001 ANTENNA OPTION;8399 ID1
523468290004 HDD ASSY;Hitachi,IC25N040ATMR04,
422682900001 FFC ASSY;TOUCH-PAD,TENN-RICH,859
526268411004 LTXNX;8399/5SHE/40N/1UIX/B2X2A/X
422682900002 FFC ASSY;TOUCH-PAD,HONG-FU,8599
531020237940 KBD;88,UI,K011818G1,8599
422682900003 FFC ASSY;TOUCH-PAD,CEI,8599
600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC
431684110001 CASE KIT;Creaxtix,8399-MAX
600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC
441684110001 LCD ASSY;15",XGA,SAMSUNG,8399 ID
600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC
441684400003 BATT ASS'Y;11.1V,4.0Ah,LI,BL-424
624200010140 LABEL;5*20,BLANK,COMMON
143
8399 N/B Maintenance
9. Spare Part List(12)
Part Number Description
Location(S)
624200010140 LABEL;5*20,BLANK,COMMON
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P/N:526268411004
144
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5
4
3
2
1
REVISION
TAPEOUT DAY
2003/01/03
R00
MODEL : 8399
HISTORY
DESIGN FOR EVT
Revision 03
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R02
GND_USB
1.Connect CPU AF_18 to VDDIO ba se on Errata 108.
2.Change LDTSTOP pull high resistor location.
3.Add level shift circuit for ENPBLT from K8N800.
4.Add R436 pull high resistor for VT8235CD hardwar e strap pin SPKR.
5.Change R287 from 6.19K to 5.6K for USB2.0 eye pattern fail issue .
6.Remove AMS2951 but add a MOSFET between AMS3107 and +SVDD3 for cost
issue.
2004/05/20
R03
1
TP503
TP527
TOUCHPAD_METAL12 TOUCHPAD_METAL12
1
1.Add AMS2951 for KBC_VREF to solve battery not accuracy issue.
C
For MDC
13
12
11
10
5
4
3
2
1
6
7
8
9
10
For CPU
MTG10
MTG11
MTG12
ID3.2/OD8.0/IN4.5
ID3.2/OD8.0/IN4.5
ID3.2/OD8.0
B
1
1
MTG16
ID3.0/OD5.2
3
8
4
7
For PCMCIA
FD501
FIDUCIAL-MARK
FD502
FD503
FIDUCIAL-MARKFIDUCIAL-MARK
FD504
FIDUCIAL-MARK
1
1
1
1
6
12
11
10
5
4
5
6
7
8
9
12
11
10
2
1
9
3
2
1
3
2
1
MTG15
ID3.0/OD7.0
7
8
9
4
5
6
1
1
AGND
MTG14
ID3.0/OD7.0
MTG13
ID3.2/OD8.0
7
8
9
4
5
6
7
8
9
7
8
9
3
2
1
GND_USB
MTG9
ID3.0/OD7.0
MTG118-RD276-30X12
MTG118_RD30X12
3
2
1
13
12
11
10
4
5
6
5
4
3
2
1
3
2
1
7
8
9
7
8
9
3
2
1
13
12
11
10
13
12
11
10
4
5
6
GND_MDC
MTG8
ID3.0/OD7.0
MTG118-RD276-30X12
MTG118_RD30X12
MTG7
ID3.0/OD7.0
MTG118-RD276-30X12
MTG118_RD30X12
4
5
6
13
12
11
10
4
5
6
MTG3
MTG/ID2.1/OD5.0
7
8
9
13
12
11
10
4
5
6
MTG6
ID3.0/OD7.0
MTG118-RD276-30X12
MTG118_RD30X12
3
2
1
3
2
1
MTG5
ID3.0/OD7.0
MTG118-RD276-30X12
MTG118_RD30X12
6
7
8
9
10
MTG4
MTG/ID2.1/OD5.0
MTG19
ID3.0/OD7.0
MTG118-RD276-30X12
MTG118_RD30X12
MTG18
ID3.0/OD7.0
4
5
6
For 2nd FAN
12
11
10
MTG501
ID4.5/OD7.0
MTG502
ID4.5/OD7.0
FD1
FIDUCIAL-MARK
FD2
FD4
FIDUCIAL-MARKFIDUCIAL-MARK
FD3
FIDUCIAL-MARK
7
8
9
1
1
1
1
4
5
6
A
3
2
1
MTG20
ID3.0/OD7.0
MTG118-RD276-30X12
MTG118_RD30X12
13
12
11
10
7
8
9
13
12
11
10
4
5
6
A
3
2
1
3
2
1
7
8
9
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
3
2
1
C
COVER SHEET & SCREW HOLE
ClawHammer_HT&DDR(1/2)
ClawHammer_Power plane(2/2)
DIMM-SLOT & Termination
Clock Generator
NB VIA_K8N800 (1/2)
NB VIA_K8N800 (2/2)
SB VIA_VT8235CD (1/3)
SB VIA_VT8235CD (2/3)
SB VIA_VT8235CD (3/3)
TV Encoder & VGA Interface
LVDS Encoder & connector
HDD & CD_ROM Conntor
Cardbus Controller
Mini PCI Interface
LAN PHY
USB2.0 & Flash ROM
Audio CODEC
KBC(W83L950D)
POWER ON PERPHERIAL CIRCUIT
+1.25V(LP2996)&+2.5V(RT9202)
+1.5V&+1.2V(SC338)
ADINP & Discharge
Charging (TL594C)
CPU core ( ISL6559 )
3V/5V(LTC3728)
TP504
TP502
TOUCHPAD_METAL12 TOUCHPAD_METAL12
1
Page
Title
1
Contexts
13
12
11
10
4
5
6
DRAWN DESIGN CHECK ISSUES
Title
7
8
9
<Title>
Size
C
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R03
411684100001
星期四, 五月 20, 2004
1
Sheet
1
of
26
5
4
3
2
1
ClawHammer-HT&DDR(1/2)
CPU_MD[0..63]
N26
L25
L26
J25
G25
G26
E25
E26
N29
M28
L29
K28
H28
G29
F28
E29
L0_CADOUT_L15
L0_CADOUT_L14
L0_CADOUT_L13
L0_CADOUT_L12
L0_CADOUT_L11
L0_CADOUT_L10
L0_CADOUT_L9
L0_CADOUT_L8
L0_CADOUT_L7
L0_CADOUT_L6
L0_CADOUT_L5
L0_CADOUT_L4
L0_CADOUT_L3
L0_CADOUT_L2
L0_CADOUT_L1
L0_CADOUT_L0
L0_CADOUT_L[0..15]
6 L0_CADOUT_L[0..15]
B
N27
M25
L27
K25
H25
G27
F25
E27
P29
M27
M29
K27
H27
H29
F27
F29
L0_CADOUT_H[15]
L0_CADOUT_H[14]
L0_CADOUT_H[13]
L0_CADOUT_H[12]
L0_CADOUT_H[11]
L0_CADOUT_H[10]
L0_CADOUT_H[9]
L0_CADOUT_H[8]
L0_CADOUT_H[7]
L0_CADOUT_H[6]
L0_CADOUT_H[5]
L0_CADOUT_H[4]
L0_CADOUT_H[3]
L0_CADOUT_H[2]
L0_CADOUT_H[1]
L0_CADOUT_H[0]
L0_CADOUT_L[15]
L0_CADOUT_L[14]
L0_CADOUT_L[13]
L0_CADOUT_L[12]
L0_CADOUT_L[11]
L0_CADOUT_L[10]
L0_CADOUT_L[9]
L0_CADOUT_L[8]
L0_CADOUT_L[7]
L0_CADOUT_L[6]
L0_CADOUT_L[5]
L0_CADOUT_L[4]
L0_CADOUT_L[3]
L0_CADOUT_L[2]
L0_CADOUT_L[1]
L0_CADOUT_L[0]
RESET_L
PWROK
TRST_L
TMS
THERMTRIP_L
THERMDC
THERMDA
TDO
TDI
TCK
+2.5VS_DDR
1
Change to 34.8 Ohm
LDTSTOP# 6,10
LDTSTOP_NB# 6
TP507
1
TP508
1
TP514
AF20
AE18
B21
E20
A20
A27
A26
A22
A21
E17
BP1
BP3
1
TP515
1
TP532
4
4
4
4
SCANSHENA
C12-RESERVE
MEMADDA14
1
1
SINCHN
SCANSHENB
D12-RESERVE
MEMADDB14
1
SCANEN
SCANCLK1
E13-RESERVE
MEMADDA15
1
1
4 DDR_CLK4#
4 DDR_CLK5#
4 DDR_CLK6#
4 DDR_CLK7#
TP522
TP519
TP518
2 0402
2 0402
2
1
R261
100
0402
1%
C266
0.047U
0603
16V
10%
C258
0.1U
0402
10%
16V
CPU_RESET#
CPU_PWROK_2.5V
CPU_RESET# 3
CPU_PWROK_2.5V 20
2
GND
+2.5V
R849
470/NA
0603
1%
R850
470/NA
0603
1%
2
R848
470/NA
0603
1%
1
1
R852
470/NA
0603
1%
R853
470/NA
0603
1%
2
C138
1000P
0402
10%
50V
R851
470/NA
0603
1%
DBREQ#
DBRDY
TCK
TMS
TDI
TRST#
TDO
1
1
1
1
1
1
1
1
2
C151
0.1U
0402
10%
16V
TP513
TP4
TP516
TP512
TP536
TP537
TP506
+2.5VS_DDR
1
1
C139
0.33U
0402
+80-20%
16V
2
C152
0.01U
0402
10%
50V
2
GND
1
R181
100
0402
1%
TP526
Remove resistors
2
1
+1.25VSREF_CLAW
2
2 1000P
50V 10%
2
C82 1
0402
C159
0.1U
0402
10%
16V
C150
0.01U
0402
10%
50V
1
2 1000P
50V 10%
2
C40 1
0402
1
resistor must
no more than
1000mil from
processor and
5mils trace and
10mil spacing
R184
100
0402
1%
+1.25VSREF_CLAW
4 DDR_WEA#
4 DDR_WEB#
D8
C8
E8
E7
D6
E6
C4
E5
DDR_RASA#
H5
DDR_RASB#
H4
1 MEMRESET_LAG10
AG12
DDR_WEA#
G5
DDR_WEB#
F4
MEMZN
D14
MEMZP
C14
1
1
TP525
TP520
GND
+2.5VS_DDR
2
44.2
CPU_CS3#
CPU_CS2#
CPU_CS1#
CPU_CS0#
CPU_THERMTRIP# 20
CPU_THERMDC 5
CPU_THERMDA 5
C250
1000P
0402
10%
50V
1
1
TP530
TP529
4 DDR_RASA#
4 DDR_RASB#
R1471
0
R1601
0
TRST#
TMS
CPU_THERMTRIP#
CPU_THERMDC
CPU_THERMDA
TDO
TDI
TCK
AE8
AE7
P3
R5
K5
V3
AF10
AF8
E12
D10
DDR_CLK0#
P4
DDR_CLK1#
P5
1 DDR_CLK2#
K4
1 DDR_CLK3#
V4
DDR_CLK4# AE10
DDR_CLK5# AG8
DDR_CLK6#
E11
DDR_CLK7#
C10
4 CPU_CS3#
4 CPU_CS2#
4 CPU_CS1#
4 CPU_CS0#
E14-RESERVE
MEMADDB15
HDT USE
2
1
TP528
TP538
4 DDR_CLK0#
4 DDR_CLK1#
1
L0_REF1
L0_REF0
CPU_CKEA
CPU_CKEB
DDR_CLK0
DDR_CLK1
1 DDR_CLK2
1 DDR_CLK3
DDR_CLK4
DDR_CLK5
DDR_CLK6
DDR_CLK7
CPU_CKEA
CPU_CKEB
DDR_CLK0
DDR_CLK1
4 DDR_CLK4
4 DDR_CLK5
4 DDR_CLK6
4 DDR_CLK7
TP521
TP517
SCANCLK2
GND
A
U2
U1
P1
N2
V1
U3
N1
N3
1
1
TP5
TP531
BP2
1
BPSCLKBP0
BPSCLK+
+1.2VLDTB
1%
2 R30
0603
1%
2 R100
0603
D4
F5
TP533
GND
44.2
4 DDR_CASA#
4 DDR_CASB#
4
4
4
4
+2.5VS_DDR
NC_AF21
NC_AF22
NC_AF23
1
DDR_BAA0
DDR_BAA1
DDR_BAB0
DDR_BAB1
H3
K3
J5
L5
MEMADDB[0]
MEMADDB[1]
MEMADDB[2]
MEMADDB[3]
MEMADDB[4]
MEMADDB[5]
MEMADDB[6]
MEMADDB[7]
MEMADDB[8]
MEMADDB[9]
MEMADDB[10]
MEMADDB[11]
MEMADDB[12]
MEMADDB[13]
MEMBANKA[0]
MEMBANKA[1]
MEMBANKB[0]
MEMBANKB[1]
MEMCASA_L
MEMCASB_L
MEMCHECK[0]
MEMCHECK[1]
MEMCHECK[2]
MEMCHECK[3]
MEMCHECK[4]
MEMCHECK[5]
MEMCHECK[6]
MEMCHECK[7]
MEMCKEA
MEMCKEB
MEMCLK_H[0]
MEMCLK_H[1]
MEMCLK_H[2]
MEMCLK_H[3]
MEMCLK_H[4]
MEMCLK_H[5]
MEMCLK_H[6]
MEMCLK_H[7]
MEMCLK_L[0]
MEMCLK_L[1]
MEMCLK_L[2]
MEMCLK_L[3]
MEMCLK_L[4]
MEMCLK_L[5]
MEMCLK_L[6]
MEMCLK_L[7]
MEMRASA_L
MEMRASB_L
MEMRESET_L
MEMVEF1
MEMWEA_L
MEMWEB_L
MEMZN
MEMZP
R209
R208
R207
R210
R183
R186
DDR_CLK0
DDR_CLK1
DDR_CLK4
DDR_CLK5
DDR_CLK6
DDR_CLK7
1
1
1
1
1
1
120
120
120
120
120
120
5%
5%
5%
5%
5%
5%
2
2
2
2
2
2
0402
0402
0402
0402
0402
0402
DDR_CLK0#
DDR_CLK1#
DDR_CLK4#
DDR_CLK5#
DDR_CLK6#
DDR_CLK7#
+2.5VS_DDR
BPSCLK+
R118 1 820 1% 2 0402
BPSCLK-
R114 1 820 1% 2 0402
GND
C103 1
CPUCK+
R132
169
0603
1%
CPUCK-
2 3900P
0603
CPUCLK+ 5
C
須用NPO
C107 1
2 3900P
0603
CPUCLK- 5
width:20/5/5/5/20
R335不能離開CPU超過 0.5inch
CPU_DQS[0..7]
CPU_DQM0
CPU_DQM1
CPU_DQM2
CPU_DQM3
CPU_DQM4
CPU_DQM5
CPU_DQM6
CPU_DQM7
CPU_DQS[0..7]
4
CPU_DQM[0..7]
4
B
+1.2VLDTA
CLAWHAMMER
BGA754_SKT
L0_CTLIN_H1 R101 1 49.9 1% 2 0402
L0_CTLIN_L1
R107 1 49.9 1% 2 0402
+2.5V
SINCHN
BRN#
R152 1 680 5% 2 0402
R139 1 680 5% 2 0402
GND
+2.5V
CPU_THERMTRIP#
R135 1 680
2 0402
LDTSTOP1#
R97
1 680
2 0402
CPU_RESET#
R148 1 680
2 0402
CPU_PWROK_2.5V R161 1 680
2 0402
NC_AE23
NC_AF21
NC_AF22
NC_AF23
2
2
2
2
+1.25VSREF_CLAW
+2.5VS_DDR
R854
470/NA
0603
1%
12
11
10
9
8
7
6
5
4
3
2
1
12
11
10
9
8
7
6
5
4
3
2
1
R104
R125
R126
R103
C140 1
0805
C137 1
0402
1
1
1
1
680/NA
680/NA
680/NA
680/NA
Place these
capacitors close to
processor pins
GND
A
J503
GND
HDT USE
CONN_ELCO6239_12
291000151201
FPC/FFC-12P/0.5MM/NA
6239-012-001-800
BP1
BP0
SCANEN
SCANSHENA
SCANSHENB
SCANCLK1
SCANCLK2
R153
R155
R167
R150
R159
R138
R131
1
1
1
1
1
1
1
680
680
680
680
680
680
680
5%
5%
5%
5%
5%
5%
5%
2
2
2
2
2
2
2
0402
0402
0402
0402
0402
0402
0402
Title
<Title>
Size
C
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2 0.22U
GND
GND
4
2 4.7U
0402
0402
0402
0402
GND
5
D
CPU_DQS0
CPU_DQS1
CPU_DQS2
CPU_DQS3
CPU_DQS4
CPU_DQS5
CPU_DQS6
CPU_DQS7
AJ13
AJ8
AJ2
AB1
J1
D1
A8
A14
T1
AH13
AH7
AG1
AA1
H1
C2
A7
A13
R1
MEMDQS[0]
MEMDQS[1]
MEMDQS[2]
MEMDQS[3]
MEMDQS[4]
MEMDQS[5]
MEMDQS[6]
MEMDQS[7]
MEMDQS[8]
MEMDQS[9]
MEMDQS[10]
MEMDQS[11]
MEMDQS[12]
MEMDQS[13]
MEMDQS[14]
MEMDQS[15]
MEMDQS[16]
MEMDQS[17]
MEMCS_L[7]
MEMCS_L[6]
MEMCS_L[5]
MEMCS_L[4]
MEMCS_L[3]
MEMCS_L[2]
MEMCS_L[1]
MEMCS_L[0]
CPU_MD0
CPU_MD1
CPU_MD2
CPU_MD3
CPU_MD4
CPU_MD5
CPU_MD6
CPU_MD7
CPU_MD8
CPU_MD9
CPU_MD10
CPU_MD11
CPU_MD12
CPU_MD13
CPU_MD14
CPU_MD15
CPU_MD16
CPU_MD17
CPU_MD18
CPU_MD19
CPU_MD20
CPU_MD21
CPU_MD22
CPU_MD23
CPU_MD24
CPU_MD25
CPU_MD26
CPU_MD27
CPU_MD28
CPU_MD29
CPU_MD30
CPU_MD31
CPU_MD32
CPU_MD33
CPU_MD34
CPU_MD35
CPU_MD36
CPU_MD37
CPU_MD38
CPU_MD39
CPU_MD40
CPU_MD41
CPU_MD42
CPU_MD43
CPU_MD44
CPU_MD45
CPU_MD46
CPU_MD47
CPU_MD48
CPU_MD49
CPU_MD50
CPU_MD51
CPU_MD52
CPU_MD53
CPU_MD54
CPU_MD55
CPU_MD56
CPU_MD57
CPU_MD58
CPU_MD59
CPU_MD60
CPU_MD61
CPU_MD62
CPU_MD63
+1.25VSREF_MEM
1
C237
0.1U
0402
10%
16V
M3
T4
U5
W5
Y4
AB3
AA5
AD4
AC5
AD5
M4
AF4
AF6
E9
NC_AE23
2
2
1%
2 R180
0603
1%
2 R174
0603
2
34.8
MEMZP 1
R235
100
0402
1%
1
+2.5VS_DDR
34.8
0/NA 2 0402
0
2 0402
MEMADD_B0
MEMADD_B1
MEMADD_B2
MEMADD_B3
MEMADD_B4
MEMADD_B5
MEMADD_B6
MEMADD_B7
MEMADD_B8
MEMADD_B9
MEMADD_B10
MEMADD_B11
MEMADD_B12
MEMADD_B13
MEMADD_B[0..13]
4 MEMADD_B[0..13]
AJ16
AJ14
AJ12
AG11
AJ15
AH15
AJ11
AH11
AJ10
AJ9
AH5
AG5
AH9
AJ7
AJ6
AJ5
AJ3
AH3
AF1
AE2
AJ4
AG3
AE3
AE1
AD1
AC2
Y1
W2
AC3
AC1
W3
W1
M1
L2
J2
G3
L1
L3
G1
G2
F1
E3
B3
A3
E1
E2
A4
C5
B5
A5
A9
C11
A6
C7
B9
A10
A11
C13
A15
A17
B11
A12
B15
A16
MEMDATA[0]
MEMDATA[1]
MEMDATA[2]
MEMDATA[3]
MEMDATA[4]
MEMDATA[5]
MEMDATA[6]
MEMDATA[7]
MEMDATA[8]
MEMDATA[9]
MEMDATA[10]
MEMDATA[11]
MEMDATA[12]
MEMDATA[13]
MEMDATA[14]
MEMDATA[15]
MEMDATA[16]
MEMDATA[17]
MEMDATA[18]
MEMDATA[19]
MEMDATA[20]
MEMDATA[21]
MEMDATA[22]
MEMDATA[23]
MEMDATA[24]
MEMDATA[25]
MEMDATA[26]
MEMDATA[27]
MEMDATA[28]
MEMDATA[29]
MEMDATA[30]
MEMDATA[31]
MEMDATA[32]
MEMDATA[33]
MEMDATA[34]
MEMDATA[35]
MEMDATA[36]
MEMDATA[37]
MEMDATA[38]
MEMDATA[39]
MEMDATA[40]
MEMDATA[41]
MEMDATA[42]
MEMDATA[43]
MEMDATA[44]
MEMDATA[45]
MEMDATA[46]
MEMDATA[47]
MEMDATA[48]
MEMDATA[49]
MEMDATA[50]
MEMDATA[51]
MEMDATA[52]
MEMDATA[53]
MEMDATA[54]
MEMDATA[55]
MEMDATA[56]
MEMDATA[57]
MEMDATA[58]
MEMDATA[59]
MEMDATA[60]
MEMDATA[61]
MEMDATA[62]
MEMDATA[63]
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
CLAWHAMMER
BGA754_SKT
291000617542
BGA754_SKT
MEMZN 1
TP510
1
L0_CADOUT_H[0..15]
6 L0_CADOUT_H[0..15]
L0_CADIN_L[0]
L0_CADIN_L[1]
L0_CADIN_L[2]
L0_CADIN_L[3]
L0_CADIN_L[4]
L0_CADIN_L[5]
L0_CADIN_L[6]
L0_CADIN_L[7]
L0_CADIN_L[8]
L0_CADIN_L[9]
L0_CADIN_L[10]
L0_CADIN_L[11]
L0_CADIN_L[12]
L0_CADIN_L[13]
L0_CADIN_L[14]
L0_CADIN_L[15]
L0_REF0
L0_REF1
LDTSTOP1# R96 1
R4161
BRN#
A19
A25
AA2
AA3
AE21
AE22
AE23
AE24
AE9
AF18
AF21
AF22
AF23
AF24
AG17
AG18
AG2
AG4
AG6
AG7
AG9
AH1
AH18
AH23
AJ18
AJ23
B13
B18
B19
B7
C1
C12
C15
C18
C19
C20
C21
C22
C23
C24
C3
C6
C9
D12
D18
D20
D22
D3
E13
E14
F3
J3
K1
R2
R3
TP509
L0_CTLOUT_L0 6
1
1
L0_CADOUT_H15
L0_CADOUT_H14
L0_CADOUT_H13
L0_CADOUT_H12
L0_CADOUT_H11
L0_CADOUT_H10
L0_CADOUT_H9
L0_CADOUT_H8
L0_CADOUT_H7
L0_CADOUT_H6
L0_CADOUT_H5
L0_CADOUT_H4
L0_CADOUT_H3
L0_CADOUT_H2
L0_CADOUT_H1
L0_CADOUT_H0
C
NC_A19
NC_A25
NC_AA2
NC_AA3
NC_AE21
NC_AE22
NC_AE23
NC_AE24
NC_AE9
NC_AF18
NC_AF21
NC_AF22
NC_AF23
NC_AF24
NC_AG17
NC_AG18
NC_AG2
NC_AG4
NC_AG6
NC_AG7
NC_AG9
NC_AH1
NC_AH18
NC_AH23
NC_AJ18
NC_AJ23
NC_B13
NC_B18
NC_B19
NC_B7
NC_C1
NC_C12
NC_C15
NC_C18
NC_C19
NC_C20
NC_C21
NC_C22
NC_C23
NC_C24
NC_C3
NC_C6
NC_C9
NC_D12
NC_D18
NC_D20
NC_D22
NC_D3
NC_E13
NC_E14
NC_F3
NC_J3
NC_K1
NC_R2
NC_R3
AE26
AF27
AJ27
L0_CTLOUT_H0 6
1
2
AD28
AC29
AB28
AA29
W29
V28
U29
T28
AC25
AC26
AA25
AA26
W26
U25
U26
R25
L0_REF0
L0_REF1
LDTSTOP_L
L0_CTLIN_L0 6
2
L0_CADIN_L0
L0_CADIN_L1
L0_CADIN_L2
L0_CADIN_L3
L0_CADIN_L4
L0_CADIN_L5
L0_CADIN_L6
L0_CADIN_L7
L0_CADIN_L8
L0_CADIN_L9
L0_CADIN_L10
L0_CADIN_L11
L0_CADIN_L12
L0_CADIN_L13
L0_CADIN_L14
L0_CADIN_L15
L0_CADIN_L[0..15]
6 L0_CADIN_L[0..15]
L0_CADIN_H[0]
L0_CADIN_H[1]
L0_CADIN_H[2]
L0_CADIN_H[3]
L0_CADIN_H[4]
L0_CADIN_H[5]
L0_CADIN_H[6]
L0_CADIN_H[7]
L0_CADIN_H[8]
L0_CADIN_H[9]
L0_CADIN_H[10]
L0_CADIN_H[11]
L0_CADIN_H[12]
L0_CADIN_H[13]
L0_CADIN_H[14]
L0_CADIN_H[15]
1
AD27
AD29
AB27
AB29
Y29
V27
V29
T27
AD25
AC27
AB25
AA27
W27
V25
U27
T25
L0_CLKIN_H0 6
L0_CLKIN_H1 6
L0_CLKIN_L0 6
L0_CLKIN_L1 6
L0_CLKOUT_H0 6
L0_CLKOUT_H1 6
L0_CLKOUT_L0 6
L0_CLKOUT_L1 6
L0_CTLIN_H0 6
1
L0_CADIN_H0
L0_CADIN_H1
L0_CADIN_H2
L0_CADIN_H3
L0_CADIN_H4
L0_CADIN_H5
L0_CADIN_H6
L0_CADIN_H7
L0_CADIN_H8
L0_CADIN_H9
L0_CADIN_H10
L0_CADIN_H11
L0_CADIN_H12
L0_CADIN_H13
L0_CADIN_H14
L0_CADIN_H15
L0_CLKIN_H0
L0_CLKIN_H1
L0_CLKIN_L0
L0_CLKIN_L1
L0_CLKOUT_H0
L0_CLKOUT_H1
L0_CLKOUT_L0
L0_CLKOUT_L1
L0_CTLIN_H0
L0_CTLIN_H1
L0_CTLIN_L0
L0_CTLIN_L1
L0_CTLOUT_H0
L0_CTLOUT_H1
L0_CTLOUT_L0
L0_CTLOUT_L1
MEMADDA[0]
MEMADDA[1]
MEMADDA[2]
MEMADDA[3]
MEMADDA[4]
MEMADDA[5]
MEMADDA[6]
MEMADDA[7]
MEMADDA[8]
MEMADDA[9]
MEMADDA[10]
MEMADDA[11]
MEMADDA[12]
MEMADDA[13]
1
L0_CADIN_H[0..15]
6 L0_CADIN_H[0..15]
Y27
Y25
Y28
W25
J29
J26
K29
J27
T29
R27
R29
R26
P28
N25
P27
P25
N5
T3
T5
V5
Y3
AB4
Y5
AD3
AB5
AE5
M5
AF3
AE6
E10
2
L0_CLKIN_H[0]
L0_CLKIN_H[1]
L0_CLKIN_L[0]
L0_CLKIN_L[1]
L0_CLKOUT_H[0]
L0_CLKOUT_H[1]
L0_CLKOUT_L[0]
L0_CLKOUT_L[1]
L0_CTLIN_H[0]
L0_CTLIN_H[1]
L0_CTLIN_L[0]
L0_CTLIN_L[1]
L0_CTLOUT_H[0]
L0_CTLOUT_H[1]
L0_CTLOUT_L[0]
L0_CTLOUT_L[1]
2
width:20/8/5/8/20
CLKIN_H
CLKIN_L
CORE_SENSE
COREFB_H
COREFB_L
DBRDY
DBREQ_L
FBCLKOUT_H
FBCLKOUT_L
KEY0
KEY1
4
U6B
MEMADD_A0
MEMADD_A1
MEMADD_A2
MEMADD_A3
MEMADD_A4
MEMADD_A5
MEMADD_A6
MEMADD_A7
MEMADD_A8
MEMADD_A9
MEMADD_A10
MEMADD_A11
MEMADD_A12
MEMADD_A13
1
R151 2
0603
AJ21
AH21
B23
A23
A24
AH17
AE19
AH19
AJ19
AJ28
A28
2
REFB_H
REFB_L
DBRDY
DBREQ#
1 80.6
1%
1
D
1
2
CPUCK+
CPUCKTP511
25 COREFB_H
25 COREFB_L
CPU_MD[0..63]
MEMADD_A[0..13]
4 MEMADD_A[0..13]
U6A
2
Date:
Document
Number
Rev
R03
<Doc>
星期四, 五月 20, 2004
1
Sheet
2
of
26
5
4
3
2
1
ClawHammer-Power plane(2/2)
+VCC_CORE
U6D
GND
Near NB within
1 inch*4
AE12
AF12
1
1
AE11
R187
TP524
TP523
1 0
+1.2VLDTA
+1.2VLDTB
2 0402
Place HT
bypass caps
on topside
near
unconnected
Clawhammer
HT link
C41
4.7U
1206
10%
GND
GND
VTT_A0
VTT_A1
VTT_A2
VTT_A3
VTT_A4
VTT_B0
VTT_B1
VTT_B2
VTT_B3
VTT_B4
VTT_SENSE
+3V
1
1
1
D
+3V
R386
47K
0402
5%
+2.5VDDA
U7
1
5
R133
8.87K
0603
1%
1
2 0402 2
1
C100
10U
0805
10V
+80-20%
C
2
R388
8.2K
0603
GND
+3V
R411
8.2K
0402
5%
R1
C160
0.1U/NA
0402
+80-20%
50V
GND
GND
GND
1
+3VS
+1.25VTT
R171 1 0
C114
100P
0402
+/-10%
50V
2
ADJ
AME8804AEEY
SOT26
2
2
C375
1U
0603
6
VOUT
2
1
20 +2.5VDDA_PG
EN
VIN
PG
1
3
1
4
GND
PG_+1.25VS_P
R412
10K
0402
5%
Q8
DTC144TKA
PG_+1.25VS_P
D
S
G
Q7
2N7002
B
GND
GND
+2.5V
GND
7,9,20 ALL_PWROK_2.5V
A18
B17
C16
C17
D17
AF16
AG15
AG16
AH16
AJ17
AE13
1
GND
D2
1 0.22U
060310%,X7R
1 0.22U
060310%,X7R
1 0.22U
060310%,X7R
1 0.22U
060310%,X7R
1
S
C97 2
16V
C31 2
16V
C15 2
16V
C16 2
16V
GND
1
1
+1.2VLDTA
1
2
Near CPU within
in VLDT pour*4
1
2 0.22U
0603
2 0.22U
0603
2 0.22U
0603
2 0.22U
0603
2 10U
0805
2 10U
0805
1
GND
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
1 0.22U
060310%,X7R
1 0.22U
060310%,X7R
1 0.22U
060310%,X7R
1 0.22U
060310%,X7R
1
C402
16V
C403
16V
C404
16V
C405
16V
C672
6.3V
C673
6.3V
2
C90 2
16V
C91 2
16V
C108 2
16V
C95 2
16V
1
Place these capacitors near socket
1
+1.2VLDTA
2 0.22U
0603
2 0.22U
0603
2 10U
0805
2 10U
0805
2 10U
0805
2 10U
0805
1
3
+2.5VS_DDR
+VCC_CORE
C117
16V
C116
16V
C125
6.3V
C126
6.3V
C127
6.3V
C115
6.3V
1
2
1
1
2
C83
0.22U
0603
10%,X7R
16V
GND
D5
D7
D9
D11
D13
D15
E4
F6
F8
F10
F12
F14
F16
G4
G7
G9
H6
H8
J4
J7
K6
L4
M6
N4
P6
R4
T6
U4
V6
W4
Y6
AA4
AA7
AB6
AB8
AC4
AC7
AC9
AD6
AD8
AD10
AD12
AD14
AD16
AE4
AF11
AF13
AF5
AF7
AF9
B27
B29
C26
C28
D25
D27
D29
AF25
AE28
AF29
AG26
AG28
AH27
AH29
2
1
1
2
AH25
AJ25
2
CLAWHAMMER
BGA754_SKT
VLDT0_A0
VLDT0_A1
VLDT0_A2
VLDT0_A3
VLDT0_A4
VLDT0_A5
VLDT0_A6
VLDT0_B0
VLDT0_B1
VLDT0_B2
VLDT0_B3
VLDT0_B4
VLDT0_B5
VLDT0_B6
C80
3300P
0402
10%
50V
+VCC_CORE
+1.25VTT
R175
1 0
14
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VDDIO_SENSE
C96
4.7U
0805
+80-20%
U6
U8
U10
U20
U22
U24
V2
V7
V9
V21
V23
W6
W8
W10
W20
W22
W24
W28
Y2
Y7
Y9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y26
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA24
AB2
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AC6
AC8
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC24
AC28
AD2
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD21
AD23
AD26
AE14
AE16
AE20
AE29
AF2
AF17
AF19
AF26
AF28
AG20
AG21
AG22
AG23
AG24
AG25
AG27
AG29
AH2
AH4
AH6
AH8
AH10
AH12
AH14
AH20
AH22
AH26
AH28
AJ20
AJ22
AJ24
AJ26
U22A
+2.5V
3
6 NB_LDTRST#
R383 1 0/NA
2 0402
8 CPU_PCIRST#
R417 1 0
2 0402
R370 1 0
2 0402
CPU_RESET# 2
2
R369
10K
0402
5%
2 0402
CLAWHAMMER
BGA754_SKT
1
7
VID0
VID1
VID2
VID3
VID4
VDDIOFB_H
VDDIOFB_L
L34
120Z/100M
2012
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
1
25
25
25
25
25
AE15
AF15
AG14
AF14
AG13
VDDIO_0
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10
VDDIO_11
VDDIO_12
VDDIO_13
VDDIO_14
VDDIO_15
VDDIO_16
VDDIO_17
VDDIO_18
VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
VDDIO_30
VDDIO_31
VDDIO_32
VDDIO_33
VDDIO_34
VDDIO_35
VDDIO_36
VDDIO_37
VDDIO_38
VDDIO_39
VDDIO_40
VDDIO_41
VDDIO_42
VDDIO_43
VDDIO_44
VDDIO_45
VDDIO_46
VDDIO_47
VDDIO_48
VDDIO_49
+2.5VDDA
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
74HCT08_V
TSSOP14
2
B
VDDA1
VDDA2
AA13
AA15
AA17
AA19
AA21
AA23
AA28
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AB26
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD18
AD20
AD22
AD24
AE17
AE25
AE27
AG19
AH24
2
C
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110
VDD_111
VDD_112
VDD_113
VDD_114
VDD_115
VDD_116
VDD_117
VDD_118
VDD_119
VDD_120
VDD_121
VDD_122
VDD_123
VDD_124
VDD_125
VDD_126
VDD_127
VDD_128
VDD_129
VDD_130
VDD_131
VDD_132
1
D
VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98
VDD_99
VDD_100
1
B2
B4
B6
B8
B10
B12
B14
B16
B22
B25
B26
B28
C25
C27
C29
D2
D16
D19
D21
D23
D26
D28
E15
E16
E18
E22
E24
F2
F7
F9
F11
F13
F15
F17
F19
F21
F23
G6
G8
G10
G12
G14
G16
G18
G20
G22
G24
G28
H2
H7
H9
H11
H13
H15
H17
H19
H21
H23
H26
J6
J8
J10
J12
J14
J16
J18
J20
J22
J24
K2
K7
K9
K11
K13
K15
K17
K19
K21
K23
L6
L8
L10
L20
L22
L24
L28
M2
M7
M9
M21
M23
M26
N6
N8
N10
N20
N22
N24
P2
P7
P9
P21
P23
R6
R8
R10
R20
R22
R24
R28
T2
T7
T9
T21
T23
T26
U6C
B20
B24
D24
E19
E21
E23
E28
F18
F20
F22
F24
F26
G11
G13
G15
G17
G19
G21
G23
H10
H12
H14
H16
H18
H20
H22
H24
J9
J11
J13
J15
J17
J19
J21
J23
J28
K8
K10
K12
K14
K16
K18
K20
K22
K24
K26
L7
L9
L21
L23
M8
M10
M20
M22
M24
N7
N9
N21
N23
N28
P8
P10
P20
P22
P24
P26
R7
R9
R21
R23
T8
T10
T20
T22
T24
U7
U9
U21
U23
U28
V8
V10
V20
V22
V24
V26
W7
W9
W21
W23
Y8
Y10
Y12
Y14
Y16
Y18
Y20
Y22
Y24
AA9
AA11
2
+VCC_CORE
GND
A
A
Title
<Title>
Size
C
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R03
<Doc>
星期四, 五月 20, 2004
1
Sheet
3
of
26
5
4
3
2
1
DIMM-SLOT & Termination
+1.25VSREF_MEM
+2.5VS_DDR
+2.5VS_DDR
X7R
+1.25VSREF_MEM
+1.25VTT
J16
MD3
MD8
D
MD9
DQS1
MD10
MD11
DDR_CLK5
DDR_CLK5#
C
B
DIMM0
MD16 41
MD17 43
45
DQS2 47
MD18 49
51
MD19 53
MD24 55
57
MD25 59
DQS3 61
63
MD26 65
MD27 67
69
71
73
75
77
79
81
83
85
87
DDR_CLK0
89
DDR_CLK0#
91
93
DDR_CKEA
95
97
MEMADD_A12 99
MEMADD_A9 101
103
MEMADD_A7 105
MEMADD_A5 107
MEMADD_A3 109
MEMADD_A1 111
113
MEMADD_A10 115
DDR_BAA0
117
DDR_WEA#
119
DDR_CS0#
121
MEMADD_A13 123
125
MD32 127
MD33 129
131
DQS4 133
MD34 135
137
MD35 139
MD40 141
143
MD41 145
DQS5 147
149
MD42 151
MD43 153
155
157
159
161
MD48 163
MD49 165
167
DQS6 169
MD50 171
173
MD51 175
MD56 177
179
MD57 181
DQS7 183
185
MD58 187
MD59 189
191
SMBDATA_DDR 193
SMBCLK_DDR
195
197
199
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
MD4
MD5
MD0
MD1
DQM0
MD6
DQS0
MD2
MD7
MD12
MD3
MD8
MD13
DQM1
MD9
DQS1
MD14
MD15
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
MD10
MD11
DDR_CLK4
DDR_CLK4#
MD20
MD21
DIMM1
MD16
MD17
41
43
45
DQS2
47
MD18
49
51
MD19
53
MD24
55
57
MD25
59
DQS3
61
63
MD26
65
MD27
67
69
71
73
75
77
79
81
83
85
87
DDR_CLK1
89
DDR_CLK1#
91
93
DDR_CKEB
95
97
MEMADD_B12 99
MEMADD_B9 101
103
MEMADD_B7 105
MEMADD_B5 107
MEMADD_B3 109
MEMADD_B1 111
113
MEMADD_B10 115
DDR_BAB0
117
DDR_WEB#
119
DDR_CS2#
121
MEMADD_B13 123
125
MD32
127
MD33
129
131
DQS4 133
MD34
135
137
MD35
139
MD40
141
143
MD41
145
DQS5 147
149
MD42
151
MD43
153
155
157
159
161
MD48
163
MD49
165
167
DQS6 169
MD50
171
173
MD51
175
MD56
177
179
MD57
181
DQS7 183
185
MD58
187
MD59
189
191
SMBDATA_DDR193
SMBCLK_DDR 195
197
199
DQM2
MD22
MD23
MD28
MD29
DQM3
MD30
MD31
DDR_CKEA
MEMADD_A11
MEMADD_A8
MEMADD_A6
MEMADD_A4
MEMADD_A2
MEMADD_A0
DDR_BAA1
DDR_RASA#
DDR_CASA#
DDR_CS1#
MD36
MD37
DQM4
MD38
MD39
MD44
MD45
DQM5
MD46
MD47
DDR_CLK7#
DDR_CLK7
MD52
MD53
DQM6
MD54
MD55
MD60
MD61
DQM7
MD62
MD63
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
CPU_MD[0..63]
DQM0
MD6
2 CPU_DQS7
2 CPU_DQM7
MD7
MD12
MD13
DQM1
MD14
MD15
2 CPU_DQS6
2 CPU_DQM6
MD20
MD21
DQM2
MD22
2 CPU_DQM5
MD23
MD28
2 CPU_DQS5
MD29
DQM3
MD30
MD31
2 CPU_DQM4
2 CPU_DQS4
DDR_CKEB
2 CPU_DQM3
2 CPU_DQS3
MEMADD_B11
MEMADD_B8
MEMADD_B6
MEMADD_B4
MEMADD_B2
MEMADD_B0
DDR_BAB1
DDR_RASB#
DDR_CASB#
DDR_CS3#
2 CPU_DQM2
2 CPU_DQS2
MD36
MD37
DQM4
MD38
2 CPU_DQM1
MD39
MD44
2 CPU_DQS1
MD45
DQM5
MD46
MD47
DDR_CLK6#
DDR_CLK6
2 CPU_DQM0
2 CPU_DQS0
MD52
MD53
RP19
10*8
RPX8
8
7
6
5
16
15
14
13
12
11
10
9
CPU_MD47
CPU_MD43
CPU_MD46
CPU_DQM5
CPU_MD42
CPU_DQS5
CPU_MD45
CPU_MD44
CPU_MD41
CPU_MD40
CPU_MD39
CPU_MD38
CPU_MD35
CPU_DQM4
CPU_MD34
CPU_DQS4
CPU_MD37
CPU_MD36
CPU_MD33
CPU_MD32
16
15
14
13
12
11
10
9
8
7
6
5
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1
2
3
4
1
2
3
4
5
6
7
8
RP22
10*8
RPX8
CPU_MD27
CPU_MD31
CPU_MD30
CPU_MD26
CPU_DQM3
CPU_DQS3
CPU_MD29
CPU_MD25
CPU_MD28
CPU_MD24
CPU_MD23
CPU_MD19
CPU_MD18
CPU_MD22
CPU_DQM2
CPU_MD21
CPU_DQS2
CPU_MD17
CPU_MD16
CPU_MD20
16
15
14
13
12
11
10
9
8
7
6
5
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1
2
3
4
1
2
3
4
5
6
7
8
RP25
10*8
RPX8
CPU_MD11
CPU_MD15
CPU_MD10
CPU_MD14
CPU_DQM1
CPU_MD13
CPU_DQS1
CPU_MD12
CPU_MD9
CPU_MD8
CPU_MD3
CPU_MD7
CPU_MD6
CPU_MD2
CPU_DQM0
CPU_DQS0
CPU_MD1
CPU_MD5
CPU_MD4
CPU_MD0
16
15
14
13
12
11
10
9
8
7
6
5
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1
2
3
4
1
2
3
4
5
6
7
8
RP28
10*8
RPX8
MD55
MD60
2 DDR_CLK5
2 DDR_CLK5#
A
2 DDR_CLK7
2 DDR_CLK7#
2 DDR_CLK1
2 DDR_CLK1#
2 DDR_CLK4
2 DDR_CLK4#
2 DDR_CLK6
2 DDR_CLK6#
5,9 SMB_DATA0
5,9 SMB_CLK0
Locate close to CPU socket
DDR_CLK5
DDR_CLK5#
+1.25VTT
R256
8.2K
0603
MD62
MD63
DDR_CKEB
2 CPU_CKEB
DDR_CS0#
2 CPU_CS0#
DDR_CS1#
2 CPU_CS1#
DDR_CS2#
2 CPU_CS2#
X7R
C122
1
0805
DDR_CLK4
DDR_CLK4#
2 4.7U
BOT
DDR_CLK6
DDR_CLK6#
GND
SMBDATA_DDR
SMBCLK_DDR
Place on 10uF capacitor on
each end of the VTT island
RP24
10*8
RPX8
1
2
3
4
5
6
7
8
5
6
7
8
1
2
3
4
5
6
7
8
RP37
68*8
RPX8
MD47
MD43
MD46
DQM5
MD42
DQS5
MD45
MD44
MD41
MD40
MD39
MD38
MD35
DQM4
MD34
DQS4
MD37
MD36
MD33
MD32
MD47
MD43
MD46
DQM5
MD42
DQS5
MD45
MD44
MD41
MD40
MD39
MD38
DQM4
MD35
MD34
DQS4
MD37
MD36
MD33
MD32
16
15
14
13
12
11
10
9
4
3
2
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
5
6
7
8
1
2
3
4
5
6
7
8
RP40
68*8
RPX8
MD27
MD31
MD30
MD26
DQM3
DQS3
MD29
MD25
MD28
MD24
MD23
MD19
MD18
MD22
DQM2
MD21
DQS2
MD17
MD16
MD20
MD31
MD27
MD30
MD26
DQM3
DQS3
MD29
MD25
MD28
MD24
MD23
MD19
MD18
MD22
DQM2
MD21
DQS2
MD17
MD16
MD20
16
15
14
13
12
11
10
9
4
3
2
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
5
6
7
8
1
2
3
4
5
6
7
8
RP31
68*8
RPX8
C123
0402
C206
0402
C129
0402
C261
0402
C132
6.3V
C128
6.3V
1
1
1
1
1
1
2 1000P
+/-20%
2 100P
+/-10%
2 100P
+/-10%
2 100P
+/-10%
2 10U
0805
2 10U
0805
RP26
10*4
1206
RP27
10*8
RPX8
MD11
MD15
MD10
MD14
DQM1
MD13
DQS1
MD12
MD9
MD8
MD3
MD7
MD6
MD2
DQM0
DQS0
MD1
MD5
MD4
MD0
MD11
MD10
MD15
MD14
DQM1
MD13
DQS1
MD12
MD9
MD8
MD3
MD7
MD6
MD2
DQM0
DQS0
MD1
MD5
MD4
MD0
16
15
14
13
12
11
10
9
4
3
2
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
5
6
7
8
1
2
3
4
5
6
7
8
RP34
68*8
RPX8
RP29
10*4
1206
RP30
10*8
RPX8
2
2
2
2
2
2
DDR_BAB0
DDR_RASA#
DDR_WEB#
DDR_WEA#
DDR_CASB#
DDR_CASA#
Place between the processor and
nearest SO-DIMM, and Net length
to the processor should be
500-1000mil
+1.25VTT
DDR_CLK1
DDR_CLK1#
RP23
10*4
1206
16
15
14
13
12
11
10
9
4
3
2
1
16
15
14
13
12
11
10
9
DDR_CS3#
2 CPU_CS3#
bulk-capacitors
DDR_CLK7
DDR_CLK7#
RP21
10*8
RPX8
MD59
MD63
MD62
MD58
DQS7
DQM7
MD57
MD61
MD60
MD56
MD55
MD51
MD50
MD54
DQS6
DQM6
MD53
MD52
MD49
MD48
DDR_CKEA
2 CPU_CKEA
MD61
DQM7
Sec soure 291000622007
DDR_CLK0
DDR_CLK0#
RP20
10*4
1206
MD59
MD63
MD62
MD58
DQS7
DQM7
MD57
MD61
MD60
MD56
MD55
MD51
MD50
MD54
DQS6
DQM6
MD53
MD52
MD49
MD48
RP38
68*4
1206
RP39
68*8
RPX8
MEMADD_B0
MEMADD_B1
MEMADD_B2
MEMADD_B3
MEMADD_B4
MEMADD_B5
MEMADD_B6
MEMADD_B7
MEMADD_B8
MEMADD_B9
MEMADD_B10
MEMADD_B11
MEMADD_B12
MEMADD_B13
2
2
2
2
+1.25VSREF_MEM
C272 1
0805
C247 1
0603D
2 MEMADD_A[0..13]
2 4.7U
2 0.22U
Locae close to DIMMs
GND
GND
4
1
1
1
1
1
1
1
1
1
1
1
C286
0402
C220
0402
C284
0402
C285
0402
C288
0402
C289
0402
C297
0402
C298
0402
C299
0402
C300
0402
C290
0402
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
1
1
1
1
1
1
1
1
1
1
1
D
GND
+1.25VTT
+2.5VS_DDR+1.25VTT
+2.5VS_DDR
RP41
68*4
1206
C149
0402
C274
0402
C268
0402
C279
0402
C263
0402
C238
0402
C217
0402
RP42
68*8
RPX8
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
1
1
1
1
1
1
1
C222
0402
C203
0402
C215
0402
C221
0402
C244
0402
C253
0402
C280
0402
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
1
1
1
1
1
1
1
C
Place alternating caps to GND and +2.5VDIMM in a
single line along VTT island.
RP32
68*4
1206
X7R
RP33
68*8
RPX8
Bypass capacitor
+2.5VS_DDR
+2.5VS_DDR
C273
0402
C330
0402
C196
0402
C197
0402
C166
0402
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
1
1
1
1
1
C124
0402
C165
0402
C195
0402
C194
0402
C198
0402
C168
0402
RP35
68*4
1206
RP36
68*8
RPX8
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
1
1
1
1
1
1
GND
GND
B
+1.25VTT
+1.25VTT
MEMADD_A0
MEMADD_A1
MEMADD_A2
MEMADD_A3
MEMADD_A4
MEMADD_A5
MEMADD_A6
MEMADD_A7
MEMADD_A8
MEMADD_A9
MEMADD_A10
MEMADD_A11
MEMADD_A12
MEMADD_A13
DDR_BAA1
DDR_BAB1
DDR_RASB#
DDR_BAA0
DDR_CKEA
DDR_CKEB
DDR_BAB0
DDR_RASA#
DDR_WEB#
DDR_WEA#
DDR_CASB#
DDR_CASA#
MEMADD_A13
MEMADD_B13
DDR_CS0#
DDR_CS1#
DDR_CS2#
DDR_CS3#
R2591 47
R2601 47
1
2
3
4
5
6
7
8
1
2
3
4
2
2
16
15
14
13
12
11
10
9
5
6
7
8
MEMADD_B2
MEMADD_B0
MEMADD_B10
MEMADD_A0
DDR_BAA1
DDR_BAB1
DDR_RASB#
DDR_BAA0
MEMADD_A8
MEMADD_A4
MEMADD_A6
MEMADD_A3
MEMADD_A1
MEMADD_A2
MEMADD_B1
MEMADD_A10
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1
MEMADD_A11 2
MEMADD_A12 3
4
MEMADD_A7 5
MEMADD_B11 6
MEMADD_B7 7
MEMADD_A9 8
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
MEMADD_B12
MEMADD_B9
MEMADD_B5
MEMADD_B8
MEMADD_B6
MEMADD_B4
MEMADD_B3
MEMADD_A5
0402
0402
+1.25VTT
C204
0805
C225
0402
C260
0805
C278
0402
C277
0805
C264
0402
C243
0805
C202
0805
RP17
47*8
RPX8
RP43
47*4
0804
RP14
47*8
RPX8
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
1
2 4.7U
1
2 0.22U
16V
2 4.7U
1
+2.5VS_DDR
1
1
2 0.22U
16V
2 4.7U
1
2 0.22U
16V
2 4.7U
1
2 4.7U
1
C209
0.22U
C276
0.22U
C216
0.22U
C248
0.22U
C156
0.22U
C131
0.22U
C136
0.22U
C226
0.22U
C239
0.22U
C256
0.22U
GND
1
1
1
1
1
1
1
1
1
1
2
16V
2
16V
2
16V
2
16V
2
16V
2
16V
2
16V
2
16V
2
16V
2
16V
X7R
0603
X7R
0603
X7R
0603
X7R
0603
X7R
0603
X7R
0603
X7R
0603
X7R
0603
X7R
0603
X7R
0603
Place a cap every 1
inch on VTT trace
between Clawhammer and
DDR
RP18
47*8
RPX8
A
RP15
47*8
RPX8
RP16
47*8
RPX8
Title
<Title>
Size
C
Date:
5
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
1
+2.5VS_DDR
2 MEMADD_B[0..13]
GND
C219
0402
C275
0402
C305
0402
C291
0402
C292
0402
C293
0402
C294
0402
C295
0402
C296
0402
C205
0402
C218
0402
C287
0402
+1.25VTT
9
10
11
12
13
14
15
16
1
2
3
4
1
2
3
4
5
6
7
8
OS-CON OR X7R
2 DDR_CLK0
2 DDR_CLK0#
2
8
7
6
5
4
3
2
1
DQM6
MD54
0.6MM/200P/H9.2
TYCO 1-1470800-2
GND
CPU_MD59
CPU_MD63
CPU_MD62
CPU_MD58
CPU_DQS7
CPU_DQM7
CPU_MD57
CPU_MD61
CPU_MD60
CPU_MD56
CPU_MD55
CPU_MD51
CPU_MD50
CPU_MD54
CPU_DQS6
CPU_DQM6
CPU_MD53
CPU_MD52
CPU_MD49
CPU_MD48
t
t
n
e e
r
c m
e
u
S
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C
0.6MM/200P/H5.2
TYCO
1470431-1
Sec soure 331660020005
CPU_MD[0..63]
MD4
MD5
1
DQS0
MD2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
MD0
MD1
Net lengths tothe SO-DIMM should
be 200-500mils
J17
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
4
of
26
5
4
3
2
1
CLOCK GENERATOR(ICS950405)
+3V
U14
9
16
19
35
38
C271
0.1U
0402
+80-20%
43
29
GND
0402
0402
0402
0402
0402
0402
28
FS3
FS2
FS1
31
45
48
1
FS0
2 0402
R257 1 10K
5
10
15
20
27
30
33
34
39
42
47
2 0402
+3V
GND
FS3
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
SDATA
SCLK
PD#*
*MODEA/HTTCLK0
~*MODEB/PCICLK7/HTTCLK1
~*PCICLK_F
RESET#
X1
GND
MODE FUNCTIONALITY TABLES
0
Pin6
Pin7
Pin8
Pin11
0
66MHZ 66MHZ 66MHZ 33MHZ
0
1
MODE A
INPUT
ONLY 66MHZ 66MHZ 66MHZ
1
0
33MHZ 33MHZ 33MHZ 33MHZ
1
MODE A
INPUT
ONLY 33MHZ 33MHZ 33MHZ
MODE C
Pin23
0
2 0402
RTL_PD#
R242 1 0/NA
2 0402
32
SB_VCLK 10
66M_AGP 7
D11
RLS4148
K
SUSA# 9
R810
ON:for ISC950403
OFF:for RTM360803
SMB_DATA0 4,9
SMB_CLK0 4,9
ICS_PD#
CHANGE VALUE
R241 1 0402/NA 2
R265 1 0402
2
6
7
23
44
R251
10K
0402
A
33
33
GCLK_NB
PCI_SB_CLK
PCI_SB_CLK 8
+3V
RTL_PD#
R236 1 10K
3
ICS_PD#
2 0402
4
1
R250 1 0/NA
R415
R811
ON:for RTM360803
OFF:for ISC950403
2
14.318MHZ
274011431414
GND
GND
2 0805
ON:for RTM360803
OFF:for ISC950403
C241
27P
0402
5%
C
GND
AGP Clock Signal
GCLK_NB
C255 1
0402
C249 1
0402
C252 1
0402
CHANGE VALUE
2 22P
1~8
+/-10%
2 22P
5~12
+/-10%
2 22P
5~12
+/-10%
+3V
2 CPU_THERMDA
2200P
0402
50V
+/-20%
GND
1. 6 : 24
2. Series resistors less than 1
3. GCLK_NB & SB_VCLK is 4 longer
than 66M_AGP
Pin24
AGP Clock Signal
PCICLK6
PCI_SB_CLK
1
R254 1 0
CHANGE VALUE
26
25
C246
27P
0402
5%
SB_VCLK
1
SB_VCLK
66M_AGP
R237 1 10K/NA 2 0402
66M_AGP
B
ICS_PD#
PCI_STOP#
PCI_CARD_CLK
MINI_PCI_CLK
C283 1
0402
C257 1
0402
C259 1
0402
C99
2 CPU_THERMDC
20 THERN_ALERM#
CHANGE VALUE
2 5P
+/-10%
2 22P
+/-10%
2 22P
+/-10%
+3V
+3V
1
MODE A MODE B
2 0402
33
2
CLK_LPC33
1
FS0
R243 1 22
R244 1 0402
CLK_KBC 19
R145
10K
0402
5%
C109
0.1U
0402
+80-20%
50V
R146
10K
0402
5%
2
FS1
R233 1 10K/NA 2 0402
C
8
11
12
0402
0402
ON:for ISC950403
OFF:for RTM360803
2
R231 1 10K/NA 2 0402
GND
2 22
2 22
D
+3V
R809
PCI_CARD_CLK 14
MINI_PCI_CLK 15
X3
X2
ICS950405
SSOP48
FS2
R262 1
R264 1
CPUCLK- 2
CPUCLK+ 2
t
t
n
e e
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id
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C
L59 120Z/100M 1608
1
2
R239 1 10K/NA 2 0402
R247
R245
1
R252 1 10K/NA 2 0402
48MHZ/FS3**
REF2/FS2*
REF1/FS1*
*FS0/REF0
R246 PCI_CARD_CLK
2 27
R248 MINI_PCI_CLK
2 27
2 27/NA R249
2
R230 1 22
10 14M_SB_IOSC
2
2
2
2
2
2
~PCICLK8/HTTCLK2
~PCICLK9/HTTCLK3
PCICLK10
24_48MHZ/SEL24_48#*~
AVDD48
0603 1
0603 1
0603 1
1
22
22
22
22
22/NA
22
VDDA
2 15
2 15
13
14
17
18
21
22
24
2
GUICLK
1
1
1
1
1
1
VDDCPU_0
VDDCPU_1
0603 1
0603 1
1
7 GUICLK
R258
R253
R240
R238
R232
R234
LPC_48M
PCICLK0
PCICLK1
~PCICLK2
~PCICLK3
PCICLK4
PCICLK5
~PCICLK6
須用 1%
40
41
36
37
2
USB_CLK
LPC_48M
AUDIO_14M
14M_SB_APICCLK
CPUCLK8C0
CPUCLK8T0
CPUCLK8C1
CPUCLK8T1
VDDPCI_0
VDDPCI_1
VDDPCI_2
1
8
15
18
10
VDDREF_0
VDDREF_1
1
2
46
C265
0.1U
0402
+80-20%
2
1
1
C240
0.1U
0402
+80-20%
GND
2
1
2
1
C245
0.1U
0402
+80-20%
2
2
1
2
1
C262
10U
0805
6.3V
2
2
120Z/100M
2012
C267
10U
0805
6.3V
2
L58
1
D
B
U5
GND
1
2
3
4
SMBCLK
VDD
SMBDATA
D+
ALERT
DGND
T_CRIT_A
8
7
6
5
THRM_CLK 19
THRM_DATA 19
G781
SO8
PN:284500781001
GND
4~15
1~12
1~12
GND
A
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
Mhz
100.90
133.90
168.00
202.00
100.20
133.50
166.70
200.40
150.00
180.00
210.00
240.00
270.00
233.33
266.67
300.00
HTT
Mhz
67.27
66.95
67.20
67.33
66.80
66.75
67.68
66.80
60.00
60.00
70.00
60.00
67.50
66.67
66.67
75.00
PCI
Mhz
33.63
33.48
33.60
33.67
33.40
33.38
33.34
33.40
33.00
33.00
35.00
30.00
33.75
33.33
33.33
37.50
1. 6 : 24
2. Series resistors less than 1
3. PCI_SB_CLK is 3 more than the
longest PCI clock
GUICLK
DEFAULT
LPC_48M
CLK_LPC33
C242 1
0402
C270 1
0402
C281 1
0402
2 22P
+/-10%
2 22P
+/-10%
2 22P
+/-10%
A
GND
Title
<Title>
Size
C
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
5
of
26
5
4
3
+3V
U12C
B7
C7
R16
R17
R21
R25
T10
T11
T12
T13
T14
T15
T16
T17
U10
U11
U12
U13
U14
U15
U16
U17
V5
W5
W21
W22
W23
W24
W25
W26
AB2
AB3
AB4
AB5
AB6
AB9
AB10
AB15
AB16
AC8
AC22
AC23
B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
1
C98
0402
C102
0402
C104
0402
C650
0402
C654
0402
C658
0402
AA21
AA22
AA23
AA24
AA25
AA26
AB21
AB22
AB23
AB24
AB25
AB26
F9
H10
H11
H12
H15
H16
H8
H9
J8
K19
L19
M19
P8
R19
R8
T19
U19
V18
V19
W10
W11
W12
W13
W14
W19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
1
1
1
1
1
1
C23
0402
C13
0402
C14
0402
C78
0402
C77
0402
C24
0402
C18
0402
C17
0402
R4181
2 LDTSTOP_NB#
3 NB_LDTRST#
1
1
1
1
1
1
+1.5V
+1.5V
AC24
AE2
AE5
AE8
AE11
AE14
AE17
AE20
AE22
AE25
L502 1
2 2012
C659
10U
0805
10V
+80-20%
2 2012
120Z/100M
C662
10U
0805
10V
+80-20%
+1.5V
L504 1
+1.5VPLL1
C663
0.01U
0402
+80-20%
50V
2 2012
+3.3VDACVDD
2 2012
+2.5VS
A10
A24
A25
A26
A9
B10
B23
B24
B25
B26
B9
C10
C11
C23
C24
C25
C9
D10
D11
D22
D23
D24
D9
E10
E11
E21
E22
E23
E24
E9
F10
F11
F15
F16
F19
F20
F21
F22
F23
G21
G22
H21
J10
J11
J12
J13
J14
J15
J16
J17
K18
K21
L18
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
B
K8N800
BGA451_110_26
2
C29
0.01U
0402
+80-20%
50V
C9
10U
0805
10V
+80-20%
GND
+NB_VCCSUS
R168 1 22
2 0603
1
1
1
C12
10U
0805
10V
+80-20%
2
2
1
2
1
1
1
2
0.1U
0402
10%
L0_CTLIN_L0 2
是否能改為+2.5VS_DDR
120Z/100M
120Z/100M
C417
C665
0.01U
0402
+80-20%
50V
GND
L4 1
120Z/100M
C
2 2012
C664
10U
0805
10V
+80-20%
GND
+1.5V
2
120Z/100M
+3V
2
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
+1.5V_VCCVL
L0_CADIN_L[0..15]
L21
M18
N18
N21
P18
P21
R18
T18
T21
T22
T23
T24
T25
U18
U21
U22
U23
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
VCCHT
RPCOMP
RNCOMP
RTCOMP
U24
U25
U26
V21
V22
V23
V24
V25
V26
C660
0.01U
0402
+80-20%
50V
2
+1.2VLDTA
+1.2VLDTA
120Z/100M
+1.5V_NB
L503 1
L2 1
C25
0.01U
0402
+80-20%
50V
D25
D26
C26
L0_CADIN_H[0..15]
L0_CLKIN_L0 2
L0_CLKIN_L1 2
A22
TCTL#
HTRST#
HTSTP#
+1.5V_VCCAGP
L0_CADIN_L0
L0_CADIN_L1
L0_CADIN_L2
L0_CADIN_L3
L0_CADIN_L4
L0_CADIN_L5
L0_CADIN_L6
L0_CADIN_L7
L0_CADIN_L8
L0_CADIN_L9
L0_CADIN_L10
L0_CADIN_L11
L0_CADIN_L12
L0_CADIN_L13
L0_CADIN_L14
L0_CADIN_L15
C16
E17
TCLK0#
TCLK1#
RCTL#
B11
A12
C12
A14
C14
A16
A18
C18
A20
C20
E13
C13
E15
C15
C17
E19
C19
D21
TCAD0#
TCAD1#
TCAD2#
TCAD3#
TCAD4#
TCAD5#
TCAD6#
TCAD7#
TCAD8#
TCAD9#
TCAD10#
TCAD11#
TCAD12#
TCAD13#
TCAD14#
TCAD15#
RCLK0#
RCLK1#
GND
2 2012
C164
10U
0805
10V
+80-20%
F25
GND
GND
+NB_AVDD2
0
L26
L23
2 L0_CTLOUT_L0
2 0402
L0_CLKIN_H0 2
L0_CLKIN_H1 2
L0_CTLIN_H0 2
L0_CADIN_L[0..15]
A21
TCTL
RCAD0#
RCAD1#
RCAD2#
RCAD3#
RCAD4#
RCAD5#
RCAD6#
RCAD7#
RCAD8#
RCAD9#
RCAD10#
RCAD11#
RCAD12#
RCAD13#
RCAD14#
RCAD15#
L0_CADIN_H0
L0_CADIN_H1
L0_CADIN_H2
L0_CADIN_H3
L0_CADIN_H4
L0_CADIN_H5
L0_CADIN_H6
L0_CADIN_H7
L0_CADIN_H8
L0_CADIN_H9
L0_CADIN_H10
L0_CADIN_H11
L0_CADIN_H12
L0_CADIN_H13
L0_CADIN_H14
L0_CADIN_H15
B16
E16
TCLK0
TCLK1
RCTL
R26
P25
N26
M25
K25
J26
H25
G26
R23
P22
N23
M22
K22
J23
H22
G23
2 L0_CLKOUT_L0
2 L0_CLKOUT_L1
RPCOMP
RNCOMP
RTCOMP
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
1
K8N800
BGA451_110_26
L7 1
L0_CADOUT_L0
L0_CADOUT_L1
L0_CADOUT_L2
L0_CADOUT_L3
L0_CADOUT_L4
L0_CADOUT_L5
L0_CADOUT_L6
L0_CADOUT_L7
L0_CADOUT_L8
L0_CADOUT_L9
L0_CADOUT_L10
L0_CADOUT_L11
L0_CADOUT_L12
L0_CADOUT_L13
L0_CADOUT_L14
L0_CADOUT_L15
2,10 LDTSTOP#
1
RCLK0
RCLK1
F24
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
2 L0_CADOUT_L[0..15]
+1.2VLDTA
M26
L24
2 L0_CLKOUT_H0
2 L0_CLKOUT_H1
2 L0_CTLOUT_H0
L0_CADOUT_L[0..15]
GND
GND
+3V
VCCATX
C22
GND
+1.5V_NB
+1.5V_NB
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
1
L0_CADIN_H[0..15]
B12
A13
B14
A15
A17
B18
A19
B20
E12
D13
E14
D15
D17
E18
D19
E20
TCAD0
TCAD1
TCAD2
TCAD3
TCAD4
TCAD5
TCAD6
TCAD7
TCAD8
TCAD9
TCAD10
TCAD11
TCAD12
TCAD13
TCAD14
TCAD15
C28
0.01U
0402
+80-20%
50V
R169
33
0603
C120
10U
0805
10V
+80-20%
1
C
VCCVL
VCCVL
VCCVL
VCCVL
VCCVL
VCCVL
VCCVL
VCCVL
VCCVL
VCCVL
VCCVL
VCCVL
VCCVL
VCCVL
VCCVL
VCCVL
1
RCAD0
RCAD1
RCAD2
RCAD3
RCAD4
RCAD5
RCAD6
RCAD7
RCAD8
RCAD9
RCAD10
RCAD11
RCAD12
RCAD13
RCAD14
RCAD15
2
AB17
AB18
AB19
AB20
AC18
AC19
AC20
AC21
V14
V15
V16
V17
W15
W16
W17
W18
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
1
U12A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+1.5V_VCCVL
C72
0402
C76
0402
C130
0402
C81
0402
C106
0402
T26
P24
P26
M24
K24
K26
H24
H26
R24
R22
N24
N22
L22
J24
J22
G24
GNDATX
GND
D
A23
A8
B8
B13
B15
B17
B19
B21
B22
C8
D6
D8
D12
D14
D16
D18
D20
E5
E6
E8
F7
F8
F12
F13
F14
F17
F18
F26
G1
G25
H1
H2
H23
J18
J2
J3
J21
J25
K4
K10
K11
K12
K13
K14
K15
K16
K17
K23
L10
L11
L12
L13
L14
L15
VCCRGB
VCCDAC
GNDRGB
GNDDAC
GNDDAC
L0_CADOUT_H0
L0_CADOUT_H1
L0_CADOUT_H2
L0_CADOUT_H3
L0_CADOUT_H4
L0_CADOUT_H5
L0_CADOUT_H6
L0_CADOUT_H7
L0_CADOUT_H8
L0_CADOUT_H9
L0_CADOUT_H10
L0_CADOUT_H11
L0_CADOUT_H12
L0_CADOUT_H13
L0_CADOUT_H14
L0_CADOUT_H15
C21
A4
B2
B4
C3
D4
L0_CADOUT_H[0..15]
2 L0_CADOUT_H[0..15]
1
GND
+3.3VDACVDD
GND
+1.5V
2
VCCPLL3
GNDPLL3
2 0.1U
10%
2 0.1U
10%
2
A6
B6
C651 1
0402
C655 1
0402
1
+1.5VPLL2
+1.2VLDTA
+NB_AVDD2
1
GND
GND
+1.5V_VCCAGP
2
VCCPLL1
VCCPLL2
GNDPLL1
GNDPLL2
2
D5
A5
C5
B5
1
1
1
+1.5VPLL1
1
1
D
GND
1
2
GND
1
1
2
NB VIA_K8N800 (1/2)
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
1
1
VCCARX
GNDARX
C649
0402
C652
0402
C653
0402
C656
0402
C657
0402
2
E25
E26
1
2
+NB_AVDD1
AA4
AA5
AB11
AB12
AB13
AB14
AB7
AB8
M8
N8
T2
T3
T4
T5
T8
T9
U2
U3
U4
U5
U8
U9
V10
V11
V12
V13
V2
V3
V4
V8
V9
W2
W3
W4
W9
Y3
Y4
Y5
1
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
VCCAGP
1
1
VCCSUS
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
2 0.1U
10%
1
2
AC25
C45
0402
C49
0402
C58
0402
C60
0402
+1.5V_VCCAGP
2
+NB_VCCSUS
+1.5V_VCCVL
C119
0.01U
0402
+80-20%
50V
+1.2VLDTA
RNCOMP
R19
1 49.9 1% 2 0603
RTCOMP
R24
1 100 1% 2 0402
RPCOMP
R25
1 49.9 1% 2 0603
GND
GND
GND
GND
A
+3V
+NB_AVDD1
L24 1
GND
GND
GND
+1.5V
2 2012
A
+1.5VPLL2
L3 1
+3.3VDACVDD
2 2012
L5 1
120Z/100M
2 2012
120Z/100M/NA
2
C30
0.01U
0402
+80-20%
50V
1
C11
10U/NA
0805
10V
+80-20%
2
1
1
C8
10U
0805
10V
+80-20%
2
0.1U
0402
10%
1
C418
1
C38
0.01U
0402
+80-20%
50V
2
1
C35
10U
0805
10V
+80-20%
2
2
1
2
120Z/100M
+3V
C27
0.01U/NA
0402
+80-20%
50V
Title
<Title>
Size
C
GND
GND
GND
GND
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
6
of
26
5
4
3
2
1
NB VIA_K8N800 (2/2)
+1.5V
10 UPSTB
10 UPSTB#
AE23
AF23
10 DNSTB
10 DNSTB#
AF22
AD22
AF26
AD23
10 UPCMD
10 DNCMD
LVREF_NB
AF21
LCOMPP
AD19
AE26
3,9,20 ALL_PWROK_2.5V
AD25
8,11,19 NB_PCIRST#
9 SUSST1#
TESTIN
AC26
SUSST1#
AD26
DEBUG
AC17
B3
A3
A2
11 CRT_RED
11 CRT_GREEN
11 CRT_BLUE
C
RSET
C4
A1
B1
11 CRT_HSYNC
11 CRT_VSYNC
C6
5 GUICLK
PCI_INTA#
BISTIN
8 PCI_INTA#
11
11
11
11
I2C_CLK
CRT_DDCK
I2C_DATA
CRT_DDDA
11
11
11
11
11
11
11
11
11
11
11
11
R39 1 0
5% 2 0402
R1211 0
5% 2 0402
FPD0
FPD1
FPD2
TVD0
TVD1
TVD2
TVD3
TVD4
TVD5
TVD6
TVD7
TVD8
TVD9
TVD10
TVD11
11 TVCLKI
11 TV_DS
11 TVHS
11 TVVS
11 TVCLK
FPD10
R60
1 0
1 0
P2
C2
P1
C1
J1
K2
K3
L4
K1
L2
L3
M4
L1
M2
M3
M1
FPD4
FPD5
FPD6
FPD7
FPD8
R72
E7
D3
2 0402
2 0402
P4
N1
N4
N3
P3
VBE#
VPAR
UPSTB
UPSTB#
DNSTB
DNSTB#
UPCMD
DNCMD
VLVREF
VLPCOMP
PWROK
RESET#
TESTIN
1 0/NA
1 0/NA
2 0402
2 0402
DISPDCLKO
DISPDCLKI
N2
D2
A7
D7
NB_FPD01
NB_FPD23
NB_FPD00
NB_FPD22
NB_FPD21
NB_FPD20
NB_FPD18
NB_FPD17
NB_FPD16
NB_FPDE
NB_FPD14
NB_CLK+
NB_FPD13
NB_FPD15
12
12
12
12
12
GBE0/DP3D03
GBE1/SBDAT
GBE2/DP2D07
GBE3/DP1D11
DEBUG
AR
AG
AB
GDS0S/GDS0#/DP3D02
GDS0F/GDS0/DP3D04
GDS1S/GDS1#/DP2DET
GDS1F/GDS1/DP2D00
RSET
HSYNC
VSYNC
GFRE/DP2HS
GIRDY/SBCLK
GTRDY
GDSEL/DP2VS
GSTOP/DP3CLK#
GPAR/DP3VS
GRBF
GWBF/DP2CLK#
GREQ/DDCCLK
GGNT/DDCDAT
GSERR/DP3DE
XIN
INTA#
BISTIN
SPCLK1
SPCLK2
SPDAT1
SPDAT2
TVD00/DP0D00/STRAP
TVD01/DP0D01/STRAP
TVD02/DP0D02/STRAP
TVD03/DP0D03/STRAP
TVD04/DP0D04/STRAP
TVD05/DP0D05/STRAP
TVD06/DP0D06/STRAP
TVD07/DP0D07/STRAP
TVD08/DP0D08
TVD09/DP0D09
TVD10/DP0D10/STRAP
TVD11/DP0D11
GCLK
SBA0#/DP1VS
SBA1#/DP1DE
SBA2#/DP1D00
SBA3#/DP1HS
SBA4#/DP1D05
SBA5#/DP1D03
SBA6#/DP1CLK
SBA7#/DP1CLK#
SBSS/SBS#/DP1D02
SBSF/SBS/DP1D01
TVCKI/DP0DET
TVDE/DP0DE
TVHS/DP0HS
TVVS/DVP0VS/NC
ST0
ST1/DP1D04
ST2
TVCLK/DP0CLK
AGPPCOMP
AGPNCOMP
GPO0
GPOUT
AGPVREF_0
AGPVREF_1
DCLKO
DCLKI
AGP8XDT#
1
1
R157
33
0603
R166
1K
0402
1%
GND
GND
2
C118
1U
0402
+80-20%
10V
GND
+3V
1 10K
2 0402
DEBUG
R164 1 10K
2 0402
BISTIN
R40
2 0402
LCOMPP
R165 1 360 1% 2 0402
RSET
R14
AGP_AD8
AGP_8XDE#
R99
AGP_GD31
AD15
AF11
AD11
AC7
NB_FPD03
AF15
AE15
NB_FPD02
NB_FPD04
AF7
AE7
AGP_ADSTBS1
NB_FPD12
AC9
AC10
AC14
AC11
AC12
AC16
AD6
AC1
Y1
AA3
AC15
NB_FPHS
NB_FPD19
NB_FPVS
NB_FPCLK-
A11
NB_FPD03 12
R1581 0
5% 2 0402
I2C_DATA_LVDS 12
NB_FPD19 12
NB_FPD02 12
NB_FPD04 12
NB_FPD12 12
NB_FPHS 12
R42 1 0
5% 2 0402
I2C_CLK_LVDS 12
NB_FPVS 12
1 1K
I2C_CLK
R31
1 4.7K
2 0402
I2C_DATA
R130 1 4.7K
2 0402
SP_SSON
R1
2 0402
1 1K
1 90.9 1% 2 0402
C
R163 1 0
2 0402
AGP_ADSTBS1 R162 1 0
2 0402
SP_MRA
R8
1 0
2 0402
SP_SR1
R3
1 0NA
2 0402
SP_SR0
R2
1 0
2 0402
AGP_GD31
R105 1 0
2 0402
+2.5V
TESTIN
R137 1 4.7K
SUSST1#
R314 1 10K/NA 2 0402
2 0402
+3VS
+1.5V
NB_FPCLK- 12
GND
AGPNCOMP
R90
1 60.4 1% 2 0402
AGPPCOMP
R81
1 60.4 1% 2 0402
66M_AGP 5
GND
AC2
AC3
AD1
AD2
AF2
AD3
AE3
AF3
AE1
AF1
AA2
AA1
AB1
ENAVEE
ENAVDD
ENPBLT_NB
V1
W1
AGPPCOMP
AGPNCOMP
FPD4
R108 1 4.7K
2 0402
AC13
AC6
AGP_VREF
FPD5
R109 1 4.7K
2 0402
FPD6
R86
1 4.7K
2 0402
FPD8
R414 1 4.7K
2 0402
FPD7
R110 1 4.7K
2 0402
FPD10
R111 1 4.7K
2 0402
Y2
AGP_8XDE#
ENAVEE 12
ENAVDD 12
+3V
AGP_8X# 10
B
AC4
AC5
GNDQQ
K8N800
BGA451_110_26
+1.5V
+3V
GND
1
T1
L16
L17
L25
M10
M11
M12
M13
M14
M15
M16
M17
M21
M23
N10
N11
N12
N13
N14
N15
N16
N17
N25
P5
P10
P11
P12
P13
P14
P15
P16
P17
P23
R1
R2
R3
R4
R5
R10
R11
R12
R13
R14
R15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GDBIL
GDBIH/GPIPE#
D
LVREF_NB
AGP_VREF
NB_FPD01 12
NB_FPD23 12
NB_FPD00 12
NB_FPD22 12
NB_FPD21 12
NB_FPD20 12
NB_FPD18 12
NB_FPD17 12
NB_FPD16 12
NB_FPDE 12
NB_FPD14 12
NB_FPCLK+ 12
NB_FPD13 12
NB_FPD15 12
C121
1U
0402
+80-20%
10V
1
NB_FPD09
NB_FPD08
NB_FPD07
NB_FPD06
NB_FPD05
R170
3K
0402
1%
2
NB_FPD09
NB_FPD08
NB_FPD07
NB_FPD06
NB_FPD05
AGP_AD8
R156
110
0603
1%
NB_FPD10 12
NB_FPD11 12
1
U1
1
NB_FPD10
NB_FPD11
2
AF18
AD18
AE18
AF17
AD17
AD16
AE16
AF16
AF14
AD14
AD13
AE13
AF13
AD12
AF12
AE12
AD10
AE10
AF10
AD9
AF9
AF8
AE9
AD8
AF6
AD7
AE6
AD5
AF5
AF4
AE4
AD4
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
SUSST#
B
R58
R33
GD0/DP3D10
GD1/DP3D11
GD2/DP3CLK
GD3/DP3D09
GD4/DP3D08
GD5/DP3D07
GD6/DP3D06
GD7/DP3D05
GD8/DP3DET
GD9/DP3HS
GD10/DP3D01
GD11/DP2D11
GD12DP3D00
GD13/DP2D10
GD14/DP2D09
GD15/DP2D08
GD16/DP2D06
GD17/DP2D05
GD18/DP2D04
GD19/DP2DE
GD20/DP2D02
GD21/DP2CLK
GD22/DP2D01
GD23/DP2D03
GD24/DP1D09
GD25
GD26/DP1D10
GD27
GD28/DP1D07
GD29/DP1D06
GD30/DP1D08
GD31/DP1DET
2
AE21
AF19
10 VBE#
10 VPAR
VAD0
VAD1
VAD2
VAD3
VAD4
VAD5
VAD6
VAD7
1
AD20
AD21
AF24
AE24
AE19
AF20
AD24
AF25
+2.5V
2
VAD0
VAD1
VAD2
VAD3
VAD4
VAD5
VAD6
VAD7
VCCQQ
VAD[0..7]
10 VAD[0..7]
D
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
D1
E1
E2
E3
E4
F1
F2
F3
F4
F5
F6
G2
G3
G4
G5
H3
H4
H5
J4
J5
J9
K5
K8
K9
L5
L8
L9
M5
M9
N5
N9
P9
R9
+1.5V
U12B
2
+3V
2
GND
ENPBLT_NB
1
2
R1
R434
10K
0402
5%
3
ENPBLT 12
1
Q3
2
DTC114TKA
R7
1 22/NA
2 0402
1
DISPDCLKI
C426
0.1U/NA
0402
+80-20%
50V
R6
22
0402
5%
GND
A
+3V
2
A
U1
DISPDCLKO
SP_MRA
SP_SR1
1
2
3
4
CLKIN
MRA
SR1
VSS
VDD
SR0
MODOUT
SSON
8
7
6
5
SP_SR0
SP_SSON
P2040/NA
SO8
Title
GND
<Title>
Size
C
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
7
of
26
5
4
3
2
1
SB VIA_VT8235CD (1/3)
+3VS_USB
+2.5VS
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
14,15
14,15
14,15
14,15
14,15
14,15
14,15
14,15
PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_SERR#
PCI_PAR
PCI_PERR#
7
14
15
15
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
14 PCI_REQ0#
15 PCI_REQ1#
14 PCI_GNT0#
15 PCI_GNT1#
F4
D1
A4
L1
PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_SERR#
PCI_PAR#
PCI_PERR#
B4
B3
C4
A3
C3
C1
D3
C2
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
P1
P2
P3
R1
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_REQ#5
D6
C5
D4
H4
L4
N4
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4
PCI_GNT#5
E6
D5
E4
J4
M4
P4
R22
5 PCI_SB_CLK
R297 1 22
2 0402
R2
PLLGNDA
PLLGNDA
1
2
1
2
C312
0.1U
0402
+80-20%
120Z/100M
50V
L63 1
2 2012
1
2
2
B23
E22
C317
10U
0805
10V
+80-20%
1
D22
A23
1
PLLVDDA
PLLVDDA
D15
2
USBSUS25
C338
C342
0.1U
4.7U
0402
0805
+80-20%
+80-20%
50V
GND
GND
+2.5V
120Z/100M
L61 1
2 2012
T4
U4
2
D24
A24
A25
A26
B24
B25
B26
C24
C25
C26
L68
120Z/100M
2012
U20A
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
VSUS25
VSUS25
RP50 1 15K*4
2
3
4
8 1206
7
6
5
USBP2+
USBP2USBP3+
USBP3-
RP46 1 15K*4
2
3
4
8 1206
7
6
5
USBP4+
USBP4USBP5+
USBP5-
RP49 1 15K*4
2
3
4
8 1206
7
6
5
D
GND
C309
10U
0805
10V
+80-20%
+3V
USBP0+
USBP0USBP1+
USBP1USBP2+
USBP2USBP3+
USBP3USBP4+
USBP4USBP5+
USBP5-
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
SERR#
PAR
PERR#
INTA#
INTB#
INTC#
INTD#
A21
B21
E21
D21
A19
B19
E19
D19
A17
B17
E17
D17
USBP0+
USBP0USBP1+
USBP1USBP2+
USBP2USBP3+
USBP3USBP4+
USBP4USBP5+
USBP5-
USBP0+
USBP0USBP1+
USBP1USBP2+
USBP2USBP3+
USBP3USBP4+
USBP4USBP5+
USBP5-
GND
17
17
17
17
17
17
17
17
17
17
17
17
SB_KA20G RP57
SB_KBRC
SB_IRQ1
SB_IRQ12
USBCLK
USB REXT
A15
B15
C15
E15
D14
E14
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
D23
C23
2 0402
IPBTDFR/GPI14/GPO14
IPBRDFR/GPI10/GPO10
IPBTDCK/GPI15/GPO15
IPBRDCK/GPI11/GPO11
IPBOUT0/GPI12/GPO12
IPBOUT1/GPI13/GPO13
IPBIN0/GPI8/GPO8
IPBIN1/GPI9/GPO9
GNT0#
GNT1#
GNT2#
GNT3#
GNT4#
GNT5#
PCICLK
PCIRST#
B
V3
V2
W2
W1
D8
D7
C7
A6
A7
B8
C8
B7
SB_KA20G
SB_KBRC
SB_IRQ1
SB_IRQ12
1
2
3
4
5
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
1
2
3
4
5
4.7K*8
RP51
10
9
8
7
6
C
1
2
3
4
5
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
1206
10
9
8
7
6
4.7K*8
KBD_CS0
KBD_CS1
SB_GPIO12
SPKR_MUTE#
1206
RP55
2.2K*8
ENBL_SB 12
KBD_CS0 19
MPCIACT# 15
KBD_CS1
SB_GPIO12
SPKR_MUTE#
MB_ID0
MB_ID1
+3V
1%
A20G 19
KBRC# 19
KBD_CS0
1206
RP54
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
USB_CLK 5
R287 1 5.6K
8
7
6
5
+3V
17
17
17
17
17
17
GND
KBCK/KA20G
KBDT/KBRC
MSCK/IRQ1
MSDT/IRQ12
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
REQ5#
1 10K*4
2
3
4
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
USBOC0#
USBOC1#
USBOC2#
USBOC3#
USBOC4#
USBOC5#
A1
A2
B1
B2
E9
E16
E23
E25
G5
H23
H25
K4
L11
AC9
AC8
PCI_RST#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
USBP0+
USBP0USBP1+
USBP1-
PCI_GNT#4
PCI_GNT#5
PCI_REQ#4
PCI_REQ#5
10
9
8
7
6
PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_TRDY#
1206
RP48
PCI_STOP#
PCI_SERR#
PCI_PAR#
PCI_PERR#
LCD_ID2 12
10
9
8
7
6
1
2
3
4
5
4.7K*8
1206
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
C
14,15
14,15
14,15
14,15
H3
J2
H2
J1
G3
H1
G2
G1
G4
F2
F1
E1
F3
E2
E3
D2
B5
A5
C6
B6
K1
J3
K2
K3
L2
L3
M2
M1
M3
N1
N3
N2
A16
A18
A20
A22
B16
B18
B20
B22
C16
C17
C18
C19
C20
C21
C22
D16
D18
D20
E18
E20
F18
F19
F21
F20
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
PCI_AD[0..31]
14,15 PCI_AD[0..31]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D
E5
F5
F7
F8
F12
F13
F16
F17
L5
M5
P5
P21
R5
R21
W5
Y5
Y21
AA21
AB6
AB7
AB10
AB11
AB14
AB15
AB20
AB21
AC18
AC19
1
+3V
VT8235
BGA451_36_1MM
B
GND
+3V
U8B
2
+3V
R278
10K/NA
0402
5%
MB_ID0
14
A
C327
0.1U
0402
+80-20%
1
1
C391
10U
0805
+80-20%
C348
0.1U
0402
+80-20%
GND
2
C325
0.1U
0402
+80-20%
1
C322
10U
0805
10V
+80-20%
C316
0.1U
0402
+80-20%
GND
MB_ID1
A
1
7
10
74HCT08_V
TSSOP14
LPC_RST# 7,11,19
R279
10K
0402
5%
NB_PCIRST# 7,11,19
TV_PCIRST# 7,11,19
R281
10K
0402
5%
2
8
1
U8C
9
2
PCI_RST#
+3V
2 2012
120Z/100M
2
R282
10K/NA
0402
5%
+3VS_USB
L65 1
2
1
+3V
1
+3V
+3VS
2
GND
1
GND
CPU_PCIRST# 3
74HCT08_V
TSSOP14
2
IDE_PCIRST# 13,14,15
6
5
1
MINI_PCIRST# 13,14,15
4
2
7
74HCT08_V
TSSOP14
CARD_PCIRST# 13,14,15
2
PCI_RST#
3
2
1
U8A
1
7
PCI_RST#
14
14
+3V
GND
GND
Title
GND
<Title>
Size
C
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
8
of
26
3
+3VS
CLKRUN# 14,15
ISA_ROMCS#
ISA_SOE#
IOR#
IOW#
TESTB
GPI19
AF11
AE11
AD11
AC11
SA16
SA17
SA18
SA19
AC14
AC13
AF14
AE14
AD14
AF13
AE13
AD13
XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7
ISA_MEMR# 17
ISA_MEMW# 17
ISA_ROMCS# 17
ISA_SOE# 17
PME#
GND
C
MPCI_PME# 14,15
CARD_PME# 14,15
ISA_SD0
ISA_SD1
ISA_SD2
ISA_SD3
ISA_SD4
ISA_SD5
ISA_SD6
ISA_SD7
+5V
+3VS
RP67
ISA_SD0
ISA_SD1
ISA_SD2
ISA_SD3
17
17
17
17
17
17
17
17
1
2
3
4
5
10
9
8
7
6
10K*8
ISA_SD4
ISA_SD5
ISA_SD6
ISA_SD7
+2.5V
RP56
PWROK#
WAKE_UP#
EXTSMI#
SCI#
1
2
3
4
5
10K*8
1206
10
9
8
7
6
GPI4
SUSA#
SUSCLK
GPO0
10
9
8
7
6
R367
+3V
1
SA[18]==>LDT Width
0 - Disable (Default)
1 - Ensable
0 - 8-Bit (Default)
1 - 16-Bit
R319
383
0603
+3V
+3V
R352
383
0603
GND
GND
2
2
2
2
R364
2.7K
R360
2.7K/NA
0603D
R361
2.7K/NA
0603D
A
1
1
1
0603D
1
SVREF
1
1
SA[19]==>Fast command
0 - Disable (Default)
1 - Ensable
PVREF
2
2
SDA2 ==> ROMSIP Select
R351
1K
0402
5%
2
R317
1K
0402
5%
2.7K
0603D
+3V
SDA0
+3V
1
2
2
R379
2.7K/NA
0603D
GND
0603D
1
GND
1
1
2
1
R381
GND
R380
2.7K/NA
B
SDCS3#
GND
0603D
C392
0.1U
0402
+80-20%
2.7K/NA
0603D
SDCS1#
GND
R363
2.7K/NA
C349
0.1U
0402
+80-20%
R365
2.7K
0603
+3V
C350
10U
0805
+80-20%
2
2
1
2
1
2
SDCS3# ==> Test Mode Select
0 - Disable (Default)
1 - Ensable
+3V
ISA_ROMCS#
0 - Disable (Default)
1 - Ensable
+3V
1206
SDCS1# ==> EEPEOM Select
R376
10K
GND
GPO5
GPO6
IOR#
IOW#
+3V
SDA1 ==>
Extermal loop test mode
C334
0.1U
0402
+80-20%
RP65
1
2
3
4
5
0 - BIOS Porting - ACR
1 - Exteral EEPROM (On-board)(Default)
R362
10K/NA
R372
2.7K
0603
SDA2
SA19
SA18
R366
GND
2
R378
2.7K/NA
0603
R375
2.7K
0603
1
2.7K
0603
1
2.7K/NA
0603
R374
2.7K
0603
Title
<Title>
1
R377
2
2
2
SDA1
GND
GND
GND
Size
C
GND
Date:
5
C394
0.1U
0402
+80-20%
1206
2
ROMCS# ==> LPC Interface Select
0603D
+3V
C393
10U
0805
+80-20%
+3V
0 - Disable LPC
1 - Ensable LPC (Default)
SA17
SDA0 ==>
LDT Trasmit Timing control
R371 1 1K 5% 2 0402
AGP_PME# 14,15
0603D
GND
1
1
C8
B7
D7
A6
A7
B8
D8
C7
U2
V1
R24
P26
AE5
AE6
AD1
AE1
P25
P24
AD6
AC6
2
MB_ID0
MB_ID1
KBD_CS0
KBD_CS1
RESERVE
RESERVE
ENBL_SB
MPCIACT#
RESERVE
RESERVE
SB_GHI#
RESERVE
SPKR_MUTE#
RESERVE
RESERVE
RESERVE
AGP_8X#
RESERVE
CRT_IN#
MINIPCI_PD
1
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3VS
+3VS
+3V
+3V
+3V
+3V
2
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
R373
2.7K
0603
1
AA3
AA2
AF2
Y3
AB1
AC7
AF6
P4
AF11
AE11
AD11
AC11
2 0402
TESTB
R326
10K/NA
0402
5%
DTC144TKA/NA
GPIO24
GPIO25
GPIO30
GPIO31
R358
2.7K/NA
0603D
2
RESERVE
SUSA#
SUSB#
SB_SUSST#
RESERVE
RESERVE
RESERVE
SB_SLP#
SEE STRAP TABLE
SEE STRAP TABLE
SEE STRAP TABLE
SEE STRAP TABLE
0603D
SA16
2 0402
R299 1 4.7K
LCD_ID1 12
+3VS
1
+3VS
+3VS
+3VS
+3VS
+3VS
+3V
+3V
+3V
R359
2.7K/NA
R302 1 4.7K
ACSDIN3
VT8235
BGA451_36_1MM
+3V
2
GPO0
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
GPO16
GPO17
GPO18
GPO19
+3V
3
R350 1 360 1% 2 0402
ACSDIN2
Q34
ISA_SA16 17
ISA_SA17 17
ISA_SA18 17
ISA_SD0
ISA_SD1
ISA_SD2
ISA_SD3
ISA_SD4
ISA_SD5
ISA_SD6
ISA_SD7
+3V
R311
10K
0402
5%
1
R315 1 360 1% 2 0402
SCOMPP
1
AE12
AF10
AF12
AD12
AC10
AD9
AF9
AD10
+3V
1
CRT_IN# 11
MINIPCI_PD 15
PCOMPP
2
SA16/GPO16
SA17/GPO17
SA18/GPO18
SA19/GPO19
1
A
PINOUT
AE3
AC3
AA1
Y2
AC1
W4
A8
N4
AD3
Y1
Y4
AD10
2
SB_GPO0 18
TP8
MEMR#
MEMW#
ROMCS#/KBCS#
SOE#
IOR#/GPI22/GPO22
IOW#/GPI23/GPO23
TEST
IORDY#/GPI19
00 - 200MHz (Default) 10 - 600MHz
01 - 400MHz
11 - 800MHz
RESERVE
RESERVE
EXTSMI#
VAKE_UP#
MII_PWRDWN
PME#
SCI#
RESERVE
RESERVE
LCD_ID0
THRM#
LCD_ID1
SMB_DATA0 4,5
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
PCLKRUN#
CPUSTP#/GPO5
PCISTP#/GPO6
SA[17:16]==>LDT Frequency
VCC_RTC
+3VS
+3VS
+3VS
+3VS
+3VS
+3V
+3V
VCC_RTC
+3V
+3V
+3V
S
Q37
2N7002
1
CLKRUN#
GPO5
GPO6
D
2
AF5
AC7
AF6
0 - Ensable
1 - Dnsable(default)
R344
10K
0402
5%
1
GPI0
GPIOA/GPI24/GPO24
GPIOC/GPI25/GPO25
GPIOD/GPI30/GPO30
GPIOE/GPI31/GPO31
2 0402
1
GPI0
GPIO24
GPIO25
GPIO30
GPIO31
2 0402
R354 1 4.7K
2
AE3
AE5
AE6
AD6
AC6
SMBDATA1
SUSA# 5
SUSB# 19,20,22
SUSC# 19,21
R322 1 10K
SOE# ==> Auto Reboot Mode
1
GPI1
GPO0
R346
10K
0402
5%
SUSST1# 7
GPI19
ISA_SOE#
+3V
2
AC3
AA3
+3V
G
SUSA#
SUSB#
SUSC#
GPI7
SMBCLK1
SMBDATA1
+3VS
1
AA2
AF2
AF1
AB2
AB3
AC2
PWROK_SB 3,7,20
SB_PWRBTN# 19
RSMRST# 19
WAKE_UP# 19
EXTSMI# 19
SCI# 19
MII_PWRDWN 16
WAKE_UP#
EXTSMI#
SCI#
GPI4
PME#
SUSST1#
SUSCLK
4.7K*8
GPI0
GPI1
GPI2
GPI3
GPI4
GPI5
GPI6
GPI7
GPI16
GPI17
GPI18
GPI19
G
D
R301 1 0/NA5% 2 0402
1
PCOMPP
SDDRQ
SDDACK#
SDIOR#/SHDMARDY/SHSTROBE
SDIOW#/SSTOP
SDRDY/SDDMARDY/SDSTROBE
SDCS1#
SDCS3#
SDA0
SDA1
SDA2
IRQ15
PWROK#
GND
B
2 0402
2
GPI1
GPO0
SA0/SDD0
SA1/SDD1
SA2/SDD2
SA3/SDD3
SA4/SDD4
SA5/SDD5
SA6/SDD6
SA7/SDD7
SA8/SDD8
SA9/SDD9
SA10/SDD10
SA11/SDD11
SA12/SDD12
SA13/SDD13
SA14/SDD14
SA15/SDD15
AE2
AF4
AD2
AD5
Y2
AA1
W3
AC1
W4
Y3
AB1
D
S
SUSA#/GPO1
SUSB#/GPO2
SUSC#
SMBALRT#/GPI7
SMBCK1
SMBDT1
PVREF
SCOMPP
R312 1 4.7K
2
AC15
GPI7
AC97_SYNC 15,16,18
AC97_SDOUT 15,16,18
AC97_RST# 15,16,18
2
PDDREQ
PDDACK#
PDIOR#/PHDMARDY/PHSTROBE
PDIOW#/PSTOP
PDRDY/PDDMARDY/PDSTROBE
PDCS1#
PDCS3#
PDA0
PDA1
PDA2
IRQ14
SVREF
2 0402
1
SCOMPP
AD17
R332 1 4.7K
2
SVREF
GPI1
SMB_CLK0 4,5
2N7002
1
SDCS1#
SDCS3#
SDA0
SDA1
SDA2
AE15
AD22
AF22
AC21
AD15
AC23
AD23
AE23
AC22
AF23
AF24
2 0402
2
13 IDE_SDDREQ
13 IDE_SDDACK#
13 IDE_SDIOR#
13 IDE_SDIOW#
13 IDE_SIORDY
13 IDE_SDCS1#
13 IDE_SDCS3#
13 IDE_SDA0
13 IDE_SDA1
13 IDE_SDA2
13 IDE_IRQ15
Q35
2
C
AF15
AD16
AF16
AF17
AE17
AD18
AF18
AE18
AF19
AD19
AD20
AF20
AE20
AD21
AF21
AE21
R347 1 4.7K
+3VS
S
D
S
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
PWROK#
PWRGD
PWRBTN#
RSMRST#
RING#/GPI3
EXTSMI#/GPI2
PME#/GPI6
LID#/GPI4
BATLOW#/GPI5
SUSST1#/GPO3
SUSCLK/GPO4
L12
GND
L13
GND
L14
GND
L15
GND
L16
GND
L23
GND
L25
GND
M11
GND
M12
GND
M13
GND
M14
GND
M15
GND
M16
GND
N5
GND
N11
GND
N12
GND
N13
GND
N14
GND
N15
GND
N16
GND
P11
GND
F6
GND
F11
GND
AB25
GND
AB22
GND
IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15
GPI0
+3V
IDE_SDD[0..15]
13,17 IDE_SDD[0..15]
2 0402
2 0402
2 0402
D
1
W23
SMBCLK1
AC97_BITCLK 15,16,18
AC97_SDIN 18
MDC_SDIN 15,16
+VCC_RTC
R329
10K
0402
5%
2
W22
PCOMPP
ACSDIN2
ACSDIN3
R304 1 22
R305 1 22
R300 1 22
1
+3V
R1
PVREF
U20B
T3
T2
U3
U2
V1
T1
U1
R3
ACBITCLK
ACSDIN0
ACSDIN1
ACSDIN2/GPI20/GPO20
ACSDIN3/GPI21/GPO20
ACSYNC
ACSDO
ACRST#
1
Y22
W26
Y24
Y25
Y26
V24
W24
Y23
V25
V26
AE24
13 IDE_PDDREQ
13 IDE_PDDACK#
13 IDE_PDIOR#
13 IDE_PDIOW#
13 IDE_PIORDY
13 IDE_PDCS1#
13 IDE_PDCS3#
13 IDE_PDA0
13 IDE_PDA1
13 IDE_PDA2
13 IDE_IRQ14
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
R324
10K
0402
5%
2
D
AA24
AA25
AB24
AC26
AC24
AD25
AE26
AF25
AF26
AD24
AD26
AC25
AB23
AB26
AA26
AA22
+3V
2
AA4
AB4
AC4
AC5
IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
VSUS33
VSUS33
VSUS33
VSUS33
IDE_PDD[0..15]
13 IDE_PDD[0..15]
SB VIA_VT8235CD (2/3)
+2.5V
F14
F10
F9
F15
H5
J5
J21
K5
K21
T5
T21
U5
U21
U22
V5
AB8
AB9
AB16
AB17
+3VS
2
+3VS
1
4
1
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
9
of
26
4
3
SB_VLREF
J23
SB_VCOMPP
K23
L24
5 SB_VCLK
15,19
15,19
15,19
15,19
C
LAD0
LAD1
LAD2
LAD3
LAD0
LAD1
LAD2
LAD3
15 LDRQ0#
15,19 LFRAME#
14,15,19 SERIRQ
18 SB_SPKR
5 14M_SB_IOSC
+VCC_RTC
1
2
AF8
AE8
AD8
AF7
LREQ
AD7
LFRAME#
AE7
SERIRQ
AE10
SPKR
AE9
AC12
AE4
AE1
AD1
GPIO27
GPIO26
C354
1U
0402
+80-20%
10V
D26
K25
J24
H24
H26
G25
G26
GPI18
GPI17
INTRUDER#
19 SB_THRM#
12 LCD_ID0
Y4
Y1
AD3
VBE0#
VBE1#
MTXENA
MTXD0
MTXD1
MTXD2
MTXD3
MTXCLK
VPAR
UPCMD
DNCMD
UPSTB
UPSTB#
DNSTB
DNSTB#
MRXERR
MRXCLK
MRXDV
MRXD0
MRXD1
MRXD2
MRXD3
VLREF
VCOMPP
VCLK
LAD0
LAD1
LAD2
LAD3
EECS#
EEDO
EEDI
EECK
LFRAME#
SERIRQ
RAMVCC
SPKR
OSC
VBAT
SMBCK2/GPI27/GPO27
SMBDT2/GPI26/GPO26
AOLGPI/GPI18/THRM#
CPUMISS/GPI17
INTRUDER#/GPI16
RAMGND
PLLVCC
PLLGND
GND
R95
7 AGP_8X#
1 0/NA
2 0402
U24
T22
V23
U23
WSC/APICREQ#
APICD0/APICCS/GPI28/GPO28
APICD1/APICACK/GPI29/GPO29
APICCLK
RTCX1
RTCX2
R14
GND
R15
GND
R16
GND
T11
GND
T12
GND
T13
GND
T14
GND
T15
GND
T16
GND
V4
GND
V21
GND
V22
GND
W21
GND
W25
GND
AA5
GND
AA23
GND
AB5
GND
AB12
GND
AB13
GND
AB18
GND
AB19
GND
AE25
GND
AE22
GND
AE19
GND
AE16
GND
AC20
GND
AC17
GND
AC16
GND
P12
GND
P13
GND
P14
GND
P15
GND
P16
GND
R4
GND
R13
GND
R11
GND
R12
GND
5 14M_SB_APICCLK
SB_WSC
SB_APICD0
SB_APICD1
SB_APICCLK
SB_A20M#
SB_FERR#
SB_IGNNE#
SB_INIT#
SB_INTR
SB_NMI
SB_SLP#
SB_SMI#
SB_STPCLK#
R479
LAN_CRS 16
LAN_COL 16
R59 2 22 04021 5% LAN_MTXE
LAN_MTXE 16
RP52 5 22*4
1 0804
LAN_MTXD0 16
6
2
LAN_MTXD1 16
7
3
LAN_MTXD2 16
8
4
LAN_MTXD3 16
MTXC
B12
C12
A11
B11
C11
A12
A10
B10
C10
E10
D10
D9
A9
LAN_MRXER 16
MRXC
LAN_MRXDV
LAN_MRXD0
LAN_MRXD1
LAN_MRXD2
LAN_MRXD3
C9
B9
R93
R92
1 22
1 22
A13
A14
B14
C14
EECS
EEDO
EEDI
EESK
E7
SB_RAMVCC
E8
SB_RAMGND
16
16
16
16
16
SB_WSC
R309 1 1K
2 0402
SB_APICD1
R316 1 330
2 0402
SB_APICD0
R308 1 4.7K
2 0402
SB_SLP#
5% 2 0402
5% 2 0402
LAN_DCLK 16
LAN_DATAIO 16
SB_PLLGND
AD4
AF3
RTCX1
RTCX2
U22B
2
4
6
22
0402
5%
SB_APICCLK
R310 1 10K
2 0402
R306 1 10K
2 0402
SB_AGPBZ#
R276 1 10K
2 0402
SERIRQ
R357 1 4.7K
2 0402
SB_A20M#
SB_IGNNE#
SB_INIT#
SB_INTR
RP72 1 470*4
2
3
4
5 0804
6
7
8
SB_NMI
SB_SMI#
SB_STPCLK#
RP73 1 470*4
2
3
4
5 0804
6
7
8
C406
220P
0402
10%
50V
GND
SB_SLP#
R318 1 1K
2 0402
SB_FERR#
R307 1 1K/NA
2 0402
LDTSTOP# 2,6
74HCT08_V
TSSOP14
GND
+3V
R436
10K
0402
SPKR
R349
10K/NA
0402
C
GND
+3VS
SB_PLLVCC
P23
1
5
SB_GHI#
GPIO27
GPIO26
GPI18
GPI17
P22
14
+3V
B13
C13
D
+2.5V
2 0402
7
T25
U26
T26
R25
T23
R23
U25
T24
R26
R3301 4.7K
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
MDCK
MDIO
LREQ
+VCC_RTC
INTRUDER#
1
D11
D12
E11
E12
MIIVCC
MIIVCC
MIIVCC
MIIVCC
MIISUS25
MIISUS25
MCRS
MCOL
SB_GHI#
SB_VIDSEL
SB_VRDSLP
SB_AGPBZ#
2
SB_VPAR
VPAR
UPCMD
DNCMD
UPSTB
UPSTB#
DNSTB
DNSTB#
A20M#
FERR#
IGNNE#
INIT#
INTR
NMI
SLP#/GPO7
SMI#
STPCLK#
U20C
R24
P25
P24
A8
P26
1
1
TP7
7
7
7
7
7
7
7
GHI#/GPIO22
VIDSEL
VRDSLP
AGPBZ#
DPSLP#/GPIO23
1
F24
L26
VD0
VD1
VD2
VD3
VD4
VD5
VD6
VD7
VD8
VD9
VD10
VD11
VD12
VD13
VD14
VD15
+3VS
2
7 VBE#
F25
F26
J26
J25
E26
E24
K24
K26
D25
F23
G23
G22
H22
G24
J22
K22
D13
E13
F22
G21
H21
L21
L22
M21
M22
M23
M24
M25
M26
N21
N22
N23
N24
N25
N26
VAD0
VAD1
VAD2
VAD3
VAD4
VAD5
VAD6
VAD7
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VAD[0..7]
7 VAD[0..7]
D
+2.5VS
1
SB VIA_VT8235CD (3/3)
是否能改為+2.5VS_DDR
+2.5V
2
2
5
RP60
1
2
3
4
5
10
9
8
7
6
10K*8
1206
SB_VIDSEL
R443 1 10K
2 0402
SB_VRDSLP
R444 1 10K
2 0402
SB_VCOMPP
R445 1 360 1% 2 0402
LAN_MTXE
R56
1 10K
2 0402
+3V
LAD0
LAD1
LAD2
LAD3
VT8235
BGA451_36_1MM
GND
RP66
1
2
3
4
5
10
9
8
7
6
10K*8
LREQ
LFRAME#
+2.5V
SB_VPAR
R290 1 8.2K
2 0402
1206
GND
B
+3VS
+3V
B
MTXC
R284 0 1
2 0402
LAN_MTXC 16
MRXC
R283 0 1
2 0402
LAN_MRXC 16
D17
R368 1 1K 5% 2 0402 1
1
2
GND
+3V
3
1
2
1.25MM/ST/MA-2
ACES
85205-0200
BAT54C
GND
+SVDD3
C358
1U
0402
+80-20%
10V
1
1
J20
C332
10U
0805
10V
+80-20%
Sec soure 291000010209
+2.5V
R448
3K
0402
1%
R3451 10M
SB_PLLGND
1
1
R450
402
0402
1%
2
C331
10U
0805
10V
+80-20%
2 0402
RTCX2
C356
18P
0603
25V
10%
4
32.768KHZ
C355
18P
0603
25V
10%
2
1
C379
0.1U
0402
+80-20%
120Z/100M
50V
L80 1
2 2012
C308
1U
0402
+80-20%
6.3V
A
2 2012
2
1
C177
10U
0805
10V
+80-20%
2
2
1
L79 1
NM93C46
SO8
1
120Z/100M
SB_PLLVCC
VCC
NC1
NC0
GND
X5
SB_VLREF
+2.5V
A
+3V
8
7
6
5
GND
RTCX1
2
GND
1
1
C324
0.1U
0402
+80-20%
120Z/100M
50V
L64 1
2 2012
2
1
2 2012
2
SB_RAMGND
2
2
1
L66 1
C323
10U
0805
10V
+80-20%
EECS
EESK
EEDI
EEDO
R272
4.7K/NA
0402
5%
U15
1
CS
2
SK
3
DI
4
DO
1
+2.5V
120Z/100M
SB_RAMVCC
2
GND
1
GND
C376
0.1U
0402
+80-20%
50V
2
GND
C347
10U
0805
10V
+80-20%
2
2
C320
0.1U
0402
+80-20%
50V
2
1
1
2
2
1
+VCC_RTC
C326
10U
0805
10V
+80-20%
GND
GND
GND
Title
GND
<Title>
Size
C
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
10
of
26
5
4
3
2
1
TV Encoder(VIA_VT1622)
U3
21
20
TV_COMP
TV_CRMA
TV_LUMA
10
12
14
16
VSS_0
VSS_1
VSS_2
DACA
DACB
DACC
DACD
GND_0
GND_1
GND_2
GND_3
TVD13
R113 1 10K
2 0402
TVD14
R94
1 10K
2 0402
TVD15
R89
1 10K
2 0402
COMP
C396
27P
0402
5%
1
1
TV_ADDR
R80
10K
0402
5%
R83
10K
0402
5%
GND
GND
TV_VDD
GND
18
32
48
59
63
4
8
11
15
TV_BCO
C64 1
+/-10%
C70 1
+/-10%
C66 1
+/-10%
TV_CSO
GND_TVIC
TV_VSO
24
39
56
2 10P
0402
2 10P/NA
0402
2 10P
0402
+3V
+3V_TV
L30 1
GND
17
33
49
62
1
GND
TV_VDDA2
C52 1
+80-20%
6
2 2012
120Z/100M
2 0.1U
0402
R57
0
1
2 0603
C69
10U
0805
10V
+80-20%
1608
C47
270P
0402
+/-10%
50V
2
C48
270P
0402
+/-10%
50V
C46
270P
0402
+/-10%
50V
1
GND_TVIC
RP4
75*4
1206
+2.5V
TV_VDDA2
L29 1
2 2012
120Z/100M
5
6
7
8
JP_BEAD_DFS
8
7
6
5
2
GND
RP2
1
2
3
4
C59
0.01U
0402
+80-20%
50V
C53
10U
0805
10V
+80-20%
1
2
GND_TV
B
C62
0.1U
0402
+80-20%
50V
C55
0.1U
0402
+80-20%
50V
2
1
2
L1
1
C57
10U
0805
10V
+80-20%
TV_COMP
2
1
C5
270P
0402
+/-10%
50V
2
1
1
2
C6
270P
0402
+/-10%
50V
2
TV_CRMA
GND1
GND2
C7
270P
0402
+/-10%
50V
2 2012
120Z/100M
1
2.7uH
1
TV_VDDA1
L27 1
TV_LUMA
1608
2
L10
+2.5V
2
1
GND
2
1608
2
2.7uH
C
GND
1
2.7uH
1
L11
C68
0.01U
0402
+80-20%
50V
4
3
2
1
L9
C67
0.1U
0402
+80-20%
50V
1
1
2
3
4
5
6
7
D
2
2
R84
10K/NA
0402
5%
TV_CONF_XLT
2
NC0
NC1
1
2 0402
1
R112 1 10K
R75
10K/NA
0402
5%
1
3
BAV99/NA
3
3
D8
GND_TV
BAV99/NA
J1
2
GND
TVD12
GND_TVIC
S-VIDEO
7P/RA
SUYIN
33007S-07T1-C
SBD
SBC
2
GND_TV
BAV99/NA
GND1
GND2
GNDA1
GNDA2
GNDA3
GNDA4
GNDA4_1
1
D9
1
2
D10
1
1
BEAD_600Z/100M/NA
0603D
GND_TV
1
2
3
4
5
6
7
DS
TE
CSO/HSO
VSO
GND
2 0402
VT1622
PQFP64_0.5MM
2
L8
C
2
+3V
2
P_OUT
BCO
+3V_TV
26
40
57
2
14.318MHZ
274011431414
2 0402
1 10K
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
28
52
1
VDD_0
VDD_1
VDD_2
VDD_3
1
C395
27P
0402
5%
1 10K
R79
2
5% 2 0402
5% 2 0402
R1191 0
R38 1 0
7 I2C_DATA
7 I2C_CLK
XCLK
X6
TV_VDDA2
R82
TV_TE
1
29
54
58
60
HSYNC
VSYNC
2 0402
5%
TV_DS
2
TV_DS
TV_TE
TV_CSO
TV_VSO
7 TV_DS
VCC_0
VCC_1
VCC_2
TV_VDDA1
64
1
5
9
13
2 1% 0402
1
TV_BCO
VDDA1
VDDA2
VDDA3
VDDA4
VDDA4_1
R419 1 1M/NA
3
1 4.64K
2
7 TVCLKI
27
61
XO/FIN
TV_PCIRST# 7,8,19
TV_RSET
2
TV_RSET R55
1
25
XI
19
7
2
23
22
7 TVCLK
RESETN
RSET
+3V
TV_CONF_XLT
TV_ADDR
55
53
2
7 TVHS
7 TVVS
CONF_XLT
ADDR
1
TVD12
TVD13
TVD14
TVD15
+3V
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
2
30
31
34
35
36
37
38
41
42
43
44
45
46
47
50
51
1
D
TVD0
TVD1
TVD2
TVD3
TVD4
TVD5
TVD6
TVD7
TVD8
TVD9
TVD10
TVD11
2
7
7
7
7
7
7
7
7
7
7
7
7
C56
0.01U
0402
+80-20%
50V
B
GND
CRT_BLUE
7 CRT_BLUE
G
+3V
CRT_DDDA
+5V
Q5
D R420 1 33
S
D
S
7 CRT_DDDA
2 0402
5%
HSYNC_CON
VSYNC_CON
+2.5V
W/S=12/12/12/12/12 mils
TV_VDD
L99 1
J2
Close to VGA Connector
2 2012
120Z/100M
1
2 L14 120Z/100M
1608
1608
1608
1608
1608
120Z/100M
120Z/100M
120Z/100M
120Z/100M
1
1
1
1
1
9
2
10
3
11
4
12
5
13
6
14
7
15
8
2 L15
2 L17
2 L16
2 L18
C397
10U
0805
10V
+80-20%
1
1608
C398
0.1U
0402
+80-20%
50V
2
1608
2 L13 120Z/100M
1
2 L12 120Z/100M
1
2
1
1
16
C399
0.01U
0402
+80-20%
50V
GND
3
2 0603
CP2
22P*4
1206
1
5
5
6
7
8
U39
74HCT1G126
SC70_5
17
+3V
CP1
22P*4
1206
L100600Z/100M/NA
1
2 1608
R13
10K
0402
5%
L501 600Z/100M/NA
1
2 1608
1
R422 1 51
4
2
CRT_IN#
CRT_IN# 9
2 0603
GND_CRT15 GND_CRT15
GND_CRT15
1
U40
74HCT1G126
SC70_5
+3V
G
2
2
3
7 CRT_VSYNC
Q6
C1
100P
0402
10%
50V
A
R12
2
GND
VGA
SUYIN
7535S-15G2T-05
CONN_SYN7535S_15GT
331720015071
1
+5V
A
R421 1 51
4
5
6
7
8
2
7 CRT_HSYNC
4
3
2
1
4
3
2
1
1
5
2N7002
C410
22P
0402
+/-10%
50V
2
CRT_GREEN
7 CRT_GREEN
C411
22P
0402
+/-10%
50V
2
1
2
C412
22P
0402
+/-10%
50V
GND_TVIC
External VGA Connector
2
CRT_RED
7 CRT_RED
2
R69
2.2K
0402
5%
2
R68
2.2K
0402
5%
GND
1
1
1
75*4
1206
1
GND
+3V
GND_CRT15
1K
0402
1%
Title
<Title>
GND
CRT_DDCK
D
S
7 CRT_DDCK
D R423 1 33
S
2 0402
5%
Size
C
GND_CRT15
2N7002
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
11
of
26
5
4
3
2
LVDS Encoder(VIA_VT1634)
1
+2.5V
LVDSVCC
L42 1
2 2012
LVDS_VREF
78
9
11
52
69
71
77
80
96
GND
14
15
17
C
PLLGND
25
35
43
51
DVDD
LVDSGND
53
70
79
95
LVDSVCC
30
40
48
RESERVED_2
RESERVED_3
VREF
RESERVED_4
RESERVED_5
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND
+2.5V
41
42
26
27
RESERVED_8
RESERVED_9
A3+
A3-
GNDPLL_0
GNDPLL_1
GNDPLL_2
A2+
A2-
GNDLVDS_0
GNDLVDS_1
GNDLVDS_2
GNDLVDS_3
A1+
A1A0+
A0-
VCC_0
VCC_1
VCC_2
VCC_3
I2CVCC
VCCPLL_0
VCCPLL_1
VCCLVDS_0
VCCLVDS_1
VCCLVDS_2
MODSEL
TXCLK+
TXCLK-
I2CVCC
L44 1
2 2012
120Z/100M
28
29
C415
0.1U
0402
+80-20%
+2.5V
31
32
33
34
LV_A0
LV_A1
LV_A2
LV_TST1
36
37
LV_PD#
R141 1 4.7K
2 0402
LV_INTR
R142 1 4.7K
2 0402
LV_I2SEL
R196 1 4.7K/NA 2 0402
LV_RES1
R144 1 4.7K
RP13 4
3
2
1
0*4
8 0804
7
6
5
38
39
44
45
TXOUT2+
TXOUT2-
46
47
TXOUT1+
TXOUT1-
49
50
TXOUT0+
TXOUT0-
2 0402
GND
PLLVCC
2 2012
120Z/100M
C416
0.1U
0402
+80-20%
R415 1 4.7K
2 0402
LV_DUAL
R140 1 4.7K
2 0402
LV_EDGE
R143 1 4.7K
2 0402
PLLGND
+2.5V
67
R197 1 4.7K
2 0402
GND
40 mils
L37
2
7 ENPBLT
1
8 ENBL_SB
3
BAW56
DVMAIN
LCD_ID0
LCD_ID1
LCD_ID2
R124
0603D
1
2 BEAD_600Z/100M
R122 1 0/NA
2 0603
1
2
120Z/100M
1608
GND
1
L25
2
120Z/100M
GND1
GND2
C19
0.1U
0402
+80-20%
16V
GND
GND
GND
GND
GND
2
C20
10U/NA
1206
10V
1
1
1
GND
C22
1000P
0402
10%
50V
C43
0.1U
0402
16V
1
2
0
0603
GND
PLLGND
B
+3V
CLOSE TO AO3400
D
R32
1
BLADJ 19
PWR_VDDIN
2
470K 0402
Q1
R1
2
C44
0.1U
0402
+80-20%
16V
+1.5V
GND
DTC144TKA
GND
2
GND
C21
0.1U
0402
+80-20%
16V
1608
2
MA/15PX2/ST
ACES
87216-3002
1
2
A
C424
0.1U
0402
+80-20%
50V
RP3
1K*4
1206
C42
1000P
0402
10%
50V
2
+3V
1
1
8
7
6
5
1
L6
TXOUT0+
TXOUT0-
1
2
3
4
LVDSGND
L36
C315
0.1U
0402
+80-20%
50V
1
19 ENBL_KBC
2
D1
TXOUT1+
TXOUT1-
0603
Close to LCD Connector
TXCLK+
TXCLK-
2
R433
10K
0603
S
2
1
TXOUT2+
TXOUT2-
LCDVCC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
LCD Panel ID
1
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
0
Q2
AO3400
SOT23_FET
D
S
+3V
40 mils
LCD 14" 330mA,15"800mA
1
GND
1
J8
C112
0.01U
0402
+80-20%
50V
GND
LV_I2SEL
2
LCD Connector+Inverter
C113
0.1U
0402
+80-20%
50V
PLLVCC
2
5
6
7
8
10K*4
1206
C
C105
10U
0805
10V
+80-20%
G
RP1
C179
0.01U
0402
+80-20%
50V
I2CVCC
68
10
16
3
4
3
2
1
B
C176
0.1U
0402
+80-20%
50V
+2.5V
DUAL (pin23)
Remove R10
For one channel panel Low
Install R8
Remove R8
For two channel panel High Install R10
LCD_ID0
LCD_ID1
LCD_ID2
C184
10U
0805
10V
+80-20%
GND
L35 1
VT1634
PQFP100_0.5MM
10 LCD_ID0
9 LCD_ID1
8 LCD_ID2
C175
0.01U
0402
+80-20%
50V
GND
LV_EDGE
LV_PD#
LV_DUAL
LV_INTR
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
RESERVED_6
RESERVED_7
1
LVDS_D20
LVDS_D21
LVDS_D22
LVDS_D23
2
8 0804
7
6
5
1
4 22*4
3
2
1
RP9
CLK1+
CLK1RESERVED_0
RESERVED_1
D20
D21
D22
D23
2
NB_FPD20
NB_FPD21
NB_FPD22
NB_FPD23
100
99
98
97
C178
0.1U
0402
+80-20%
50V
1
7
7
7
7
LVDS_D20
LVDS_D21
LVDS_D22
LVDS_D23
GND
VREF near pin 78
C183
10U
0805
10V
+80-20%
2
LVDS_D16
LVDS_D17
LVDS_D18
LVDS_D19
LV_TST1
I2C_CLK_LVDS 7
I2C_DATA_LVDS 7
1
8 0804
7
6
5
D15
D16
D17
D18
D19
72
73
18
22
23
21
5% 2 0402
5% 2 0402
2
4 22*4
3
2
1
RP8
TST1
TST2
EDGE
PD#
DUAL
INTR
1
NB_FPD16
NB_FPD17
NB_FPD18
NB_FPD19
5
4
3
2
1
2
7
7
7
7
LVDS_D15
LVDS_D16
LVDS_D17
LVDS_D18
LVDS_D19
C414
0.1U
0402
+80-20%
1
LVDS_D12
LVDS_D13
LVDS_D14
LVDS_D15
LV_I2SEL
R41 1 0
R1291 0
2
8 0804
7
6
5
61
59
60
1
4 22*4
3
2
1
I2CSEL
I2CCLK
DSEL/I2CDAT
2
RP7
D10
D11
D12
D13
D14
LV_A0
LV_A1
LV_A2
2 2012
120Z/100M
1
NB_FPD12
NB_FPD13
NB_FPD14
NB_FPD15
82
81
8
7
6
63
64
65
D
DVDD
L46 1
2
7
7
7
7
LVDS_D10
LVDS_D11
LVDS_D12
LVDS_D13
LVDS_D14
2
LVDS_D8
LVDS_D9
LVDS_D10
LVDS_D11
LVDSGND
+2.5V
R190
10K
0402
5%
1
8 0804
7
6
5
A0
A1
A2
C154
0.01U
0402
+80-20%
50V
GND
2
RP12 4 22*4
3
2
1
D5
D6
D7
D8
D9
C155
0.1U
0402
+80-20%
50V
LVDS_VREF
1
NB_FPD08
NB_FPD09
NB_FPD10
NB_FPD11
89
86
85
84
83
GND
58
57
56
55
2
7
7
7
7
LVDS_D5
LVDS_D6
LVDS_D7
LVDS_D8
LVDS_D9
GPIO1-1
GPIO1-2
GPIO2-1
GPIO2-2
1
LVDS_D4
LVDS_D5
LVDS_D6
LVDS_D7
D0
D1
D2
D3
D4
2
NB_FPD04
NB_FPD05
NB_FPD06
NB_FPD07
8 0804
7
6
5
94
93
92
91
90
2
7
7
7
7
RP11 4 22*4
3
2
1
LVDS_D0
LVDS_D1
LVDS_D2
LVDS_D3
LVDS_D4
R188
10K
0402
5%
C158
10U
0805
10V
+80-20%
1
LVDS_D0
LVDS_D1
LVDS_D2
LVDS_D3
C413
0.1U
0402
+80-20%
LV_RES1
2
8 0804
7
6
5
12
13
19
20
24
54
62
66
1
RP10 4 22*4
3
2
1
+1.5V
RESERVED1
RESERVED2_0
RESERVED2_1
RESERVED2_2
RESERVED2_3
RESERVED2_4
RESERVED2_5
RESERVED2_6
DE
CLKIN+
CLKINHSYNC
VSYNC
2
NB_FPD00
NB_FPD01
NB_FPD02
NB_FPD03
76
87
88
75
74
1
7
7
7
7
LVDS_DE
LVDS_CLKIN+
LVDS_CLKINLVDS_HSYNC
LVDS_VSYNC
2
LVDS_CLKIN+
LVDS_CLKINLVDS_HSYNC
LVDS_VSYNC
1
5% 2 0402
5% 2 0402
5% 2 0402
5% 2 0402
2
LVDS_DE
R182 1 22
R179 1 22
R199 1 22
R198 1 22
1
5% 2 0402
NB_FPCLK+
NB_FPCLKNB_FPHS
NB_FPVS
2
D
R193 1 22
7
7
7
7
1
U9
7 NB_FPDE
1
120Z/100M
LCDID2
0
0
0
0
1
1
1
1
LCDID1
0
0
1
1
0
0
1
1
LCDID0
PANEL
0
1
0
1
0
1
0
1
X
HSD150PX14-A
HT15X34-100
LPN150XB-L03
B150XG02-1
QD15XL06-01-2
LP150X08-A3
X
R102 1 0
2 0402
R106 1 0/NA
2 0402
VENDOR
ENAVDD
ENAVDD 7
ENAVEE 7
A
XGA
XGA
XGA
XGA
XGA
XGA
Hannstar
Hydis
Samsung
AU
QDI
Lg-Phillips
Layout Note:
S/W/W/S=10/8/8/10 mils
as short as possible
Title
四組各自平行走線等長
Size
C
<Title>
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
12
of
26
5
4
3
2
1
HDD & CD_ROM Conntor
IDE_PDD[0..15]
5
6
7
8
+5V
R425 1
GND
R2261 10K
HDD_PDDREQ
2
0 5% 2 0402
HDD_LED#
1
CL-190G
K
A D507
0 5% 2 0402
CL-190G
K
A D506
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
C251
0.1U
0402
+80-20%
16V
2
19 NUM#
19 CAP#
19 AC_POWER#
GND
1
2
2
2
2
1
1
1
1
1
R427
0/NA
0402
5%
1
19 SCROLL#
C254
0.1U
0402
+80-20%
16V
GND
GND
R227
330
0402
5%
3
Close to IDE Connector
2 0402
R228
330
0402
5%
D13
CDROM_LED#
1
2 0402
R225
330
0402
5%
GND
2
2 0402
R154
330
0402
5%
BAW56/NA
2
HDD_PIORDY
R402
330
0402
5%
2
HDD_PDA2
HDD_PDCS3#
1
R3251 10K
R320 1 4.7K
HDD_IRQ14
R340
330
0402
5%
5%
+5V
C
R335
330
0402
5%
R229
1
470 0402
FM/22PX2/2MM
ALLTOP
C17834-144XX
+3V
R337
330
0402
5%
2
R338
330
0402
5%
GND
R426 1
0804
+VDD3
+3V
2
RP58 1 0*4
2
3
4
+3VS
R356
5.6K
0402
5%
1
9 IDE_PDIOR#
9 IDE_PDA1
9 IDE_PIORDY
HDD_PDDREQ
HDD_PDIOW#
HDD_PDIOR#
HDD_PIORDY
HDD_PDDACK#
HDD_IRQ14
HDD_PDA1
HDD_PDA0
HDD_PDCS1#
HDD_LED#
HDD_PDD8
HDD_PDD9
HDD_PDD10
HDD_PDD11
HDD_PDD12
HDD_PDD13
HDD_PDD14
HDD_PDD15
2
16
15
14
13
12
11
10
9
GND0
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
KEY
GND3
GND4
GND5
CSEL
GND6
IOCS16#
PDIAG#
DA2
CS#1
GND7
AVCC
RSV
1
9 IDE_PDCS1#
9 IDE_PDCS3#
9 IDE_PDA2
9 IDE_PDDACK#
9 IDE_PDDREQ
9 IDE_PDIOW#
9 IDE_IRQ14
9 IDE_PDA0
RP59 1 0*8
2
3
4
5
6
7
8
RESET#
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
GND1
DMARQ
DIOW#
DIOR#
IORDY
DMACK#
INTRQ
DA1
DA0
CS#0
DASP#
DVDD
GND2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
2
16
15
14
13
12
11
10
9
D
HDD_PDD7
J14
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
1
1 0*8
2
3
4
5
6
7
8
Sec soure 331030044023
IDERST#
HDD_PDD7
HDD_PDD6
HDD_PDD5
HDD_PDD4
HDD_PDD3
HDD_PDD2
HDD_PDD1
HDD_PDD0
2
IDE_PDD8 RP62
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
HDD_PDD0
HDD_PDD1
HDD_PDD2
HDD_PDD3
HDD_PDD4
HDD_PDD5
HDD_PDD6
HDD_PDD7
RPX8
HDD_PDD8
HDD_PDD9
HDD_PDD10
HDD_PDD11
HDD_PDD12
HDD_PDD13
HDD_PDD14
HDD_PDD15
RPX8
HDD_PDCS1#
HDD_PDCS3#
HDD_PDA2
HDD_PDDACK#
HDD_PDDREQ
HDD_PDIOW#
HDD_IRQ14
HDD_PDA0
RPX8
HDD_PDIOR#
HDD_PDA1
HDD_PIORDY
1
16
15
14
13
12
11
10
9
2
IDE_PDD0 RP61 1 0*8
IDE_PDD1
2
IDE_PDD2
3
IDE_PDD3
4
IDE_PDD4
5
IDE_PDD5
6
IDE_PDD6
7
IDE_PDD7
8
D
Primary EIDE
Connector
9 IDE_PDD[0..15]
GND
19 BATT_POWER#
CL-190G
K
A D503
CL-190G
K
A D505
CL-190G
K
A D504
CL-190G
K
A D501
CL-190G
K
C
A D502
D510
SR
19 BATT_R#
2
1
19 BATT_G#
4
3
VG
19-22SRVGC/TR8
5
6
7
8
CABLE_SEL
1
0804
CD_IRQ15
R384 1 10K
2 0402
CD_SIORDY
R398 1 4.7K
2 0402
R385 1 10K
GND7
GND8
CD_SDD8
CD_SDD9
CD_SDD10
CD_SDD11
CD_SDD12
CD_SDD13
CD_SDD14
CD_SDD15
19 T_CLK
19 T_DATA
CD_SDCS3#
Close to IDE Connector
C314
0.1U
0402
+80-20%
16V
C313
0.1U
0402
+80-20%
16V
1
1
2
2
1
B
L69 120Z/100M 1608
T_CLK
1
2
L67 120Z/100M 1608
T_DATA 1
2
2
4
5
SW_LEFT
+5V
Sec soure 291000150607
GND
Sec soure 297040100027
CD_SDDREQ
CD_SDIOR#
CD_SDDACK#
CD_SDA2
C341
0.1U
0402
+80-20%
16V
TC010-PSS11CET
297040105010
SW_TC010-PS11CET
T-MEC(台灣美琪)
SW_RIGHT
TC010-PSS11CET
297040105010
SW_TC010-PS11CET
T-MEC(台灣美琪)
J18
1
2
3
4
5
6
1
3
SW504
2
4
5
FPC/FFC/0.5MM/6P
ACES
20096-0600
1
3
SW503
D15
J19
1
2
3
4
5
6
7
8
9
10
11
12
D16
GND
GND
K211-A503-507
MA/0.8MM/R A
SPEED
GND
ESD0805A/NA
ESD0805A/NA
GND
Sec soure 297040100027
GND
CD_SDDREQ
GND1
GND2
R323
470/NA
0402
5%
2
+3V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
2
RP69 1 0*4
2
3
4
CD_SDIOW#
CD_SIORDY
CD_IRQ15
CD_SDA1
CD_SDA0
CD_SDCS1#
CDROM_LED#
ROUT
NC
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
DIVARQ
DIOR#
GND3
DMACK#
IOCS16#
PDIAG#
DA2
CS#1
VCC2
VCC3
VCC4
GND4
GND5
GND6
RSV2
R430
0/NA
0603
K
9 IDE_IRQ15
9 IDE_SDIOR#
9 IDE_SIORDY
CD_SDD7
CD_SDD6
CD_SDD5
CD_SDD4
CD_SDD3
CD_SDD2
CD_SDD1
CD_SDD0
LOUT
AGND
RESET#
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
GND
DIOW#
IORDY
INTRQ
DA1
DA0
CS#0
DASP#
VCC0
VCC1
GND1
GND2
CSEL#
RSV
A
16
15
14
13
12
11
10
9
J21
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
K
9 IDE_SDA0
9 IDE_SDA2
9 IDE_SDCS1#
9 IDE_SDCS3#
9 IDE_SDA1
9 IDE_SDIOW#
9 IDE_SDDACK#
9 IDE_SDDREQ
RP70 1 0*8
2
3
4
5
6
7
8
B
CDROM_COM M 18
CDROM_LEFT 18
CDROM_RIGHT 18
A
16
15
14
13
12
11
10
9
W/S=10/10/10/10 mils
1
1 0*8
2
3
4
5
6
7
8
CDROM_COM M
CDROM_LEFT
CDROM_RIGHT
2
IDE_SDD8 RP63
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15
CD_SDD0
CD_SDD1
CD_SDD2
CD_SDD3
CD_SDD4
CD_SDD5
CD_SDD6
CD_SDD7
RPX8
CD_SDD8
CD_SDD9
CD_SDD10
CD_SDD11
CD_SDD12
CD_SDD13
CD_SDD14
CD_SDD15
RPX8
CD_SDA0
CD_SDA2
CD_SDCS1#
CD_SDCS3#
CD_SDA1
CD_SDIOW#
CD_SDDACK#
CD_SDDREQ
RPX8
CD_IRQ15
CD_SDIOR#
CD_SIORDY
1
16
15
14
13
12
11
10
9
2
IDE_SDD0 RP68 1 0*8
IDE_SDD1
2
IDE_SDD2
3
IDE_SDD3
4
IDE_SDD4
5
IDE_SDD5
6
IDE_SDD6
7
IDE_SDD7
8
+5VS
R429
0
0603
IDERST#
IDE_SDD[0..15]
Secondary EIDE Connector
9,17 IDE_SDD[0..15]
+5V
GND
GND
GND
2 0402
FPC/FFC/0.5MM/12P/NA
ACES 20096-1200
Sec soure 331000050005
GND
CD_SDD7
A
1
A
+5V
2
GND
2
2
1
2
R331
10K
0402
5%
R1
R327
10K
0402
5%
8,14,15 IDE_PCIRST#
R328
5.6K
0402
5%
1
+3V
1
+3V
3
IDERST#
Title
<Title>
Q32
Size
C
DTC144TKA
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
13
of
26
5
4
3
AD20
PCI_INTB#
2
1
PCMCIA CONTROLLER & CARDBUS SCOKET
REQ0#/GNT0#
D
D
CARD_PCIRST#
SIGNAL
PC CARD PULL UP
VOLT
2 10K
0402
5%
9,15 CARD_PME#
R396 1
2 10K
0402
5%
CARD_PME#
59
70
62
CLKRUN#
69
68
67
65
64
61
60
18 CARDSPK#
9,15 CLKRUN#
PCI_LOCK#
SERIRQ
10,15,19 SERIRQ
IDSEL
PCI_CLK
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PERR#
SERR#
REQ#
GNT#
RST#
RI_OUT#/PME#
SUSPEND#
SPKR_OUT#
MF6
MF5
MF4
MF3
MF2
MF1
MF0
1
CC/BE3#
CC/BE2#
CC/BE1#
CC/BE0#
C
2 0402
2 0402
2
1
+VCCA
2
C372
108
111
110
109
107
105
101
104
133
123
106
132
103
136
119
143
84
100
131
117
75
137
134
135
CCLK
CFRAME#
CIRDY#
CTRDY#
CDEVSEL#
CSTOP#
CPAR
CPERR#
CSERR#
CREQ#
CGNT#
CINT#
CBLOCK#
CCLKRUN#
CRST#
R2_D2
R2_D14
R2_A18
CVS1
CVS2
CCD#1
CCD#2
CAUDIO
CSTSCHG
125
112
99
88
CCBE#3
CCBE#2
CCBE#1
CCBE#0
R394 1 10K
+VCCA
2 0402
+VPPA
C365
+VCCA
R401 1 10K
GND
0.1U
0402
GND 16V
CAD0
CAD1
CAD3
CAD5
CAD7
CCBE#0
CAD9
CAD11
CAD12
CAD14
CCBE#1
CPAR
CPERR#
CGNT#
CINT#
0.1U
0402
16V
+VCCA
R382
47K
0402
5%
2 0402
CCLK
CIRDY#
CCBE#2
CAD18
CAD20
CAD21
CAD22
CAD23
CAD24
CAD25
CAD26
CAD27
CAD29
R2_D2
CCLKRUN#
CBI1410
PQFP144_0.5MM
GND
+3V
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
CCD#1
CAD2
CAD4
CAD6
R2_D14
CAD8
CAD10
CVS1
CAD13
CAD15
CAD16
R2_A18
CBLOCK#
CSTOP#
CDEVSEL#
C378
270P
0402
+/-10%
50V
GND
+VPPA
CTRDY#
CFRAME#
CAD17
CAD19
CVS2
CRST#
CSERR#
CREQ#
CCBE#3
CAUDIO
CSTSCHG
CAD28
CAD30
CAD31
CCD#2
B
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
C357
270P
0402
+/-10%
50V
GND
FM/34PX2/1.27MM
ACECON
MF-291000000009
GND
1
GND
J502
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
73
74
71
72
63
14
66
86
102
122
138
CCLK
CFRAME#
CIRDY#
CTRDY#
CDEVSEL#
CSTOP#
CPAR
CPERR#
CSERR#
CREQ#
CGNT#
CINT#
CBLOCK#
CCLKRUN#
CRST#
R2_D2
R2_D14
R2_A18
CVS1
CVS2
CCD1#
CCD2#
CAUDIO
CSTSCHG
6
22
42
58
78
94
114
130
8 PCI_INTB#
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
+VCCA
R399 1 10K
R400 1 10K
2
13
21
32
28
29
31
33
36
34
35
1
2
20
PCI1410 HAVE INTEGRATED ALL PULL UP RES ABOVE
1
R397 1
+3V
1%
PCICLK_CARD
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_PAR
PCI_PERR#
PCI_SERR#
PCI_REQ0#
PCI_GNT0#
CARD_PCIRST#
0.1U
0402
16V
+3V
+3V
CARD_VCC
CARD_VCC
CARD_VCC
CARD_VCC
+3V
+3V
CARD_VCC
CARD_VCC
CARD_VCC
CARD_VCC
CARD_VCC
CARD_VCC
CARD_VCC
CARD_VCC
2
2 0402
GND
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
144
142
141
140
139
129
128
127
124
121
120
118
116
115
113
98
96
97
93
95
92
91
89
87
85
82
83
80
81
77
79
76
Card Bus Socket
1 100
C/BE3#
C/BE2#
C/BE1#
C/BE0#
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
90
126
1
+3V
B
R387
5 PCI_CARD_CLK
8,15 PCI_DEVSEL#
8,15 PCI_FRAME#
8,15 PCI_IRDY#
8,15 PCI_TRDY#
8,15 PCI_STOP#
8,15 PCI_PAR
8,15 PCI_PERR#
8,15 PCI_SERR#
8 PCI_REQ0#
8 PCI_GNT0#
8,13,15 CARD_PCIRST#
12
27
37
48
C368
SKT_VCC0
SKT_VCC1
2
PCI_AD20
PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0
+VCCA
U26
1
8,15
8,15
8,15
8,15
PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
CCD#1
CCD#2
CBLOCK#
CSTOP#
CDEVSEL#
CTRDY#
CVS1
CVS2
CRST#
CSERR#
CPERR#
CINT#
CIRDY#
CREQ#
CSTSCHG#
CAUDIO
2
C
3
4
5
7
8
9
10
11
15
16
17
19
23
24
25
26
38
39
40
41
43
45
46
47
49
51
52
53
54
55
56
57
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
AUX_VCC
PCI_AD[0..31]
8,15 PCI_AD[0..31]
VCCD0#/VCC5#/SDAT
VCCD1#/VCC3#/SCLK
VPPD0/VPP_PGM/SLAT
VPPD1/VPP_VCC
GND
CORE_VCC0
CORE_VCC1
CORE_VCC2
CORE_VCC3
CORE_VCC4
CORE_VCC5
18
30
44
50
C377
0.1U
0402
+80-20%
16V
PCI_VCC0
PCI_VCC1
PCI_VCC2
PCI_VCC3
1
C366
0.1U
0402
+80-20%
16V
VCCEN#0
VCCEN#1
VPPEN0
VPPEN1
2
1
C360
0.1U
0402
+80-20%
16V
2
1
C361
0.1U
0402
+80-20%
16V
2
2
1
+3V
R391
10K
0402
5%
VPPEN0
VPPEN1
hoder 331000000303
+VCCA
+VPPA
A
C363
4.7U/NA
1206
16V
Close to
TPS2211A
C370
1
1
GND
C364
0.1U
0402
16V
C374
0.1U
0402
16V
2
CP2211
0.1U
0402
16V
1
SSOP16
2
0.1U
0402
16V
C371
16
15
14
13
12
11
10
9
2
1
1
0.1U
0402
16V
C373
2
0.1U
0402
16V
C369
2
2
C367
2
1
1
Close to TPS2211
A
SHDN
VDDP0
VDDP1
AVCCA
AVCCB
AVCCC
AVPP
12V
1
+5V
VCCD0
VCCD1
3.3VA
3.3VB
5VA
5VB
GND
OC
2
+3V
1
2
3
4
5
6
7
8
2
U27
VCCEN#0
VCCEN#1
4.7U/NA
1206
16V
Title
<Title>
GND
Size
C
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
r00
<Doc>
星期四, 五月 20, 2004
1
Sheet
14
of
26
5
4
3
1
Mini-PCI & USB 2.0
1
+5V
2A
2
R339
330
0402
5%
MINI-PCI
AD21
PCI_INTD# \ INTC#
REQ2#/GNT2#
D508
Wireless LED
CL-190G
D
K
D
3
WIRE_LED#
Q10
R1
WIRE_LED
2
+3V
1
DTC144TKA
GND
8,14 PCI_AD[0..31]
PCI_AD[0..31]
J22
8 PCI_REQ1#
PCI_REQ2#
PCI_AD27
PCI_AD25
MINI_LPC_FRAME#
8,14 PCI_C/BE#3
PCI_C/BE#3
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
8,14 PCI_C/BE#2
8,14 PCI_IRDY#
9,14 CLKRUN#
8,14 PCI_SERR#
8,14 PCI_PERR#
8,14 PCI_C/BE#1
PCI_C/BE#2
PCI_IRDY#
CLKRUN#
PCI_SERR#
PCI_PERR#
PCI_C/BE#1
PCI_AD14
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
PCI_AD5
MINI_LPC_AD0
PCI_AD3
9,16,18 AC97_SYNC
9,16 MDC_SDIN
9,16,18 AC97_BITCLK
18 MINIPCI_SPKR#
Close to
MiniPCI
CONN.
AC97_SYNC
MDC_SDIN
AC97_BITCLK
PCI_AD1 +5V
R127 1
R128 1
2 22
2 22
MINIPCI_SPKR#
B
0402
0402
MINI_LPC_CLK
2
1
+5V
GND1
GND2
C89
0.1U
0402
+80-20%
16V
WIRE_LED
WIRE_LED#
+5V
PCI_INTD# 8
MINI_LPC_AD2
PCIRST#
PCI_GNT2#
PCI_GNT1# 8
MPCI_PME#
MINI_LPC_AD3
PCI_AD30
PCI_AD28
PCI_AD26
PCI_AD24
MPCI_PME# 9,14
R120
100
1
PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16
PCI_FRAME#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#
0402
2
5 LPC_48M
10 LDRQ0#
10,14,19 SERIRQ
10,19 LAD0
A
10,19 LAD1
10,19 LAD2
10,19 LAD3
LPC_48M
R255 1
0
2 0402
5%
MINI_LPC_CLK
LFRAME#
R472 1
0
2 0402
5%
MINI_LPC_FRAME#
LDRQ0#
R348 1
0
2 0402
5%
MINI_LPC_LDRQ#
PCI_SERIRQ R267 1
0
2 0402
5%
MINI_PCI_SERIRQ
LAD0
R269 1
0
2 0402
5%
MINI_LPC_AD0
LAD1
R476 1
0
2 0402
5%
MINI_LPC_AD1
LAD2
R268 1
0
2 0402
5%
MINI_LPC_AD2
LAD3
R478 1
0
2 0402
5%
MINI_LPC_AD3
C94
0.1U
0402
+80-20%
16V
C93
0.1U
0402
+80-20%
16V
GND
C
PCI_AD21
PCI_PAR 8,14
PCI_FRAME# 8,14
PCI_TRDY# 8,14
PCI_STOP# 8,14
PCI_DEVSEL# 8,14
PCI_AD9
PCI_C/BE#0
PCI_C/BE#0 8,14
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
MPCI_PD
+3V
AC97_SDOUT
AC97_RST#
MINI_PCI_SERIRQ
AC97_SDOUT 9,16,18
AC97_RST# 9,16,18
R117
10K
0402
5%
MPCIACT#
B
MPCIACT# 8
+3V
JS502
GND1
GND2
Sec soure 291000001206
C92
0.1U
0402
+80-20%
16V
PCI_AD15
PCI_AD13
PCI_AD11
1
2
SHORT-SMT4
124P/0.8MM/H9.2
TYCO
1566678-1
GND
10,19 LFRAME#
+3V
MINI_PCIRST# 8,13,14
2
GND
0402
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
PCI_AD31
PCI_AD29
C
R116 0/NA
1
CLK_MINIPCI
R115 0/NA 0402
1
2
1
2
2
5 MINI_PCI_CLK
MINI_LPC_AD1
1
MINI_LPC_LDRQ#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
2
PCI_INTC#
RING
TX+
TXPJ4
PJ5
LED2_YELP
LED2_YELN
RESERVED4
5V[1]
INTA#
RESERVED5
3.3VAUX[0]
RST#
3.3V[4]
GNT#
GROUND9
PME#
RESERVED6
AD[30]
3.3V[5]
AD[28]
AD[26]
AD[24]
IDSEL
GROUND10
AD[22]
AD[20]
PAR
AD[18]
AD[16]
GROUND11
FRAME#
TRDY#
STOP#
3.3V[6]
DEVSEL#
GROUND12
AD[15]
AD[13]
AD[11]
GROUND13
AD[9]
C/BE[0]#
3.3V[7]
AD[6]
AD[4]
AD[2]
AD[0]
RESERVED_WIP4[0]
RESERVED_WIP4[1]
GROUND14
M66EN
AC_SDATA_OUT
AC_CODEC_ID0#
AC_RESET#
RESERVED7
GROUND15
SYS_AUDIO_IN
SYS_AUDIO_IN_GND
AUDIO_GND2
MPCIACT#
3.3VAUX[1]
1
MPCI_PD
TIP
RX+
RXPJ7
PJ8
LED1_GRNP
LED1_GRNN
CHSGND
INTB#
3.3V[0]
RESERVED0
GROUND0
CLK
GROUND1
REQ#
3.3V[1]
AD[31]
AD[29]
GROUND2
AD[27]
AD[25]
RESERVED1
C/BE[3]#
AD[23]
GROUND3
AD[21]
AD[19]
GROUND4
AD[17]
C/BE[2]#
IRDY#
3.3V[2]
CLKRUN#
SERR#
GROUND5
PERR#
C/BE[1]#
AD[14]
GROUND6
AD[12]
AD[10]
GROUND7
AD[8]
AD[7]
3.3V[3]
AD[5]
RESERVED2
AD[3]
5V[0]
AD[1]
GROUND8
AC_SYNC
AC_SDATA_IN
AC_BIT_CLK
AC_CODEC_ID1#
MOD_AUDIO_MON
AUDIO_GND0
SYS_AUDIO_OUT
SYS_AUDIO_OUT_GND
AUDIO_GND1
RESERVED3
VCC5VA
2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
8 1206
7
6
5
1
0*4/NA
2
8 PCI_INTC#
LAD0 RP5 1
LAD1
2
LAD2
3
LAD3
4
1
9 MINIPCI_PD
LAD[0..3]
MINI-PCI TYPE III A
10,19 LAD[0..3]
C79
0.1U
0402
+80-20%
16V
PIN24, 124 ARE AUX_POWER
GND
GND
A
Title
<Title>
Size
C
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
15
of
26
5
4
3
+3VS_LAN
R35
1 0/NA
1 5.1K/NA 2 0402
1%
1 0/NA
1
18
7
41
25
36
32
C110
1U
0402
+80-20%
10V
+3VS
+3VS_LAN
2
1
3
1
2 0/NA
0402
R61
49.9
0402
1%
2
4.7P/NA
0603
MII_PWRDWN 9
C111
1U
0402
+80-20%
10V
R66
49.9
0402
1%
4
5
RD+
RDC
RD-
RX+
RXC
RX-
NC0
NC1
NC2
NC3
+3VS_LAN
+3VS_LAN_PLL
PJ4
PJ7
R48
75
0402
1%
R49
75
0402
1%
1
1
C409
0.1U
0402
10%
16V
R76 600Z/100M
1
2 1608
GND
R47
75
0402
1%
C74
1000P
1808
3KV
10%
R46
75
0402
1%
GND_45
C
2 2012
2
2
GND
C408
0.1U
0402
10%
16V
PJRX-
12
13
R85 600Z/100M
1
2 1608
120Z/100M
1
2 2012
C407
0.1U
0402
10%
16V
PJRX+
PJTX-
CLOSE TO VT6103L
+3VS_LAN
1
16
15
14
GND
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
L33
C73
0.1U
0402
10%
16V
PJTX+
LF_H41S
SOX16
C63
0.1U
0402
+80-20%
50V
L28
90Z/100M
C54
0.1U
0402
16V
1
2
3
11
10
9
GND
+3VS_LAN_PLL
1
C51
0.1U
0402
10%
16V
4
1
R63
+3VS
2 0402 +3VS_LAN
2
RXINC61
2 0402
R88
2
2
0402
1
R45
1
1
1
2 0/NA
GND
120Z/100M
1
1
C88
0.1U
0402
10%
16V
1
TX+
CMT
TX-
1
LAN_PD#
LAN_RST
R65
TD+
TDC
TD-
1
24
42
RXIN+
6
7
8
1
REXT
FXEN
0402
1
31
28
1 LAN_XO
0402
0402
2 0/NA
GND
2
C85
22P
0603
5%
2
1
2
1
2
1
2
2 300
2 0/NA
1
2
VDD0
VDD1
VDDC
VDDOSC
VDDRX
VDDTX
VDDPLL
GND
GND
R91
39
L32
2
1M/NA
0402
R67
1
R44
2
GND0
GND1
GNDC
GNDOSC
GNDRX
GNDTX
GNDTXC
GNDPLL
+3VS
R98
1
FXEN
1 6.49K 2 0402
1%
1 5.1K
2 0402
R43
2
RXDV
RXER
R70
GND
2
PD#
RST
REXT
U4
TXD+
TXD-
1
REXT
TEST
25MHZ
C87
22P
0603
5%
2 0402
D
2 0603
2
XO
+3VS
2 LAN_XO
1 1.5K
2
X1
LAN_DATAIO R87
LAN_XI
40
XI
RXC
PHYAD1/RXD3
PHYAD2/RXD2
PHYAD3/RXD1
PHYAD4/RXD0
TEST#
SPEED
DUPLEX
ANE
20
21
22
23
2
COL
CRS
C
LAN_XI 1
2 0402
2
LED0/LINK
LED1/SPD100
LED2/DUPLEX
LED3/NWAYEN
VT6103L
PQFP48_0.5MM
GND_PLL
1 10K
1 0
1
GND
R52
+3VS_LAN
R34
2
0
0603
TEST#
GND
C65
0.1U
0402
10%
16V
C71
0.1U
0402
10%
16V
GND
GND_45
+5VS
GND_PLL
C422
0.1U
0402
10%
+5VS
C423
0.1U
0402
10%
+3V
2
2
17
6
38
29
37
33
30
2
1 5.1K/NA 2 0402
R77
49.9
0402
1%
1
3
5
R50
C50
0.1U
0402
50V
+80-20%
2
1 R73
2 0402
2 0402
LAN_PD#
R78
49.9
0402
1%
C75
0.1U
0402
+80-20%
50V
1
R74 1 22
R413 1 22
2 0402
1
4
45
46
47
48
1 10K
L26
90Z/100M
1608
2
3
2 0402
5 0804
6
7
8
R37
120nH
1
4
R71 1 22
1 22*4
2
3
4
RXIN+
RXIN-
27
26
RX+
RX-
TXC
TXD0
TXD1
TXD2
TXD3
TXEN
TXER
TXD+
TXD-
35
34
2
15
16
TX+
TX-
1
2 0402
2 0402
DUPLEX
CLOSE TO VT6103L
1
LAN_MRXDV
LAN_MRXER
10 LAN_MRXDV
10 LAN_MRXER
1 22
1 22
2 0402
1
R54
R53
1 10K
1
GND
LAN_MTXD1
LAN_MTXD2
LAN_MTXD3
LAN_MTXE
LAN_MRXC
LAN_MRXD3 RP6
LAN_MRXD2
LAN_MRXD1
LAN_MRXD0
10 LAN_MRXC
10 LAN_MRXD3
10 LAN_MRXD2
10 LAN_MRXD1
10 LAN_MRXD0
9
11
12
13
14
10
8
R51
1
10 LAN_MTXD0
10 LAN_MTXD1
10 LAN_MTXD2
10 LAN_MTXD3
10 LAN_MTXE
R64 1 2.1K/NA 2 0603
1%
LAN_COL
10 LAN_COL
LAN_CRS
10 LAN_CRS
2 0402
SPEED
2
R62 1 22
LAN_MTXD0
MDIO
MDC
INT#/PHYAD0
2
10 LAN_MTXC
2 0402
1
LAN_MTXC
1
1 10K
2
TP505
43
44
19
R36
L31
U2
LAN_DATAIO
ANE
1
PHY ADDRESS = 00000
as short as possible
2
S/W/W/S=10/8/8/10 mils
2
二組中間須絕緣, EX: GND SHIELDING
2
二組各自平行走線等長
D
1
LAN PHY (VT6103L) & MDC
Layout Note:
10 LAN_DATAIO
10 LAN_DCLK
2
+3V
GND_PLL
B
B
TIP
J5
CLOSE TO CONN.
2
1
1
2
3
AC97_SYNC
MDC_SDIN
2
1
2 22
0402
AC97_BITCLK
5%
CLOSE TO CONN.
2
1
S501
Protector/NA
2
400UH
3
AUDIO CODEC ON MOTHER BD
A1
A2
A3
A4
1
2
GND
1
LOW
2
C666
1000P
1808
3KV
10%
PJ7
PJ8
RXPJ4
PJ5
RX+
TXTX+
A1
A2
A3
A4
GND1
GND2
RJ45-8P/RJ11-4P
AMP 1470120-2
TIP_1
1
L105
F502
PIN 16
TIP_1
TIP
RING
RING_1
0402
AC97_BITCLK 9,15,18
C352
10P/NA
0402
5%
50V
MDC HARDWARE S TRAP
HIGH
2
GND1
GND2
1808A
GND
PJ4
PJRX+
PJTXPJTX+
JS1
1
SHORT-SMT4
C2
1000P
1808
3KV
10% RING
GND_MDC
2
A
GND
8
7
6
5
4
3
2
1
PJ7
PJRX-
R5
AC97_SYNC 9,15,18
MDC_SDIN 9,15
1
0402
0402
2
2 22
2 22
0
R334 1
2
C3
1000P
1808
3KV
10%
MINISMDC110/NA
CLOSE TO MDC
R341 1
R336 1
F501
1
1
1
1808A
GND
Sec soure 291000923002
S1
Protector/NA
400UH
1.25MM/ST/MA-4
ACES
85205-0400
C353
1U
0402
+80-20%
6.3V
2
R342 4.7K 0402
1
2
FM/0.8MM/H8.4
AMP 3-1473293-0
CLOSE TO MDC
L19
1
2
C167
1U
0402
+80-20%
6.3V
1
2
3
4
0402
2
5
AC97_SDOUT
AC97_RST#
1
9,15,18 AC97_SDOUT
9,15,18 AC97_RST#
+3V
+5V
R343 0/NA
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
+3VS
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
Modem Dougther Board
MONO_OUT
2
+3V
J15
18 MONO_OUT
5
J7
1
Sec soure 291000010410
GND_45
GND_MDC
Sec soure 291000810819
JS506
1
2
SHORT-SMT4
C667
1000P
1808
3KV
10% RING_1
GND_MDC
A
MINISMDC110/NA
R867
AUDIO COD EC ON DAUGHTER BOARD
1
0
5%
2
0402
Title
<Title>
Size
C
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
16
of
26
5
4
3
2
USB2.0 & Flash ROM
F2
2
USB_OC#1 8
1
C4
1000P
0402
10%
50V
+5V
9 ISA_SA18
GND
R389 1 0
2 0402
R390 1 0/NA
2 0402
GND
1 0/NA
+5V
USB 2.0
2 0603
R22
1 0/NA
2 0603
USBP1-
USBP0+
8 USBP0+
0603
32
C362
0.1U
0402
10%
10V
3
2
A1
A2
A3
A4
USBP1- 8
L23
90Z/100M
GND1
GND2
GND3
GND4
1
R23
USBP1+
2
0/NA
0603
SHORT-SMT4
GND
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
1
2
1
GND
USB_OC#3 8
1
2
USB_OC#3
R26
560K
0402
1%
GND_USB GND_USB
C37
1000P
0402
10%
50V
2
R29
560K
0402
1%
2
C39
1000P
0402
10%
50V
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
ISA_MEMW# 9
1G
2G
VCC
GND
+5V
20
10
SO20
2
74HCT244D
ISA_SA0
ISA_SA1
ISA_SA2
ISA_SA3
ISA_SA4
ISA_SA5
ISA_SA6
ISA_SA7
18
16
14
12
9
7
5
3
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15
U24
2
4
6
8
11
13
15
17
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1G
2G
VCC
GND
18
16
14
12
9
7
5
3
GND
1
19
ISA_SOE#
74HCT244D
C382
0.1U
0402
10%
10V
ISA_SA8
ISA_SA9
ISA_SA10
ISA_SA11
ISA_SA12
ISA_SA13
ISA_SA14
ISA_SA15
C
+5V
1
1
2
GND
C383
0.1U
0402
+80-20%
16V
R27
10K
0402
1%
+ C33
330U
6.3V
20%
2
1
2
USB_OC#2
1
8 USB_OC#2
2
1
2
C34
1U
0402
+80-20%
6.3V
R28
10K
0402
1%
2
1
1
MINISMDC110
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
20
10
SO20
2
F3
+5VS
ISA_MEMW#
ISA_SA16 9
ISA_SA17 9
ISA_ROMCS# 9
ISA_MEMR# 9
ISA_MEMR#
U23
2
4
6
8
11
13
15
17
1
19
9 ISA_SOE#
C
31
D
IDE_SDD[0..15]
9,13 IDE_SDD[0..15]
Sec soure 331000008090
2
GND_USB
WE#
VSS
ISA_SA0
ISA_SA1
ISA_SA2
ISA_SA3
ISA_SA4
ISA_SA5
ISA_SA6
ISA_SA7
ISA_SA8
ISA_SA9
ISA_SA10
ISA_SA11
ISA_SA12
ISA_SA13
ISA_SA14
ISA_SA15
ISA_SA16
ISA_SA17
SDA0 ==>
LDT Trasmit Timing control
GND
JS504
VCC
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
22
24
32P/PLCC/SMT
PLCC32
USBP1+ 8
4PX2/RA
TYCO
1470748
1
16
4
GND1
GND2
GND3
GND4
2
0/NA
A1
A2
A3
A4
B1
B2
B3
B4
1
3
1
R20
90Z/100M
L22
4
1
2
J3
B1
B2
B3
B4
VPP
1
USBP0- R21
8 USBP0-
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CE#
OE#
O0
O1
O2
O3
O4
O5
O6
O7
1
R4
560K
0402
1%
GND_USB GND_USB
13
14
15
17
18
19
20
21
ISA_SD0
ISA_SD1
ISA_SD2
ISA_SD3
ISA_SD4
ISA_SD5
ISA_SD6
ISA_SD7
1
2
1
2
9
9
9
9
9
9
9
9
1
R9
560K
0402
1%
U25
USB_OC#1
2
C10
1000P
0402
10%
50V
2
2
GND
D
C380
0.1U
0402
+80-20%
16V
R10
10K
0402
1%
+ C32
330U
6.3V
20%
2
1
1
8 USB_OC#0
2
USB_OC#0
2
1
R11
10K
0402
1%
2
C36
1U
0402
+80-20%
6.3V
1
MINISMDC110
2
1
1
1
+5VS
1
C381
0.1U
0402
10%
10V
GND
GND
USBP2- R16
8 USBP2-
1 0/NA
USB 2.0
2 0603
R17
1 0/NA
2 0603
USBP3-
USBP2+
8 USBP2+
2
0/NA
0603
+5V
+5V
L21
90Z/100M
GND1
GND2
GND3
GND4
1
R18
+5V
+5V
+5V
3
2
A1
A2
A3
A4
4
GND1
GND2
GND3
GND4
A1
A2
A3
A4
B1
B2
B3
B4
1
3
1
R15
90Z/100M
L20
4
1
2
J4
B1
B2
B3
B4
USBP3- 8
USBP3+
2
0/NA
0603
USBP3+ 8
ISA_SA0
ISA_SA1
ISA_SA2
ISA_SA3
RP64
1
2
3
4
5
10
9
8
7
6
4.7K*8
RP71
ISA_SA12 1
ISA_SA13 2
ISA_SA14 3
ISA_SA15 4
5
ISA_SA4
ISA_SA5
ISA_SA6
ISA_SA7
1206
10
9
8
7
6
4.7K*8
ISA_SA8
ISA_SA9
ISA_SA10
ISA_SA11
ISA_MEMR# R395 1 4.7K
2 0402
ISA_MEMW# R392 1 4.7K
2 0402
1206
4PX2/RA
TYCO
1470748
JS505
B
1
Sec soure 297040100027
2
SHORT-SMT4
GND
GND_USB
2
19 POWERBTN#
JO530
1
2
1
3
1
GND
2
2
C386
1000P
0402
10%
50V
1
SW505
SW506
1
2
3
4
1
3
19 KI4
DOWN
GND
USBP4- R404 1 0/NA
USB 2.0
2 0603
USBP4+
2 0603
USBP5-
1
R405
GND1
GND2
GND3
GND4
2
0/NA
0603
3
2
A1
A2
A3
A4
GND1
GND2
GND3
GND4
GND
USBP5- 8
Sec soure 297030105003
L98
KO0
2
4
5
TC010-PSS11CET
GND
297040105010
SW_TC010-PS11CET
T-MEC(台灣美琪)
Sec soure 297040100027
90Z/100M
4
3
2
A
A1
A2
A3
A4
B1
B2
B3
B4
1
4
1
B1
B2
B3
B4
90Z/100M
8 USBP4+
R136 1 0/NA
J9
L97
KO0 19
TC010-PSS11CET
GND
297040105010
SW_TC010-PS11CET
T-MEC(台灣美琪)
JO531
2
1
5V/1MA
DT016-PT11AB-B-1
GND
8 USBP4-
2
4
5
UP
JO529
USB_OC#5 8
19 LID#
R353
560K
0402
1%
GND
1
3
1
R224
560K
0402
1%
USB_OC#5
2
C385
1000P
0402
10%
50V
2
2
GND
R212
10K
0402
1%
+ C384
C101
330U
0.1U
6.3V
0402
20%
+80-20%
16V
1
1
2
1
1
8 USB_OC#4
2
2
1
R195
10K
0402
1%
USB_OC#4
KI3
19 KI3
TC010-PSS11CET
297040105010
SW_TC010-PS11CET
GND
T-MEC(台灣美琪)
2
MINISMDC110
C84
1U
0402
+80-20%
6.3V
2
4
5
1
600Z/100M
2 1608
2
2
1
1
1
SW502
SW501
L101
1
F4
+5VS
B
Sec soure 297040100027
JO501
Sec soure 331000008090
1
R149
A
USBP5+
2
0/NA
0603
USBP5+ 8
4PX2/RA
TYCO
1470748
JS501
1
2
GND_USB
Title
Sec soure 331000008090
SHORT-SMT4
<Title>
Size
C
GND
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
17
of
26
5
4
3
2
1
Audio CODEC(VT1617A)
+3V
C144 1
C142 1
C143 1
2 1U 0402
2 1U 0402
2 1U 0402
18
20
19
C153 1
C157 1
2 1U
2 1U
0402
0402
23
24
0402
0402
0402
12
21
22
13
LNL/SR_OUT_L
LNL/SR_OUT_R
VIDEO_L
VIDEO_R
CD_L
CD_R
CD_GND
LINE_IN_L
LINE_IN_R
SPDIF_OUT
VREF_OUT
VREF
CAP2
LFE_OUT
NC0
NC1
NC2
NC3
CENTER_OUT
PC_BEEP
MIC1
MIC2
PHONE
37
C187 1
2 1U
39
41
C191 1
C192 1
2 1U/NA 0402
2 1U/NA 0402
48
28
32
44
31
33
34
40
43
AC_GPI3
C180
1000P
0402
10%
50V
1
C170
C181
1U
0.1U
0402
0402
+80-20%
16V
2
2
R428
10K/NA
0402
5%
R203
10K
0402
5%
C
+AVDDAD
AGND
C188
0.1U
0402
+80-20%
16V
2
Microphone Jack
AGND
C172
270P
0402
+/-10%
50V
10
30
31
32
33
34
HP/LINE
LLINEIN
LHPIN
LIN
G6
G7
G8
G9
G10
GND0
GND1
GND2
GND3
LOUT+
LOUTG1
G2
G3
G4
G5
1
GND
AGND
25
26
27
28
29
C232
1U
0402
+80-20%
10V
1
2
1
C224
100P
0402
10%
50V
AGND_C
C223
100P
0402
10%
50V
AGND_C
AGND_C
JACK-5P-R/A-W9.1
ST-28M-F60
331840005014
CONN_JACK_ST28MF60
AGND
+5V_AMP
C227
SPKR_ROUT+
1
2
P/N 286101428001
AGND
100U
16V
CPWX6.6
R217
1K
0402
1%
R223
47K
0402
5%
HP_SENSE
2
A
1
2
AGND
R222
2
1
R204
2
1
R205
2
EAPD
0/NA 0402
1
R1
0
0402
SB_GPO0 9
AGND
GND
C214 100K
0.1U 0402
0402 5%
+80-20%
16V
Title
<Title>
Size
C
Date:
5
C208
1U
0402
+80-20%
10V
6 J12
1
2
7
L41 120Z/100M 1608
5
L39
0603D
4
1
2 BEAD_600Z/100M
3
L50 600Z/100M
1
2 1608
SPKR_LOUT+
SPKR_LOUT-
4
9
2 0402
AGND
L51 600Z/100M
1
2 1608
2
HI
2
2
1
1
1
+
C229
0.1U
0402
+80-20%
16V
1
12
13
24
G1428
2
AGND
C212
0.1U
0402
5%
50V
SHUTDOWN
22
AGND
AGND
C213
0.1U
0402
+80-20%
16V
R215 1 4.7K
1
SHUTDOWN
11
+5V
L52 120Z/100M
2
1608
C419
C235
0.1U
100U
0402
16V
10%
CPWX6.6
1
2
SEBTL
19
2
LOW
B
AC_GPI3
1
BYPASS
+5V_AMP
2
VDD
GAIN0
GAIN1
SPKR_ROUT+
SPKR_ROUT-
7
18
1
1
C230
0.1U
0402
16V
+80-20%
2
1
C231
1U
0402
+80-20%
10V
3
1
LOW
15
R218
1K
0402
1%
AGND
HI
GND
MINIPCI_SPKR#
2
5
6
PC-BEEP
21
16
SHUTDOWN
Q13
DTC144TKA
GND
2
47K/NA
0402
1
2 1U
0402
2 1U
0402
R216
100K
0402
5%
A
CARDSPK# 14
R393
10K
0402
5%
2
C228 1
6.3V
C233 1
6.3V
+VDD3
SPK_OFF / EAPD Shutdown
2
1
15
17
" High Shutdown "
AGND
SB_SPKR 10
2
HP_SENSE
GND_USB
AOUT_L
1
1
+5V_AMP
2
3
PVDD0
PVDD1
+
14
ROUT+
ROUT-
RIN
2
1
R219 1 100K
2 0402
R221 1 100K
2 0402
R220 1 100K/NA 2 0402
RHPIN
RLINEIN
2
8
1
2 1U
0402
TP534
0603D
2 BEAD_600Z/100M
AGND
AGND_C
R206
10K
0402
5%
U13
20
23
C234 1
10V
GND
L40
1
1
100U
16V
CPWX6.6
2
2 1U
0402
2 1U
0402
0603
AGND
CARDSPK#
1
C211 1
6.3V
C210 1
6.3V
AOUT_R
SB_SPKR
2
AGND
平行走線等長
2
0
R185
2
1U/NA
0402
6.3V
+80-20%
2
0603D
2 BEAD_600Z/100M
GND
1
L57
SPKR_LOUT+
Sec soure 339115000059
Internal Microphone
W=10mils
as short as possible
B
AGND
+
-
D6/H2.2
FM-10B1P-07
GND
L38
1
C236
+
L62 120Z/100M 16081
1
2
2
0603D
2 BEAD_600Z/100M
AGND
1
MIC501
AGND AGND
GND
AHC1G86DBV
SOT25
AGND
C161
1
L49
1
AGND
4
AGND_C
AGND
close to MTG8
U11
5%
10K
0402
5%
1
JACK-5P-R/A-W9.1
ST-28M-F60
331840005013
CONN_JACK_ST28MF60
100K 2 0402
1
R403
R202
1U
0402
6.3V
+80-20%
5
2
2
1
GND
C193
1U
0402
+80-20%
10V
2
C148
PCBEEP
2
2
2
5%
R214
47K
0402
5%
2
R178
47K
0402
AGND
1
1
1
2
AGND
C201
270P
0402
50V
1
1
2
C162
270P
0402
50V
GND
6 J10
7
5
4
3
3
L43
600Z/100M
AGND
2
1
2 1608
0402
L48
600Z/100M
R213 1 1K
2
1
2 1608
0402
R2011 4.7K/NA 2 0402 AC_GPI0
R194 1 1K
1
AC_ID1
C174
270P
0402
+/-10%
50V
1
C163
1U/NA
0402
3
VT1617A
PQFP48_0.5MM
1
5% VREF_OUT
2 0402
2
29
30
C173
0.1U
0402
+80-20%
16V
1
AFLT1
AFLT2
XTAL_OUT
C171
C169
1U
0.1U
0402
0402
+80-20%
16V
2
1
1
VREF_OUT
1
AGND
R200 1K 5% 0402
1
2
2
R189
2.2K/NA
0402
5%
0
XTAL_IN
MONO_OUT 16
27
1
R191 1
2
MONO_OUT
0402
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
2
5 AUDIO_14M
+AVDDAD
1
2
AOUT_L
AOUT_R
35
36
1
16
17
MONO_OUT
2
2 1U 0402
2 1U 0402
LINE_OUT_L
LINE_OUT_R
Close to L78L05ACU
1
C400 1
C401 1
AUX_L
AUX_R
D
AGND
2
14
15
C199
10U
0805
10V
+80-20%
EAPD
47
1
2 1U 0402
2 1U 0402
EAPD
1
C146 1
C145 1
SYNC
SDATA_IN
SDATA_OUT
RESET#
BIT_CLK
46
45
C189
0.1U
0402
+80-20%
16V
2
0402
ID1
ID0
1
0402
2 22
10
8
5
11
6
2
2 22
R333 1
2 1U
2 1U
2 1U
C190
0.1U
0402
+80-20%
16V
AC_ID1
AC_GPI0
1
R192 1
C135 1
C141 1
C147 1
26
42
2
AGND1
AGND2
1
DGND1
DGND2
Close to Codec
2
C133
2200P
0603
PCBEEP
MIC1
MIC2
C
+5V
L47 120Z/100M
1608
1
2
25
38
2
4
7
2
2
2
AVCC1
AVCC2
Audio Codec
1
R176
100K
0402
5%
C134
2200P
0603
1
1
1
5%
5%
R177
100K
0402
5%
C185
0.1U
0402
+80-20%
16V
DVCC1
DVCC2
1
2 0402
2 0402
1
330
330
1
CDROM_LEFT R173 1
CDROM_RIGHT R172 1
CDROM_COM M
AC97_SYNC
AC97_SDIN
ACSDOUT
AC97_RST#
AC97_BITCLK
9,15,16 AC97_SYNC
9 AC97_SDIN
9,15,16 AC97_SDOUT
9,15,16 AC97_RST#
9,15,16 AC97_BITCLK
Sec soure 291000010410
C182
0.1U
0402
+80-20%
16V
CLOSE TO CODEC
1.25MM/ST/MA-4
L56 120Z/100M 1608
13 CDROM_LEFT
13 CDROM_RIGHT
13 CDROM_COM M
C186
0.1U
0402
+80-20%
16V
2
SPKR_LOUT+
SPKR_LOUT-
ACES
85205-0400
2
L55 120Z/100M 1608
1
2
1
2
1
9
2
1
2
3
4
L54 120Z/100M 1608
D
+AVDDAD
U10
L45 120Z/100M 1608
1
2
J13
2
L53 120Z/100M 1608
1
2
1
2
SPKR_ROUT+
SPKR_ROUT-
4
3
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2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
18
of
26
5
4
3
KBC (W83L950D)
BATT_DEAD#
KBC_ADEN#
POWERBTN#
LID#
+SVDD3
1
2
3
4
5
10
9 KBC_RSMRST
8
7
6
10K*8
1206
+VDD3
RP47
KI0
KI1
KI2
KI3
C
1
2
3
4
5
+VDD3
10
9
8
7
6
KI4
KI5
KI6
KI7
2
JO503
2
JO505
1
2
JO507
2
JO509
2
JO511
2
JO513
2
JO515
1
JO508
1
JO510
1
24 BATT_SELL
13 AC_POWER#
17 KO0
1
2
1
2
JO512
1
JO514
1
JO516
1
JO518
1
1
2
1
2
JO517
1
2
2
1
JO506
1
2
2
1
JO504
1
2
2
JO502
1
2
JO519
1
2
JO520
1
JO522
1
JO524
1
27
26
BATTRY_TYPE
13
12
KO0
KO1
KO2
KO3
KO4
KO5
KO6
KO7
KO8
KO9
KO10
KO11
KO12
KO13
KO14
KO15
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
KI0
KI1
KI2
KI3
KI4
KI5
KI6
KI7
62
61
60
59
58
57
56
55
GP40/XOUT/PWM2
GP41/XCIN/PWM3
GP56/DA1/PWM01
GP57/DA2/PWM11
GP54/CNTR0
GP55/CNTR1
GP60/AN0/INT5
GP61/AN1/INT6
GP62/AN2/INT7
GP63/AN3/INT8
GP64/AN4/INT9
GP65/AN5/INT10
GP66/AN6/INT11
GP67/AN7/INT12
GP0/P3REF/FA0
GP1/FA1
GP2/FA2
GP3/FA3
GP4/FA4
GP5/FA5
GP6/FA6
GP7/FA7
GP10/FA8
GP11/FA9
GP12/FA10
GP13/FA11
GP14/FA12
GP15/FA13
GP16/FA14
GP17/FA15
JO521
2
JO523
1
2
1
2
17 KI3
17 KI4
GND
KBD_CS0 8
RESET#
XIN
XOUT
GND
+SVDD3
D14
BLADJ 12
I_CTRL 24
POWERBTN#
1
80
79
78
77
76
75
74
KBC_+3VS
KBC_CPUCORE
25
KBC_RESET#
28
XIN
29
XOUT
BAV70LT1
POWERBTN# 17
KBC_PWRON_+VDD3 20
CHARGING 24
BAT_VOLT
BAT_TEMP
I_LIMIT 23
KBC_RESET# 20
VREF
VCC
VSS
AVSS
CNVSS
Come From Battery
RP44 33*4
1206
1
2
BAT_CLK 3
BAT_DATA 4
C301
0.1U
0402
+80-20%
16V
BAT_V
BAT_T
BAT_C
BAT_D
8
7
6
5
C302
0.1U
0402
+80-20%
16V
BAT_V
BAT_T
BAT_C
BAT_D
23
23
23
23
GND
+KBC_VREF
GP30/PWM0/FCTRL0
GP31/PWM10/FCTRL1
GP32/FCTRL2
GP33/FCTRL3#
GP34/BANK0
GP35/BANK1
GP36/CE#
GP37/OE#
W83L950D
10K*8
1206
11
10
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
2
FPC/FFC/1MM/26P
ACES
85202-26-05
FAN0
FAN1
3
JO525
1M
1
2
R292
0402
X4
1
2
+KBC_VDDA
72
71
30
73
24
C304
0.1U
0402
16V
+80-20%
C303
0.1U
0402
16V
+80-20%
5%
1
RP53
2
C329
22P
0402
+/-10%
8MHZ
2
+SVDD3
KO0
KO1
KO2
KO3
KO4
KO5
KO6
KO7
KO8
KO9
KO10
KO11
KO12
KO13
KO14
KO15
KI7
KI6
KI5
KI4
KI3
KI2
KI1
KI0
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
BATT_G# 13
BATT_R# 13
BATT_POWER# 13
CAP# 13
NUM# 13
SCROLL# 13
2
J501
KBC_SB_PWRBTN
KBC_WAKE_UP#
KBC_EXTSMI#
D
SB_THRM# 10
KBC_WAKE_UP#
2
2 0402
2 0402
2 0402
T_CLK 13
SUSC# 9,21
38
37
36
35
34
33
32
31
1
R285 10K 1
R293 10K 1
R273 10K 1
GP76/SDA
GP77/SCL
T_DATA 13
1
3
2
GP20/FD0/LPCEN
GP21/FD1
GP22/FD2/SDA1/RXD1
GP23/FD3/SCL1/TXD1
GP24/FD4
GP25/FD5
GP26/FD6
GP27/FD7
KBRC# 8
A20G 8
T_DATA
KBC_RSMRST
KBC_SB_PWRBTN
T_CLK
KBC_EXTSMI#
9
8
7
6
5
4
2
BAT_DATA
BAT_CLK
+VDD3
GP50/A0
GP52/INT30#/R
GP53/INT40#/W
GP42/INT0/OBF00
GP43/INT1/OBF01
GP46/SCLK1/OBF1
LID# 17
21
20
1
KBC_SUSB
KBC_SCI
GP70/SIN2
P71/SOUT2
GP72/SCLK2
GP73/SRDY2#/INT21
GP74/INT31
GP75/INT41
LID#
KBC_PWR_ON
16
18
1
20,23 ADEN#
23 LEARNING
20 KBC_SUSB
D
17
15
14
23
22
19
GP44/RXD
GP45/TXD
2
SW_VDD3
BATT_DEAD#
KBC_ADEN#
20 SW_+SVDD3
GP51/INT20#/S0
GP47/SRDY1#/S1
1
L60 120Z/100M
1608
1
2
7,8,11 LPC_RST#
10,15 LFRAME#
GP80/SD0
GP81/SD1
GP82/SD2
GP83/SD3
GP84/SD4
GP85/SD5
GP86/SD6
GP87/SD7
2
LAD3
LAD2
LAD1
LAD0
70
69
68
67
66
65
64
63
SERIRQ
LAD3
LAD2
LAD1
LAD0
KBC_LRST#
LFRAME#
LAD[0..3]
10,15 LAD[0..3]
+KBC_VDDA
1
U16
5 CLK_KBC
10,14,15 SERIRQ
2
30mil
+SVDD3
2
GND
C328
22P
0402
+/-10%
C
GND
GND
PQFP80_0.5MM
Sec soure 291000152610
+VDD3
BAT_CLK
BAT_DATA
T_DATA
T_CLK
1
8
7
6
5
KBC_EXTSMI#
RSMRST# 9
1
Q20
10K*4
1206
D
S
G
2
KBC_RSMRST
1
D
1
2
3
4
+3VS
3
KBC_+3VS
EXTSMI# 9
R270 1 10K/NA 2 0402
Q17
DTC144TKA
C318
0.1U
0402
+80-20%
50V
C306
0.1U
0402
+80-20%
50V
S
FDV301N
SOT23_FET
I_CHG 23
2
RP45
R1
R280
10K
0402
1
2
+SVDD3
2
+3VS
+5V
BATT_DEAD#
GND
R432
0
0402
R286
0/NA
0402
LOW
1
1
2
R1
KBC_WAKE_UP# 1
SB_PWRBTN# 9
D
S
+VCC_CORE
3
KBC_CPUCORE
WAKE_UP# 9
Q27
DTC144TKA
Q21
2N7002
2
FAN0
DTC144TKA
2
+VDD3
GND
HI
R289
20K
0402
1%
DTC144TKA
3
Q23
R1
G
2
2
SUSB# 9,20,22
BAT_DATA
R274 1 22
2 0402
D
S
THRM_DATA 5
FAN1
+3V
DTC144TKA
1
G
1
C26
1U
0402
+80-20%
6.3V
BAT_CLK
GND
2 0402
D
Title
Q19
2N7002
S
<Title>
THRM_CLK 5
D
S
GND
R275 1 22
Size
C
Date:
5
A
Q18
2N7002
D
S
D
DTC144WK
1
2
Sec soure 291000010209
GND
+3V
Q26
3
D
S
1.25MM/ST/MA-2
ACES
85205-0200
GND
2
G
J6
FAN
R295
10K
0402
5%
KBC_SUSB
PWR_ON_3VS_5VS 26
C321
10P
0402
+/-10%
50V
2
FAN OFF
2
S
FAN ON
1
1
1
FAN0
R123
470K
0402
5%
2
C86
0.1U
Q9
0402
+80-20% AO3403
16V
SOT23_FET
GND
G
2 0402
1
R288 1 1K
+SVDD3
LOW
2
Signal
KBC_PWR_ON
KBC_SCI
2
1
Close to AO3403
Q25
R1
1
3
9 SCI#
SCI#
+5V
1
2
C307
0.1U
0402
+80-20%
50V
R291
10K
0402
5%
CPU_FAN Control
A
R271 1 10K/NA 2 0402
1
1
GND
2
2
C207
1U
0402
+80-20%
6.3V
I_DISCHG 23
S
3
D
Q22
B
+VDD3
R277
10K
0402
5%
GND
KBC_SB_PWRBTNG
GND
Sec soure 291000010209
+3VS
D
2
S
2
D
S
1.25MM/ST/MA-2
ACES
85205-0200
BATT_DEAD_P 24
BAT_CLK
G
1
2
FAN OFF
12 ENBL_KBC
R1
R211
470K
0402
5%
J11
FAN
FAN ON
1
1
FAN0
C200
0.1U
Q11
0402
+80-20% AO3403
16V
SOT23_FET
GND
G
2
1
Close to AO3403
Q24
R1
DTC144TKA/NA
1
HI
1
Signal
2
+5V
1
B
3
CPU_FAN Control
2
2
GND
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
DOWN
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
19
of
26
5
4
3
2
1
POWER ON PERPHERIAL CIRCUIT
1
+KBC_VREF
R435
0
0805
PWR_VDDIN
+SVDD3
+VDD3
AO3413
+2.5VS
+5VS
U17
2
2
1
GND
D
C319
4.7U
0805
+80-20%
2
AME8800DEFT
SOT89N
1
1U
0603
2
2
2
C311
4.7U
0805
+80-20%
4.7U
0805
+80-20%
VIN
GND
GND
D12
3
GND
A
GND
Q16
R1
2 0402
5%
R266 1
0
2
2 0402
5%
KBC_PWRON_+VDD3 19
DTC144TKA
288202240001
GND
GND
1
1
R313 1
0
ADEN# 19,23
BAS32L
DTC144WK
288202237002
1
SW_+SVDD3
K
Q31
2
3
GND
19 SW_+SVDD3
C310
C269
GND
VOUT
1
1
1
C282
2.2U
0603
+/-10%
2
R263
100K
0402
5%
2
C351
4.7U
0805
+80-20%
3
G
R321
100K
0402
5%
D
1
S
G
1
C345
0.1U
0402
+80-20%
50V
2
C340
10U
0805
6.3V
10%
D
1
S
1
1
AMS3107
SOT223
286303107001
2
GND
S
1
D
G G
3
2
OUTPUT
2
GND
2
+3VS
G
1
INPUT
C333
10U
0805
10V
+80-20%
2
AO3413
+SVDD3
G
FUSE_1206
3216FF-1
1A-1206
1
Q15
Q36
AO3413
D
S
PWRIN1
2
Q12
D
S
1
D
U19
D
S
F5
2
1
1
OPEN-SMT4
JO528
2
1
4
1
2
GND
GND
1
5
C421
4.7U
0805
+80-20%
GND
C425
1U
0603
2
NC0
1
2
NC1
AME8800AEEV/NA
SOT25
C420
2.2U/NA
0805
+80-20%
2
C339
0.1U
GND
0603
25V
+80-20%
2
1
1
2
4
2
G
S
D
1
2
C335
10U
6.3V
0805
10%
+KBC_VREF
VOUT
VIN
GND0
C
GND
GND
1
GND
2
100K
0603
Q29
D
2N7002
2N7002
D
S
SUSB#
G
KBC_SUSB 19
S
C343
0.1U
0402
+80-20%
50V
GND
+3V
+3V_P
1
2
1
OPEN-SMT4
JO8
2
1
OPEN-SMT4
JO7
2
R134 1 0
3 +2.5VDDA_PG
KBC RESET#
14
U8D
2 0402
12
11
SUSB#
CPU_CORE_EN_P 25
13
74HCT08_V
TSSOP14
+2.5V
B
GND
2
B
2
S
+3VS
JO9
OPEN-SMT4
JO527
2
C344
0.1U
0603
50V
U29
3
2
1
GND
JO526
1
6
1
5
4
R298
Q28
G
5VTAP
OUT
ERRGND
7
+2.5V_P
GND
2
2
C390
0.1U
0402
+80-20%
50V
PWR_VDDIN
R296
1K
0402
5%
D
S
SUSB#
10U
6.3V
0805
10%
IN
SENSE
F/B
SHUTDN
LP2951-02BM/NA
SO8
3
2
1
C346
2
D 2
2N7002
1
D 2
S
Q41
G
GND
+2.5VS_DDR
R294
1
100K
0402
5%
R408
1K
0402
5%
D
S
4
1
1
GND
+2.5V
8
7
6
5
C336
2.2U
0603
1
2
GND
1
C337
1U
0402
+80-20%
10V
2
4
C359
10U
0805C
10V
2
1
1
2
C388
0.1U
0402
+80-20%
50V
U18
AO4422
SO8
+2.5VS_DDR
8
7
6
5
G
2
100K
0402
5%
D
G
R406
1
GND
+3V
3
2
1
S
D
8
7
6
5
8
2
7
3
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
For Lan
S
C387
1U
0402
+80-20%
10V
U21
AO4403
SO8
1
+5V
3
2
1
C
+3VS
1
U35
AO4403
SO8
+5VS
R431
0/NA
0805
U28
PWRIN1
OPEN-SMT4
OPEN-SMT4
R1
DTC144TKA
288202240001
+5VS
+5V_P
3
+3V
+3V
DTC144TKA
288202240001
+SVDD3
OPEN-SMT4
3
+1.2V_P
R407
1K
0402
5%
JO1
2
1
OPEN-SMT4
JO2
2
SW1
2
4
5
1
3
2
1
1
U22C
9
9,19,22 SUSB#
22 +1.2VPG
8
R355 1 0
2 0402
THERN_ALERM# 5
4
MN
VCC
RESET
GND
H8_RESET#
2
GND
KBC_RESET# 19
U22D
12
11
R409
100K
0402
5%
7
IMP811
SOT143
CPU_PWROK_2.5V 2
13
A
74HCT08_V
TSSOP14
GND
2
C389
1U
0402
+80-20%
10V
+2.5V
1
1
+1.5V
1
TC010-PSS11CET
297040105010
SW_TC010-PS11CET
T-MEC(台灣美琪)
2
OPEN-SMT4
74HCT08_V
TSSOP14
U38
3
A
PWROK_SB 3,7,9
10
Q40
1
+1.2VLDTA
R410
10K
0402
5%
THERM_ALERM#
14
1
OPEN-SMT4
JO10
2
ALL_PWROK_2.5V 3,7,9
+2.5V
14
1
OPEN-SMT4
JO11
2
OPEN-SMT4
CPU_THERMTRIP# 2
7
2
1
1
2
1
OPEN-SMT4
JO5
2
1
Q30
JO12
2
2
+1.25V_DDR_P
JO6
1
R1
+1.25VTT
+1.5V_P
GND
GND
JO4
1
2
1
OPEN-SMT4
JO3
2
GND
Title
<Title>
Size
C
OPEN-SMT4
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
20
of
26
5
4
3
2
1
+1.25V
PR58
0
5
6
SD
AVIN
VTT
PVIN
GND
GND1
GND2
GND3
GND4
GND5
1
+1.25V_DDR_P
+1.25V_DDR_P
2
PJL1
3
VSENSE
1
8
2
JP_NET20
1
9
10
11
12
13
D
2
GND
PC78
10U
1206
16V
PC74
10U
1206
16V
PC77
+ 150U
7243
6.3V
2
PC72
0.1U
0603
50V
GND
2
1
G2996
SO8_GND_4
GND
1
1
PC97
22U
1210
10V
4
VREF
VDDQ
1
PC89
0.1U
0603
50V
2
2
2
2
7
1
1
+2.5V_P
D
2
PR54
0
0603
2 PR53
0
120Z/100M
0603
PC86
2012
1000P
0603
25V
10%
1
1
2
PL11
1
2
SUSC#
1
+2.5V_P
0603
PU13
GND
+2.5V_P
DVMAIN
PL12
PJL2
+ PC95
22U/NA
25V
20%
1
1
JP_NET20
GND
A
PR46
10
0603
SS14
DC2010
K
PC70
PR48
2.2
0603
GND
2
PC80
0.1U
0805
10%
D
B
PL7
AO4410
SO8
288204410010
G
PC83
0.1U
0603
50V
PU10
4
2
2.2UH
IHLP5050CE-01
20%
PC68
10U
1206
16V
+ PC81
820U/NA
4V
+ PC82
820U
4V
K
1
2
3
S
1
1
D
2
2
PR51
8.2K
0603
1%
PD10
1
1
1
2
1
2
+2.5V_P
SO8
S
SC1470
TSSOP14
PC79
0.01U
0603
50V
10%
AO4422
14
13
12
11
10
9
8
2
SGND7
BST
DH
LX
ILIM
VDDP
DL
PGND
EN/PSV
VIN
VOUT
VCCA
FB
PGOOD
AGND
1
2
3
B
4
5
6
7
8
1
2
3
4
5
6
7
PU12
G
PU11
1
1
2
PC73
0.1U/NA
0603
50V
5
6
7
8
2
2
10U
16V
1206
1
PR47
0603
1 0
2
1
2
1
PD11
PC67
0.1U
0603
50V
GND
9,19 SUSC#
GND
2
1
2
+5V_P
1
2
PR49
1M
0603
C
PC75
1000P
0603
10%,X7R
1
1
GND
2
C
PC87
0.01U
0402
10%
50V
2
2
GND
1
1
2
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
+ PC96
22U
25V
20%
1
2
2
2012
120Z/100M
PC88
0.01U
0402
+80-20%
50V
2
1
1
2
SHORT-SMT4
2
JS3
1
PC71
0.1U
0402
+80-20%
50V
A
SSA34/NA
DC2010
JS2
1
2
SHORT-SMT1
GND
SGND7
DVT:
1. ADD PC77 150U/6.3V
2. PL8 take off placement
A
1
1
A
PR50
4.02K
0603
1%
Title
2
PR52
1K
0603
1%
2
<Title>
Size
C
SGND7
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
21
of
26
5
4
3
2
1
D
D
+2.5VS_DDR
PL2
1
2
PU2
AO4422
SO8
PC5
10U
1210
25V
20%
2
2
2
PC11
10U
1210
25V
20%
1
1
1
2012
120Z/100M
PC15
0.1U
0603
50V
GND
4
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
1
PC6
10U
1206
16V
PC3
10U
1206
16V
1
2
PC12
0.1U/NA
0603
50V
2
1
2
C
1
1
PC14
0.1U
0603
50V
2
+5V_P
PR9
20K
0603
1%
2
GND
1
G
2
1
PC7
+ 150U
7243
6.3V
PC8
0.1U/NA
0603
50V
AO4422
SO8
2
PC4
0.1U
0603
50V
PC9
+ 150U
7243
6.3V
4
1
1
1
2
PC10
10U
1206
16V
+1.2V_P
S
D
3
2
1
PU4
2
PC13
10U
1206
16V
1
1
2
D
8
7
6
5
5
6
7
8
2
G
C
S
1
2
3
+1.5V_P
GND
PR15
14K
0603
1%
1
PR8
9.09K
0603
1%
DRV1
ADJ1
EN1
PGD1
GND
IN
DRV2
ADJ2
EN2
PGD2
SC338
PSOP10_0.5MM
+VDD3
1
2
PR7
0
0603
10
9
8
7
6
2
1
9,19,20 SUSB#
1
2
3
4
5
GND
2
GND
PU3
1
PR13
PR16
10K
0603
1%
0
PR14
0603 47K/NA
0603
2
2
1
2
GND
PG_VCC_CORE_P 25
1
2
GND
B
PC16
0.1U
0603
50V
PR10
1
B
+3V
1
GND
GND
PR11
47K
0603
2
PR12
2
0
0603
1
2
+1.2VPG 20
0
0603
DVT:
1. ADD PC7.PC9 150U/6.3V
2. ADD PC5 10U/25V change from 272023106701 to 272023106502
3. PR8 change from 10Kto 9.09 for H/W +1.57V
A
Title
<Title>
Size
C
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
22
of
26
A
5
4
3
2
1
ADPIN & Dischrage
PWR_VDDIN
PD6
PD5
1
2
3
3
2
D
1
D
BAV70LT1
BAV70LT1
PD3
1
PL5
120Z/100M
2012
1
3
2
1
2
3
1
BATT1
1
PC124
0.01U
50V
10%
0603D
PC123
1000P
0603
25V
10%
+SVDD3
1
2
2
PR85
.01
2512
1%
2
1
1
1
GND
PR86
100K
0603
0.1%
1
PC125
0.1U
0603
50V
PR971
PR941
0
2 0603
0
2 0603
2
VCC
OUT2
RS2RS2+
8
7
6
5
B
MAX4377
MSOP8
GND
1
1
2
1
GND
OUT1
RS1RS1+
GND
GND
GND
PC130
0.1U
0603
50V
2
GNDB
BAT_V 19
1
2
3
4
19 I_DISCHG
PR91
20K
0603
1%
MA/2.5MM/7 P
TBTD-0070018_7
2
BAT_T 19
2 0603
2
0
1
PR92 1
PC126
0.1U
0603
50V
GND
PU20
2
PR109
PC147 10
0603
1U
0805
10V
2
2
2
PR88
4.99K
0603
1%
1
19 I_CHG
1
GNDB
PR87
499K
0603
1%
1
PL16
120Z/100M
2012
PC146
0.1U
0603
50V
BATT1
1
2
1
2
+SVDD3
PL17
120Z/100M
2012
1
2
2
2
1
B2
PC129
0.1U
0603
50V
2
TR/SFT-10A
FUSE_2917
1
PF3
7
6
5
4
3
2
1
1
S
1
GND
GND
7
6
5
4
3
2
1
2
D 2
C
GND
GND
GND
PQ14
2N7002
GND
PC44
1U
0805
10V
PQ18
AO4407/NA
SO8
24 BATT
GND
I_LIMIT 19
PJ2
PC118
0.1U
0603
50V
5
6
7
8
1
2
1
2
D
S
G
PC41
0.1U
0603
50V
5
6
7
8
2
D
PQ17
DTC144WK
SOT23AN_1
2
2
2
1
MAX4073FEUT-T
SOT26
PR31
10
0603
B
PC119
0.01U
0603
50V
10%
4
PR76
33K
0603
OPEN-SMT4
1
GND1
GND0
OUT
3
1
2
3
1
1
2
4
ADEN# 19,20
PJO501
S
1
1
VCC
PQ1
2N7002
PQ15
AO4407
SO8
G
1
100K
0603
PR82
226K
0603
1%
D
6
1
2
2
PC1
1000P
0603
D
RS+
RS-
D
S
G
PR2
1M
0603
PU9
4
5
Sec soure 331000007044
1
1
1
PC2
1000P
0603
2
GND
GND
S
PJO3 PJO4
SPARKGAP_6 SPARKGAP_6
2
PC149
0.1U
0603
50V
2
1
2
1
2
PR75
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
LEARNING
19 LEARNING
GND
C
PC148
0.01U
0603
50V
10%
SM840B/NA
DC2012
PR5
4.7K
0805
2
2
2
PR6
4.7K
0805
G
PR3
100K
0603
GND
1
PC152
0.01U
0603
50V
10%
K
1
1
1
1
1
PC151
1000P
0603
2
4
PC150
1000P
0603
2
1
PD4
A
2
A
2
PR4
470K
0603
8
7
6
5
2
A
PC39
0.1U
0603
50V
DVMAIN
ADINP 24
3
2
1
A4
S
2
2
.01
2512
1%
1
PL1
120Z/100M
PC38 2012
0.1U
0603
50V
1
K
3
4
PR1
1
G
GND
1 A3
D
6.5A/32VDC
2
PC40
1000P
0603
PD1
PD2
RLZ24D_NA BZV55C24V
MLL34B
MLL34B
A2
SBM1040
S
2
JACK-2P
331910002006
2
PU1
AO4407
SO8
2
1
1
1
A1
2
2
PF1
1
K
PJ1
2DC-S107B200
3
2
2
PR108
PC145 10
0603
1U
0805
10V
GND
BAT_C 19
BAT_D 19
DVT:
1. PU20--> VDD3 change to SVDD
2. ADD PR108 , PR109
3. ADD PR85
PVT:
1. PJO6.PJO7 take off
2. PJO1.PJO2 take off
2
2
Sec soure 331000007044
PJP1
PJO8
A
1
SPARKGAP_6
1
SPARKGAP_6
GND
GND
A
Title
<Title>
Size
C
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
23
of
26
5
4
3
2
1
CHARGING
PQ23
AO4407
SO8
S
PL20
L4 1
PL18
2
1
D
PD14
2
A
K
BATT 23
K
SSA34
DC2010
2
2IN+
2
PR101
13.7K
0603
0.1%
D
2
1
1
PR93
100K
0603
2
PC135
1U
0805
16V
PR90
10K
0603D
1%
PC132
1000P
0603
10%
1
D
S
S
G
2
BATT_SELL 19
16.8V;LOW
12.65V
PR84
0
0603
1
PJO9
OPEN-SMT4 BATT_SELL:HI
C
PR98
124K
0603
1%
2
2
2
2 0.01U 10%
50V
0603
1
1
PC141
PQ22
2N7002
PR89
4.7
0603
1
TL594C
SO16
CHARGING G
0.01U
50V
0603
10% 2
2
2IN+
GND
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
8
7
6
5
4
3
2
1
E1
C1
E2
GND
C2
RT
VCC
CT
OUTPUTCTRL
DTC
REF
FEEDBACK
2IN1IN2IN+
1IN+
1
9
10
11
12
13
14
15
16
PC144
0.1U
0603
50V
D
S
1
PU19
2N7002
D
S
2
1
3
PQ25
2N7002
PR95
10K
0603D
1%
PC138
REF
1
1
2
2
2 6.19K
1%
0603
1
PR99
2.49K
0603
1%
0.1U
16V
0603
10%
0.1U
50V
0603
PJO502
1
2
.02
2512
1%
GND
GNDB
2
2
PC133
PR107
1
PR96
1
2
S
C
2
2
1
PQ20
PC128
1
1
D
S
G
PR104
23.7K
0603
1%
PR100
249K
0603
1%
2
1
1
1
GND
A
BAS32L
MLL34B
PQ24
DTA144WK
SOT23AN_1
D
CHARGING
19 CHARGING
BZV55C20/NA
GND
GND
PD16
K
2
PD15
PR102
20K
0603
0.1%
PC143
0.1U
0603
+80-20%
A
BZV55C15V/NA
A
PC131
10U
1210
25V
20%/X5R
1
PD13
1
2
SSA34
DC2010
E
GND
PC127
1000P
0603
10%
1
K
1
2
1
1
3.0UH
SPC-06703
PC14030%
0.1U
0603
50V
2
PQ21
MMBT2222A
B
PD17
PC137
10U
1210
25V
20%/X5R
2
PR103
100K
0603
2
K
4
33UH
SPC-1204P
20%
A
2
PR106
4.7K
0603
1
PR105
4.7K
0603
C
PC139
1000P
0603
1
1
1
PC136
0.01U
0603
50V
10%
2
PC142
10U
1210
25V
20%/X5R
2
1
PC134
0.01U
0603
50V
10%
2
1
2
8
7
6
5
G
TR/3216FF-3A
3
2
1
L3
D
PL19
1
2
BEAD_120Z/100M
0805D
L2
2
1
PF2
1
23 ADINP
2
D
2
OPEN-SMT4
PJS501
2
19 I_CTRL
B
1
SHORT-SMT3
B
8
-
4
PR78
100K/NA
0603
1%
BATT_DEAD_P 19
=8.56V
PC122
0.1U/NA
0603
50V
DVT:
1. PC143 change from 1000P to 0.1U/50V
2. PR101 change from 1% to 0.1%
PVT:
1. PR104 change from 24.3K to 23.7K (271071237211) for 8 cell
charging voltage 16.9V
2
1
PR79
287K/NA
0603
1%
PC121
0.1U/NA
0603
50V
7
PU18B
LMV393M/NA
SSOP8
1
+
6
1
5
2
3
PQ19
SOT23N
SCK431LCSK-.5/NA
2
1
1
GND
PR80
100K/NA
0603
2
1.25V_REF
2
PU18A
LMV393M/NA
SSOP8
PR77
590K/NA
0603
1%
2
GND
1
PC120
0.1U/NA
0603
50V
2
2
1
4
2
+
2
PR83
3.3K/NA
0603
8
3
1
1
+SVDD3
1
D/VMAIN
+SVDD3
A
2
G
PQ16
2N7002/NA
A
PJO5
OPEN-SMT4
1
PR81
0/NA
0603
D
S
S
BATT_SELL1
GND
2
D
GND
Title
BATT_SELL:HI
11.1V;LOW
8.556V
<Title>
Size
C
GND
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
24
of
26
5
4
3
2
1
VCC_CORE
PL9
1
2
BEAD_120Z/100M
0805D
D
D
PL10
1
PC56
0.1U
0603
50V
1
1
PC28
0.1U
0603
16V
PC18
1000P
0603
10%
+ PC58
820U
2.5V
2
1
PC19
1
2
2
ISL6559
SOL28
K
PC31
0.1U
0603
16V
1
2
2
2
1
2
1
1
GND
GND
+VCC_CORE
8
5
PQ5
AOB416
G
0.68UH
IHLP5050CE-01
PD8 20%
PQ6
AOB416/NA
G
ISL6207
SO8
+ PC25
820U
2.5V
SSA34
DC2010
+ PC29
820U
2.5V
1
LGATE
1
1
GND
2
1
PHASE
1
1
UGATE
PWM
P4_2
PC65
0.1U
0603
16V
PC46
1000P
0603
10%
GND
PR33
GND
2
D/VMAIN_P3
B
1
1
PC51
10U
1210
25V
2
PC24
10U
1210
25V
2
1
PC57
1000P/NA
0603
2
1
2
1
2
2
PC59
0.1U/NA
0603
16V
PC43
10U
1210
25V
0.1U/NA
0805
10%
PR40
2
7
6
2
2
PHASE
GND
LGATE
1
2
0.68UH/NA
IHLP5050CE-01
20%
8
5
PQ9
AOB416/NA
G
1
PD9
PC61
ISL6207/NA
0.1U/NA SO8
0603
16V
SSA34/NA
DC2010
+VCC_CORE
PC64
+ 220U
7343
2V
PR35
1
1
3 VID3
1
3 VID2
1
3 VID1
1
3 VID0
1
0
0
0
0
2 PR20
0603
2 PR23
0603
2 PR24
0603
2 PR26
0603
2 PR27
0603
GND
2
P_VID4
2
3 VID4
PC60
+ 220U/NA
7343
2V
PC35
+ 220U
7343
2V
2
GND
0
1
+5V_P
1
GND
PWM
PL6
P4_3
1
2
1
0
0603
PC63
1U/NA
0805
16V
2
1
2
1
2
PR41
UGATE
D
3
4
PC26
0.1U/NA
0603
50V
BOOT
VCC
1
2
PR19
0
0603
EN
GND
2
A
1
2 PR39
0603
1
ENBALE
10/NA
0603
PQ8
AOB420/NA
G
S
0/NA
PR38
10/NA
0805
K
1
PU8
D
1
1
3K/NA
0603
P_VID3
P_VID2
GND
A
P_VID1
DVT:
1. PL3.PL4.PL6 change to 273000990127
2. ADD PR44.PR42 , PR43.PR45 N/A
3. PR30.PR33.PR35 change from 2K to 3K , for one low-side mos O.C.P
4.PQ3.PQ6 /NA
5.ADD input cap PC76.PC69.PC30.PC55.PC49.PC24.PC51.PC43
6.ADD output cap PC64.PC60.PC35
7.PC24.PC30.PC43.PC49.PC51.PC55 change from 272023106701 to
272023106502
PVT:
1. PC69.PC76.PC60 N/A
P_VID0
Title
<Title>
Size
C
Date:
5
IN-
2
PR42
0
0603
PL4
PC62
1K
0603
1%
A
1
A
VCC
2
D/VMAIN_P3
2
1
D
PQ7
AOB420
G
BOOT
1
GND
PR43
0/NA
0603
PC49
10U
1210
25V
2
PC33
1U
0805
16V
2
D
1
2
PC55
10U
1210
25V
2
4
33P/NA
0603
25V
+ PC54
22U
25V
20%
2
IN-
1
15
20
2
1
2
1
PR28
10
0805
3K
0603
PR37
20 CPU_CORE_EN_P
S
S
1
3
GND
330P/NA 0/NA
0603
0603
10%
1
14
2
PC30
10U
1210
25V
C
COREFB_L 2
S
B
PR29
3.48K
0603
2
PR21
107K
0603
1%
PR36
2 1
10
0603
EN
COREFB_H 2
PC17
1000P
0603
10%
2
RGND
OVP
1
1
PC42
6
IN+
PC45
GND_0
GND_1
GND_2
1
13
1
PC36
1000P
0603
K
VSEN
OFS
PC34
PC66
0.1U
0603
16V
D
VDIFF
FB
12
PC22
0.1U
0603
16V
A
2
EN
7
PR45
0/NA
0603
D/VMAIN_P3
PU7
2
SSA34
DC2010
S
8
PR34
1
PD7
D
10
23
19
18
24
IN+
2
PR44
0
0603
GND
1
4700P
0603
28
ISEN1
ISEN2
ISEN3
ISEN4
FS/DIS
IOUT
COMP
PQ3
AOB416/NA
G
2
0.1U
0805
10%
2
ENBALE
4.99K
0603
1%
PWM1
PWM2
PWM3
PWM4
PQ2
AOB416
G
3K
0603
1
2
VID0
VID1
VID2
VID3
VID4
5
PR30
22
21
17
25
2
1
LGATE
16
1
27
11
9
PR32
PC37
2
GND
1
0.68UH
IHLP5050CE-01
20%
8
ISL6207
SO8
PC20
0.1U
0603
16V
1
VCC
PGOOD
2
50V
2
1
S
2
1
56P
2 0603
PHASE
GND
PU6
PC32
1
PC23
1U
0805
16V
2
2
PR22
10K
0603
UGATE
PWM
1
3
1
1
C
VCC
D
10
0603
4
7
6
5
4
3
+VCC_CORE
CLOSE TO CPU
1
S
+3V_P
P_VID0
P_VID1
P_VID2
P_VID3
P_VID4
BOOT
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
GND
26
GND
PL3
1
6
EN
2
2
7
1
2
GND
PG_VCC_CORE_P
PQ4
AOB420
G
PU5
2
1
PR17
10
0805
S
0.1U
0805
10%
PR18
22 PG_VCC_CORE_P
2
D
1
PC47
0.1U
0603
16V
2
2
PC48
10U
1206
16V
2
1
PR25
0
0603
2
1
2
2
+ PC53
820U
2.5V
2
GND
2
+ PC50
820U/NA
2.5V
GND
1
1
2
GND
+5V_P
2
PC21
1000P
0603
1
+ PC27
22U
25V
20%
2
1
+ PC52
22U
25V
20%
2
PC69
+ 15U/NA
7243
25V
20%
1
1
1
PC76
+ 15U/NA
7243
25V
20%
2
2
PC84
1000P
0603
2
1
BEAD_120Z/100M
0805D
2
PC85
0.01U
0603
1
1
DVMAIN
+VCC_CORE
D/VMAIN_P3
2
2
1
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
25
of
26
5
4
3
2
1
+5V_P/+3.3V_P
DVMAIN
PL14
JS5
1
2
1
1
SHORT-SMT4
2012
120Z/100M
PC102
0.01U
0603
50V
10%
D
1
2
D
2
1
+ PC115
22U
25V
20%
BAW56
SOT23N
PC103
INTVCC22
1
2
0
0603
1
1
5
6
7
8
2
24
23
22
21
20
19
18
17
PU17
AO4422
SO8
1
1
2
3
1
2
3
4
5
6
7
8
PC113
0.1U
0603
50V
1
PR69
1
1
PC106
8200P
0603
10%,X7R
B
JS4
2
2
2
2
2
PR68
20K
0603
1%
2
2
1
1
2
1000P
0603
10%,X7R
107K
0603
1%
1
1
2
1
PR60
2K
PC100
0603
47P
0603
10%
2
2
1
1
2
+ PC114
680U
6.3V
20%
2
1
PC104
180P
0603
PC98
5%
180P
PC101
0603
5%
47P
10%
PR67 0603
PR66 200K
200K 0603
0603 1%
1%
PC110
10U
1206
16V
2
PC105
PR61
20K
0603
1%
B
+5V_P
S
2
63.4K
0603
1%
2
0.012
2512
1%
PU16
SI4832DY
SO8
4
1
1 PR59
1
1
D
G
PR74
2
PL15
10UH
SPC-1205P
20%
1
1
16
15
14
13
12
11
10
9
NC1
SW2
TG2
RUN/SS2
SENSE2+
SENSE2NC0
VOSENSE2
2
S1
SW1
TG1
PGOOD
RUN/SS1
NC2
SENSE1+
SENSE1NC3
SGND1
SGND2
SGND3
SGND4
SGND5
1
G1
25
26
27
28
29
30
31
32
33
34
35
36
37
1000P GND
0603
10%,X7R
GND
C
S
1
2
3
3
4
PC107
0.1U
0603
50V
D
G
4
BOOST1
VIN
BG1
EXTVCC
INTVCC
PGND
BG2
BOOST2
SW1
PC90
PC92
0.01U
0603 1
2
1
2
2
1
1
2
PC91
10U
1206
16V
2
2
G2
A
+ PC94
820U
4V
PC111
0.1U
0805
10%
2
.012
2010
1%
8
SW15 D1
6
7
PU14
LTC3728L
HVQFN32_1
5
6
7
8
2
PL13
10UH
SPC-1205P
20%
GND
VOSENSE1
PLLFLTR
PLLIN
FCB
ITH1
SGND
3.3VOUT
ITH2
1
GND
10U
16V
1206
PC99
0.1U
0603
50V
1
2
PC93
0.1U
0805
10%
AO4912
SO8
D2
PR73
2
PR70
2.2
0603
t
t
n
e e
r
c m
e
u
S
c
c Do
a
iT ial
M t
n
e
id
f
n
o
C
PU15
2
1
1
2
PC109
1000P
0603
10%,X7R
PC108
1000P
0603
20%
3
1
+5V_P
1
1
PD12
PR64
+3V_P
2
1
PR65
2.2
0603
1
2
2
1
GND
2
GND
GND
GND
C
+ PC112
22U
25V
20%
PC116
0.01U
0603
50V
10%
2
PC117
0.01U
0603
50V
10%
2
2
1
1
GND
1
2
2
SHORT-SMT1
GND
PR63
SGND3
0/NA
0603
1
+SVDD3
PR62
PR72
100K
0603
PWR_ON_3VS_5VS 1
G
PR56
1M
0603
0
19 PWR_ON_3VS_5VS
PQ13
2N7002
PR71 1
2 0603
SGND3
D
S
G
PQ12
2N7002
DVT:
1. PR74 change from 0.008 to 0.012
2. PL13.PL15 change to 273000990018 for height
3. PC90 change from 1000P to 4700P for H/W sequence
PVT:
1. +VDD3 change to +SVDD3
2. PC106 change from 1000P to8200P ( 272075822401 )
3. PC90 change from 4700P to 0.01U ( 272075103403 )
1
S
2
0
0603
D
S
G
PQ10
2N7002
S
1
2
D
S
D
PR55
S
D
S
2
PQ11
2N7002
D
2
D
10K
0603
1%
D
S
G
+SVDD3
INTVCC2
2
1
1
1
PR57
100K
0603
SGND3
R303
1M
0603
2
A
A
SGND3
Title
<Title>
Size
C
Date:
5
4
3
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com
2
Document
Number
Rev
R00
<Doc>
星期四, 五月 20, 2004
1
Sheet
26
of
26
REFERENCE MATERIAL
AMD Athlon 64 CLAWHAMMER Processor
AMD, INC.
“VIA K8N800 North Bridge”
VIA, INC.
“VIA VT8235 South Bridge”
VIA, INC.
H8/W83L950D
WINBOND, LTD.
System Explode View
Technology Corp / MiTAC
8399 Hardware Specification
Technology Corp / MiTAC
SERVICE MANUAL FOR 8399
Sponsoring Editor : Jesse Jan
Author : Grass Ren
Assistant Editor : Ping Xie
Publisher : MiTAC International Corp.
Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C.
Tel : 886-3-5779250
Fax : 886-3-5781245
First Edition : Aug.2004
E-mail : Willy.Chen @ mic.com.tw
Web : http: //www.mitac.com
http: //www.mitacservice.com