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32581C
Table 3-2.
Signal Definitions
BGU481 Ball Assignment - Sorted by Ball Number (Continued)
I/O
Buffer1 Power
Rail Configuration
(PU/PD) Type
Ball
No.
Signal Name
D10
GPIO1
I/O
(PU22.5)
INT,
O3/5
VIO
IOCS1#
O
(PU22.5)
O3/5
TFTD12
O
(PU22.5)
TRDE#
Ball
No.
Signal Name
PMR[23]3 = 0 and
PMR[13] = 0
D26
INTA#
VIO
PMR[23]3 = 0 and
PMR[13] = 1
D27
AVCCUSB
D28
O1/4
VIO
PMR[23]3 = 1
O
O3/5
VIO
PMR[12] = 0
GPIO0
I/O
(PU22.5)
INTS,
O3/5
VIO
D12
VCORE
PWR
---
D13
VSS
GND
D14
VIO
D15
D16
D11
I
(PU22.5)
INPCI
VIO
---
PWR
---
---
---
GPIO6
I/O
(PU22.5)
INTS,
O1/4
VIO
PMR[18] = 0 and
PMR[8] = 0
DTR2#/BOUT2
O
(PU22.5)
O1/4
PMR[18] = 1 and
PMR[8] = 0
PMR[12] = 1
IDE_IOR1#
O
(PU22.5)
O1/4
PMR[18] = 0 and
PMR[8] = 1
---
---
SDTEST5
O
(PU22.5)
O2/5
PMR[18] = 1 and
PMR[8] = 1
---
---
---
O
O8/8
PWR
---
---
---
VIO
PWR
---
---
---
NC
---
---
---
---
D30
TDP
I/O
Diode
---
---
I
(PU22.5
PD22.5)
INT
VIO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
(PU/PD under software control.)
D31
TDN
I/O
WIRE
VIO
---
E1
AD16
I/O
INPCI,
OPCI
VIO
Cycle Multiplexed
A16
O
OPCI
TFTD14
O
O1/4
PMR[23]3 = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
E2
AD19
I/O
INPCI,
OPCI
VIO
Cycle Multiplexed
F_C/BE2#
O
O1/4
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
A19
O
OPCI
E3
AD18
I/O
INPCI,
OPCI
VIO
Cycle Multiplexed
A18
O
OPCI
I/O
(PU22.5)
INPCI,
OPCI
VIO
Cycle Multiplexed
BHE#
O
OPCI
SIN2
I
INTS
VIO
PMR[28] = 0
SDTEST3
O
O2/5
I
(PU22.5)
INPCI
VIO
---
D175, 2 PE
D18
VIO
PWR
---
---
---
D19
VSS
GND
---
---
---
I/O
INT,
O14/14
VIO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
D205, 2 PD2
TFTD8
D215, 2
O
O1/4
F_AD2
O
O14/14
ERR#
I
INT,
O1/4
TFTD4
O
O1/4
F_C/BE0#
O
PMR[23]3 = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
VIO
PMR[23]3
= 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
D29
O1/4
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
O
O14/14
VIO
TFTD2
O
O1/4
PMR[23]3 = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
INTR_O
O
O14/14
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
E4
E28
D23
VIO
PWR
---
---
---
NC
---
---
---
---
D25
VSS
GND
---
---
---
DEVSEL#
VIO
INSTRP
I
(PD100)
--Strap (See Table 34 on page 44.)
PMR[28] = 1
E29
TRST#
E30
TDO
O
OPCI
VIO
---
E31
TCK
I
(PU22.5)
INPCI
VIO
---
F1
TRDY#
I/O
(PU22.5)
INPCI,
OPCI
VIO
Cycle Multiplexed
D13
I/O
(PU22.5)
INPCI,
OPCI
IRDY#
I/O
(PU22.5)
INPCI,
OPCI
VIO
Cycle Multiplexed
D14
I/O
(PU22.5)
INPCI,
OPCI
C/BE2#
I/O
(PU22.5)
INPCI,
OPCI
VIO
Cycle Multiplexed
D10
I/O
(PU22.5)
INPCI,
OPCI
AD17
I/O
INPCI,
OPCI
VIO
Cycle Multiplexed
A17
O
OPCI
TMS
I
(PU22.5)
INPCI
VIO
---
F2
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
D24
SOUT2
CLKSEL2
PMR[23]3 = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
D225, 2 AFD#/DSTRB#
32
I/O
Buffer1 Power
Rail Configuration
(PU/PD) Type
F3
F4
F28
AMD Geode™ SC3200 Processor Data Book