Download NEC Xeon E5-2420 v2

type and processor stepping. Refer to the processor BIOS Writer’s Guide for more
information.
Figure 2-22. Platform ID Data
31
3
2
0
Processor
Flag
Reserved
Platform ID Data
• PCU Device ID: This information can be used to uniquely identify the processor
power control unit (PCU) device when combined with the Vendor Identification
register content and remains constant across all SKUs. Refer to the appropriate
register description for the exact processor PCU Device ID value.
Figure 2-23. PCU Device ID
16
31
15
RESERVED
0
PCU Device ID
PCU Device ID Data
• Max Thread ID: The maximum Thread ID data provides the number of supported
processor threads. This value is dependent on the number of cores within the
processor as determined by the processor SKU and is independent of whether
certain cores or corresponding threads are enabled or disabled.
Figure 2-24. Maximum Thread ID
31
4
Reserved
0
3
Max Thread
ID
Maximum Thread ID Data
• CPU Microcode Update Revision: Reflects the revision number for the microcode
update and power control unit firmware updates on the processor sample. The
revision data is a unique 32-bit identifier that reflects a combination of specific
versions of the processor microcode and PCU control firmware.
Figure 2-25. Processor Microcode Revision
31
0
CPU microcode and PCU firmware revision
CPU code patch revision
• Machine Check Status: Returns error information as logged by the MCA Error
Source Log register. See Figure 2-26 for details. The power control unit will assert
the relevant bit when the error condition represented by the bit occurs. For
example, bit 29 will be set if the package asserted MCERR, bit 30 is set if the
Intel® Xeon® Processor E5-2400 v2 Product Family
Datasheet Volume One
49