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Processor Configuration Registers
2.10.34
PEG_CAP—PCI Express-G Capabilities Register
This register indicates PCI Express device capabilities.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
2.10.35
0/6/0/PCI
A2–A3h
0142h
RO, RW-O
16 bits
0h
Bit
Attr
Reset
Value
15:14
RO
0h
13:9
RO
00h
RST/
PWR
Description
Reserved
Uncore
Interrupt Message Number (IMN)
Not Applicable or Implemented. Hardwired to 0.
8
RW-O
1b
Uncore
Slot Implemented (SI)
0 = The PCI Express Link associated with this port is connected to
an integrated component or is disabled.
1 = The PCI Express Link associated with this port is connected to
a slot.
BIOS Requirement: This field must be initialized appropriately if
a slot connection is not implemented.
7:4
RO
4h
Uncore
Device/Port Type (DPT)
Hardwired to 4h to indicate root port of PCI Express Root Complex.
3:0
RO
2h
Uncore
PCI Express Capability Version (PCIECV)
Hardwired to 2h to indicate compliance to the PCI Express
Capabilities Register Expansion ECN.
DCAP—Device Capabilities Register
This register indicates PCI Express device capabilities.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
0/6/0/PCI
A4–A7h
0000_8000h
RO, RW-O
32 bits
0000000h
Bit
Attr
Reset
Value
31:16
RO
0h
15
RO
1b
14:6
RO
0h
5
RO
0b
Uncore
Extended Tag Field Supported (ETFS)
Hardwired to indicate support for 5-bit Tags as a Requestor.
4:3
RO
00b
Uncore
Phantom Functions Supported (PFS)
Not Applicable or Implemented. Hardwired to 0.
2:0
RW-O
000b
Uncore
Max Payload Size (MPS)
Default indicates 128B maximum supported payload for
Transaction Layer Packets (TLP.).
Datasheet, Volume 2
RST/
PWR
Description
Reserved
Uncore
Role Based Error Reporting (RBER)
Indicates that this device implements the functionality defined in
the Error Reporting ECN as required by the PCI Express 1.1
specification.
Reserved
171