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Processor Configuration Registers 2.18.10 FEDATA_REG—Fault Event Data Register This register specifies the interrupt message data. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 2.18.11 Attr 0/0/0/GFXVTBAR 3C–3Fh 0000_0000h RW 32 bits Reset Value RST/ PWR Description 31:16 RW 0000h Uncore Extended Interrupt Message Data (EIMD) This field is valid only for implementations supporting 32-bit interrupt data fields. Hardware implementations supporting only 16-bit interrupt data may treat this field as RsvdZ. 15:0 RW 0000h Uncore Interrupt Message Data (IMD) Data value in the interrupt request. FEADDR_REG—Fault Event Address Register This register specifies the interrupt message address. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.18.12 0/0/0/GFXVTBAR 40–43h 0000_0000h RW 32 bits 0h Bit Attr Reset Value RST/ PWR Description 31:2 RW 00000000h Uncore Message Address (MA) When fault events are enabled, the contents of this register specify the DWORD-aligned address (bits 31:2) for the interrupt request. 1:0 RO 0h Reserved FEUADDR_REG—Fault Event Upper Address Register This register specifies the interrupt message upper address. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 31:0 242 Attr RW 0/0/0/GFXVTBAR 44–47h 0000_0000h RW 32 bits Reset Value 00000000h RST/ PWR Uncore Description Message upper address (MUA) Hardware implementations supporting Extended Interrupt Mode are required to implement this register. Hardware implementations not supporting Extended Interrupt Mode may treat this field as RsvdZ. Datasheet, Volume 2
