1
Download Freescale Semiconductor MCF5480 Computer Hardware User Manual
Transcript
Registers 10.3.3.1.14 Tx FIFO Read Pointer Register PCITFRPR(RW) —MBAR + 0x3850 msb 0 1 2 3 4 5 6 7 R 8 9 10 11 12 13 14 15 Reserved W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 R Reserved ReadPtr W RESET 0 0 Bits Name 0:19 Reserved 20:31 ReadPtr 0 0 0 0 0 0 0 0 0 Description Unused. Software should write zero to these bits. This value is maintained by FIFO hardware and is NOT normally written. It can be adjusted in special cases, but this disrupts data flow integrity. The value represents the Read address presented to the FIFO RAM. 10.3.3.1.15 Tx FIFO Write Pointer Register PCITFWPR(RW) —MBAR + 0x3854 msb 0 1 2 3 4 5 6 7 R 8 9 10 11 12 13 14 15 Reserved W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb 0 0 0 0 0 R Reserved WritePtr W RESET 0 0 Bits Name 0:19 Reserved 20:31 WritePtr 0 0 0 0 0 0 0 0 0 Description Unused bits. Software should write zero to these bits. Value is maintained by FIFO hardware and is NOT normally written. It can be adjusted in special cases, but this disrupts data flow integrity. Value represents the Write address presented to the FIFO RAM. This marks the end of the PCI Multi-Channel DMA Transmit Interface description. 10.3.3.2 Multi-Channel DMA Receive Interface PCI Rx is controlled by 13 32-bit registers. These registers are located at an offset from MBAR. Register addresses are relative to this offset. MPC5200B Users Guide, Rev. 1 10-34 Freescale Semiconductor
