Download Simplicity 7018H Specifications

Interrupt Vectors
Figure 2–6. Interrupt Requests
CPU Interrupt Registers and Logic
15
14
13
12
11
10
9
8
7
6
5
INT6
4
3
2
1
0
INT5 INT4 INT3 INT2 INT1
IMR
15
14
13
12
11
10
9
8
7
6
5
INT6
4
3
INTM
1
0
2
Interrupt
acknowledge
INT5 INT4 INT3 INT2 INT1
IFR
Peripheral Interrupt Extension
15
14
13
12
11
10
9
8
7
6
5
4
3
2 1
0
Interrupt controller
PIRQ0 register
Peripheral: External Interrupt
Priority
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Flag
0
Mask
XINT1CR register
2.5.1
1
Priority
Phantom Interrupt Vector
The phantom interrupt vector is an interrupt system integrity feature. If the
CPU’s interrupt acknowledge is asserted, but there is no associated peripheral
interrupt request asserted, the phantom vector is used so that this fault is handled in a controlled manner. The phantom interrupt vector is required when,
for example, the CPU executes a software interrupt instruction with an argument corresponding to a peripheral interrupt (usually INT1–INT6). Another example is when a peripheral makes an interrupt request but its INTn flag was
cleared by software before the CPU acknowledged the request. In this case,
there may be no peripheral interrupt request asserted to the interrupt controller; and therefore, the controller does not know which peripheral interrupt vector to load into the PIVR. In these two situations, the phantom interrupt vector
is loaded into the PIVR in lieu of a peripheral interrupt vector.
System Configuration and Interrupts
2-17