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8259 Interrupt
Enable
PC-AT Hardware Interrupt
(highest to lowest priority)
The PC-AT has two 8259 interrupt
controllers that allow up to 15 different
hardware devices to interrupt the PC-AT.
The first 8259 (at base port address 20H)
handles interrupts IRQ0-IRQ7. The
second 8259 (at base port address A0H)
handles interrupts IRQ8-IRQ15. The
table below lists the PC-AT hardware
interrupts by precedence (from highest to
lowest priority). Programming of the
8259 controller establishes this
precedence.
PC-AT hardware interrupts (IRQ0IRQ15) are enabled/disabled by writing to
the 8259 interrupt mask register (8259
base port address + 1).
IRQ0
(highest) .........................
IRQ1...............................................
IRQ2...............................................
IRQ8...............................................
IRQ9...............................................
IRQ10.............................................
IRQ11.............................................
IRQ12.............................................
IRQ13.............................................
IRQ14.............................................
IRQ15.............................................
IRQ3...............................................
IRQ4...............................................
IRQ5...............................................
IRQ6...............................................
IRQ7
(lowest) ..........................
Interrupt
Function
Timer
Keyboard
Reserved
Real-time clock
Reserved
Reserved
Reserved
Reserved
Math co-processor
Hard disk controller
Reserved
COM2 serial
COM1 serial
LPT2 printer
Floppy disk controller
LPT1 printer
80x86 Maskable The 80x86 processor is capable of disabling all maskable hardware interrupts (IRQ0-IRQ15).
Interrupt Enable However, it cannot disable a non-maskable interrupt (NMI), such as a memory parity error
interrupt or a divide-by-zero interrupt.
You may want to disable interrupts to protect portions of code from reentrance. For example,
if a function is being executed at the time an interrupt occurs and an interrupt service routine
(ISR) is called, the ISR may attempt to execute that same function. If this happens, the
function is said to be reentered. Keep in mind that most INT 21H functions should not be
called within an ISR because most DOS functions are non-reentrant.
PC-AT maskable hardware interrupts (IRQ0-IRQ15) are enabled/ disabled by the 80x86
instructions STI and CLI. STI sets the 80x86 interrupt flag, enabling interrupts. CLI
clears the 80x86 interrupt flag, disabling interrupts.
80x86 Interrupt
Vectors
Interrupt vectors tell the 80x86 processor where to go to handle an interrupt. Interrupt vectors
are stored in low memory. Because the 80x86 processor works with memory in 64K-byte
chunks called segments, each vector comprises two words: a segment value and an offset into
the segment.
The table below shows the vector address table for PC-AT hardware interrupts. If you decide
to let the AT6nnn use IRQ5, for example, then you must replace the vector at address
0034-0037 with the vector of your interrupt service routine (ISR).
Interrupt Number
08
09
0A
0B
0C
0D
0E
0F
70
71
72
73
74
75
76
77
Vector Address
0020 - 0023
0024 - 0027
0028 - 002B
002C - 002F
0030 - 0033
0034 - 0037
0038 - 003B
003C - 003F
01C0 - 01C3
01C4 - 01C7
01C8 - 01CB
01CC - 01CF
01D0 - 01D3
01D4 - 01D7
01D8 - 01DB
01DC - 01DF
Interrupt Description
IRQ0 (Timer)
IRQ1 (Keyboard)
IRQ2 (Reserved)
IRQ3 (COM2)
IRQ4 (COM1)
IRQ5 (LPT2)
IRQ6 (Floppy disk)
IRQ7 (LPT1)
IRQ8 (Real-time clock)
IRQ9 (Reserved)
IRQ10 (Reserved)
IRQ11 (Reserved)
IRQ12 (Reserved)
IRQ13 (Math co-processor)
IRQ14 (Hard disk)
IRQ15 (Reserved)
Fortunately, there are DOS services that permit you to easily modify the interrupt vector table.
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6000 Series Programmer's Guide