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List of Figures
1
Resolution Calculations for Conventionally Generated PWM ......................................................... 7
2
Operating Logic Using MEP ............................................................................................... 9
3
HRPWM Extension Registers and Memory Configuration ........................................................... 10
4
HRPWM System Interface
5
Required PWM Waveform for a Requested Duty = 40.5% .......................................................... 13
6
Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz
16
7
High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz
18
8
9
10
11
12
13
14
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................................
Simple Buck Controlled Converter Using a Single PWM ............................................................
PWM Waveform Generated for Simple Buck Controlled Converter ................................................
Simple Reconstruction Filter for a PWM Based DAC ................................................................
PWM Waveform Generated for the PWM DAC Function ............................................................
HRPWM Configuration Register (HRCNFG) ...........................................................................
Counter Compare A High Resolution Register (CMPAHR) ..........................................................
TB Phase High Resolution Register (TBPHSHR) .....................................................................
11
24
24
26
26
30
30
30
List of Tables
1
Resolution for PWM and HRPWM ........................................................................................ 7
2
HRPWM Registers ........................................................................................................ 10
3
Relationship Between MEP Steps, PWM Frequency and Resolution .............................................. 12
4
CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right) ......................................................... 14
5
Duty Cycle Range Limitation for 3 and 6 SYSCLK/TBCLK Cycles ................................................. 17
6
SFO Library Routines ..................................................................................................... 18
7
Factor Values .............................................................................................................. 21
8
Register Descriptions ..................................................................................................... 29
9
HRPWM Configuration Register (HRCNFG) Field Descriptions .................................................... 30
10
Counter Compare A High Resolution Register (CMPAHR) Field Descriptions
30
11
TB Phase High Resolution Register (TBPHSHR) Field Descriptions
31
12
13
14
15
4
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SFO Library Version Comparison .......................................................................................
SFO V5 Library Routines .................................................................................................
Software Functions ........................................................................................................
Technical Changes in the Current Revision ...........................................................................
List of Figures
33
34
36
41
SPRU924F – April 2005 – Revised October 2011
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