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9–22
Chapter 9: Deterministic Latency PHY IP Core
Interfaces
Table 9–18. Deterministic Latency PHY IP Core Registers (Part 3 of 3)
Word
Addr
0x082
Bits
R/W
Register Name
[31:1]
R
[0]
RW
Reserved
[31:6]
RW
pcs8g_tx_control
[5:1]
RW
tx_bitslipboundary_select
[0]
RW
tx_invpolarity
[31:1]
RW
Reserved.
pcs8g_tx_status
0x083
Description
Reserved.
—
Reserved.
Sets the number of bits that the TX bit slipper needs to slip.
To block: Word aligner.
When set, the TX interface inverts the polarity of the TX
data.
To block: 8B/10B encoder.
0x084
[0]
RW
rx_invpolarity
—
When set, the RX channels inverts the polarity of the
received data.
To block: 8B/10B decoder.
[31:4]
RW
pcs8g_rx_wa_control
Reserved.
[3]
RW
rx_bitslip
Every time this register transitions from 0 to 1, the RX data
slips a single bit.
To block: Word aligner.
0x085
[2]
RW
rx_bytereversal_enable
[1]
RW
rx_bitreversal_enable
[0]
RW
rx_enapatternalign
When set, enables byte reversal on the RX interface.
To block: Byte deserializer.
When set, enables bit reversal on the RX interface.
To block: Word aligner.
When set in manual word alignment mode, the word
alignment logic begins operation when this bit is set.
To block: Word aligner.
Dynamic Reconfiguration
As silicon progresses towards smaller process nodes, circuit performance is affected
more by variations due to process, voltage, and temperature (PVT). These process
variations result in analog voltages that can be offset from required ranges. The
calibration performed by the dynamic reconfiguration interface compensates for
variations due to PVT.
Each channel and each TX PLL has a separate dynamic reconfiguration interfaces. The
parameter editor provides informational messages on the connectivity of these
interfaces. Example 9–1 shows the messages for a single duplex channel.
Altera Transceiver PHY IP Core
User Guide
March 2012 Altera Corporation