Download SECTION 9 EXTERNAL BUS INTERFACE

ber of wait states for such access is two clocks. The accesses in these figures are valid
for both peripheral mode and slave mode.
CLKOUT
BR (input)
Use the Internal Arbiter
BG
Receive Bus Grant and Bus Busy Negated
O
O
Assert BB, Drive Address and Assert TS
BB
O
ADDR[0:31]
RD/WR
TSIZ[0:1]
BURST
BDIP
TS (input)
O
Data
TA (output)
O
Minimum 2 Wait States
DATA is valid
Figure 9-35 Peripheral Mode: External Master Reads
from MPC555 — Two Wait States
MOTOROLA
9-50
EXTERNAL BUS INTERFACE
Rev. 15 Nov 98
MPC555
USER’S MANUAL