Download Programmer`s Reference Guide

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
Table 2-15. PHB Hardware Configuration (Continued)
2
Function
Sample Pin(s)
Sampled
State
Meaning
PPC:PCI Clock Ratio
RD[10:12]
000
Reserved
100
1:1
010
2:1
110
3:1
001
3:2
101
Reserved
011
5:2
111
Reserved
Multi-Processor Interrupt Controller (MPIC)
Functional Description
The MPIC is a multi-processor structured intelligent interrupt controller.
MPIC Features:
2-50
❏
MPIC programming model
❏
Supports two processors
❏
Supports 16 external interrupts
❏
Supports 15 programmable Interrupt & Processor Task priority
levels
❏
Supports the connection of an external 8259 for ISA/AT
compatibility
❏
Distributed interrupt delivery for external I/O interrupts
❏
Direct/Multicast interrupt delivery for Interprocessor and timer
interrupts
❏
Four Interprocessor Interrupt sources
Computer Group Literature Center Web Site