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ChipScope Pro Cores Description Table 1-8: IBERT Core for the Virtex-5 FPGA GTP and GTX Transceivers Feature Description Multiple Multi-Gigabit Transceivers Up to eight transceivers can be selected per design. Pattern Generator One pattern generator per selected transceiver is used. If the basic pattern generator is chosen, the PRBS 7-bit, PRBS 23-bit, PRBS 31-bit, and User-defined patterns are enabled. If the full pattern generator is used, the above patterns are included, along with Alternate PRBS 7-bit, PRBS 9-bit, PRBS 11-bit, PRBS 15-bit, PRBS 20-bit, PRBS 29-bit, Framed Counter, and Idle patterns. While the set of patterns available for all transceivers is selected once at compile time, the particular pattern from that set can be chosen individually for each transceiver at runtime. Pattern Checker One pattern checker per selected transceiver is used. The same pattern set is available as the pattern generator. The pattern can be chosen for each transceiver at runtime. Fabric Width The FPGA fabric interface to the GTP transceiver is fixed in 2byte mode. The FPGA fabric interface to the GTX transceiver is fixed in 4-byte mode. BERT Parameters Number of bits received in error and total number of words received are gathered dynamically and read out by the Analyzer. Polarity The polarity of the TX or RX side of each transceiver can be changed at runtime. 8B/10B Encoding/Decoding Support 8B/10B encoding or decoding can be enabled at run time on a per dual-transceiver (GTP_DUAL or GTX_DUAL tile) basis. TX encoding and RX decoding are selected together. Note: If 8B/10B coding is enabled, the only valid patterns that can be used are the Framed Counter and Idle Patterns. Reset Each transceiver and each transceiver’s BER counters can be reset independently. A global reset is also available to reset all transceivers and BER counters at once. Link and Lock Status Link, DCM, and PLL lock status are gathered for each transceiver in the core. DRP Read The contents of each transceiver’s DRP space can be read independently of all others. DRP Write The contents of each transceiver’s DRP can be changed at run time, with single-bit granularity Status The entire core’s dynamic status information can be read out of the core at run time. ChipScope Pro 11.4 Software and Cores UG029 (v11.4) December 2, 2009 www.xilinx.com 47
